KR101762920B1 - One-time programmable memory apparatus - Google Patents

Abstract

The present invention relates to a technology for reducing the layout area by using one reference voltage generation circuit for the fuse-type memory device instead of using a reference voltage generation circuit for each bit line sense amplifier.
To this end, according to the present invention, in an orthopedic memory device, a voltage of a bit line on an api-cell array is compared with a reference voltage to sense bit line data, and whether data is normally programmed in the api cell array The reference voltage generating circuit for comparing the program data stored in the data driving and latch unit with the data read from the at least one OFT cell array in order to confirm the reference voltage, And a sense amplifier and a comparator which use only one of them for the column.

Description

{ONE-TIME PROGRAMMABLE MEMORY APPARATUS}

The present invention relates to a technology for implementing a low-area orthotropic memory device, and more particularly to a technique of using a single reference voltage generating circuit in a fuse-type memory device instead of using a reference voltage generating circuit for each bit- And more particularly to an orthopedic memory device capable of reducing the area.

One-Time Programmable (OTP) memory refers to a memory that can not be written any more by a single program operation and allows only read operations. The number of leads can be any number of times. There are various kinds of OTP memory. EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash (Flash) memory that stores binary information in a floating gate memory cell can be used as orthopy memory if only the program function is deleted, and EPROM (Electrically Programmable ROM) Can be used as an orthopedic memory. However, the most commonly used orthopy memory is the fuse type. The fuse method refers to a method of determining binary information according to whether a fuse is blown or not.

PMIC (Power Management IC) is a chip applied to information devices such as mobile phones, notebook computers, TVs and monitors. It converts power supplied from outside into stable and efficient power required by the system. The PMIC uses a small amount of efuse (electrical fuse) -optimized memory capable of logic-based design that does not require an additional process to perform analog trimming, to be.

A dual port eFuse OTP cell is used as an OTFT cell array of this fuse type memory intellectual property (hereinafter referred to as "e-fuse OTFT memory").

However, since one reference voltage generating circuit is used for each column in the sensing circuit of the conventional orthophilic memory device, the layout size of the fuse orthopedic memory is increased and the read current is increased .

SUMMARY OF THE INVENTION A problem to be solved by the present invention is to provide a dual-port fuse-type cell in which a relatively small-sized dual-port fuse-type cell is used in an OTFT cell array and only one reference voltage generation circuit is used in the fuse- Thereby reducing the layout area.

According to an aspect of the present invention, there is provided an OTFT device including: an OTFT cell array including a plurality of OFT cells arranged in a bipolar fashion; A control logic unit for outputting an internal control signal corresponding to the operation mode according to a read signal, a program signal, and a test mode enable signal; A row driver for receiving a row address and driving a selected row on the atopy cell array under the control of the control logic unit; A data driving and latch unit which decodes a column address to selectively drive a desired one of all columns on the atopy cell array and latches program data; And a control circuit for sensing data of a bit line by sensing a voltage of a bit line on the atopy cell array in a manner of comparing the voltage of the bit line on the atopy cell array with a reference voltage, A reference voltage generating circuit for comparing the program data stored in the driving and latching unit with the data read from the at least one atopy cell array at the present time, the reference voltage generating circuit being used for a plurality of columns on the atopy array, And a comparator.

The present invention uses a relatively small-sized dual-port fuse-optic cell in an opportunistic cell array of an orthopy-memory device and uses only one reference voltage generation circuit in the fuse-orophytic memory device, So that the layout area of the orthophilic memory device can be reduced.

Also, by implementing analog sensing, there is an effect that the sensing resistance can be reduced to a low value in the PV mode and the read mode.

1 is a block diagram of an orthopy memory device according to an embodiment of the present invention.
FIG. 2A is a circuit diagram of a dual-ported fuse-type cell array arranged in an octipole cell array.
2B is a circuit diagram of a differential pair of fuse-optic cells arranged in an orthogonal cell array.
3A is a layout image of a dual port fuse-type cell.
3B shows a layout image of a fuse-optic cell in a differential pair.
Fig. 4 is a diagram showing that the dual port fuse-optic cells are arranged in 4 rows x 8 columns.
5 is a circuit diagram showing an embodiment of a sense amplifier and a comparator.
6 is a detailed view of the reference voltage generating circuit.
7 is a layout image of the orthophilic memory device.
8A and 8B are waveform diagrams showing simulation results for an orthophilic memory device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an orthophilic memory device according to an embodiment of the present invention. As shown in FIG. 1, the orthophilic memory device 100 includes an orthophase cell array 110, a control logic section 120, a row driver ) 130, a data driving and latching unit 140, and a sense amplifier and a comparator 150.

In the OTFT array 110, an OTFT cell array of an fuse type is arranged. Here, an example is shown in which the 4-row by 8-row OTFT array is arranged in the OTFT array 110 as an example.

The control logic unit 120 outputs an internal control signal suitable for the operation mode according to the control signals A [4: 0], TM_EN, PGM, and RD.

The row driver 130 decodes the row address A [4: 3] to drive one of the four rows.

The data driving and latching unit 140 decodes a column address to selectively drive a desired one of the columns on the atopy cell array and latch program data.

The sense amplifier and the comparator 150 read the data of the bit line BL on the positive cell array 110 and determine whether the data is normally programmed in the positive cell array 110 And compares the program data stored in the data driving and latching unit 140 with the data read from the OFT cell array 110.

FIG. 2A is a circuit diagram of a dual port fuse-tap cell arranged in the OTFT cell array 110. As shown in FIG. 2A, one terminal is connected to a bit line BL, a read word line signal RWL is applied to a gate, In which one terminal is connected to the other terminal of the read transistor MN2 and the other terminal is connected to the ground terminal VSS and a write word line signal WWL is supplied to the gate of the read transistor MN2, The eighth transistor MN1 and one terminal thereof are connected to the common connection point of the other terminal of the read transistor MN2 and one terminal of the programming transistor MN1 and the other terminal is connected to the source line SL, ).

The circuit for driving the word line (Word-Line) of the atypical cell decodes the row address according to the operation mode and selectively outputs the read word line signal (RWL) and the write word line signal (WWL) Activate.

In the program mode for the eFuse, a voltage of 5 V or 0 V is supplied through the source line SL according to the data to be programmed, and the programming transistor MN1 is turned on. Accordingly, when a voltage of 5V is supplied through the source line SL, a sudden current flows to both ends of the fuse eFuse so that the eFuse is cut off. However, when a voltage of 0V is supplied, (eFuse) does not flow at both ends of the eFuse, so the eFuse maintains its original connected state.

When the eFuse is blown in the program mode, a precharge voltage of 5 V is supplied to the bit line BL in the read mode, and a precharge voltage of 5 V is applied to the gate of the read transistor MN2 ), The voltage of the bit line BL stays at 5V, which is the precharged voltage.

However, if the eFuse is kept connected in the program mode, the voltage precharged to the bit line BL in the read mode is applied to the lead transistor MN2, the eFuse and the source line SL ≪ / RTI >

Therefore, the sense amplifier connected to the bit line BL can read the high or low voltage according to the break or continuity of the eFuse. That is, in the read mode, the write word line WWL is driven by the ground voltage VSS and the read word line RWL is driven by the power supply voltage VDD. Thus, when the output data DOUT of the sense amplifier is "1" and "0" is programmed to the notch cell when "1" is programmed to the notch cell, Quot; 0 ".

FIG. 2B is a circuit diagram of a differential paired fuse-off cell, in which the dual port of FIG. 2A has a structure in which a dual-port fuse-type cell is connected in a pair as compared with a circuit of a fuse- to be. The fuse apity cell of the differential pair can receive a reference voltage through a simple peripheral circuit without requiring a reference voltage generating circuit.

FIG. 3A shows a layout image of the dual port fuse-optic cell. The cell size is 20.555 占 퐉 占 5.09 占 퐉 (= 104.625 占 퐉 ² ). 3B shows a layout image of the fuse-optic cell in which the differential pair has a cell size of 17.02 mu m x 11.26 mu m (= 191.6452 mu m ² ), and the dual port is twice the size of the fuse-optic cell.

In view of this, it is preferable that the dual port type fuse type cell as shown in FIG. 2A uses the fuse type cell.

The main features of the orthophilic memory device 100 are shown in Table 1 below. Here, the above-described opportunistic cell array 110 will be described by taking as an example a configuration composed of 4 rows x 8 columns. This fuse-link uses p-type polysilicon (Co-silicide), in which n-type polysilicon is blown better than fuse. The operation mode of the orthophilic memory device 100 is a program mode, a read mode, and a program-verify-read (PVR) mode. The program bit and the read bit of the orthophilic memory device 100 are 1 bit and 8 bits, respectively, and the program time is 20 microseconds. The power supply voltage used is VDD. When the VDD voltage is in the program mode, 5.5V may be used to supply sufficient program power to the fuse link, and 2V to 5.5V may be used in the lead mode. The device used in the orthophilic memory device 100 is a 5V MOS transistor.

FIG. 4 exemplarily illustrates that the dual-port fuse-type cells as shown in FIG. 2A are arranged in 4 rows by 8 columns (32 bits) in the OTFT array 110. Here, the read word lines RWL [3: 0], write word lines WWL [3: 0] and the ground line VSS are routed in the row direction and the source lines SL [7: 0] and bit lines BL [ It can be seen that it is routed in the column direction.

The row driver 130 decodes the row address under the control of the control logic 120 and outputs the row address of the row of the OFT cell array 110 Drive one. The column decoder included in the data driving and latching unit 140 decodes the column address under the control of the control logic unit 120 to drive the corresponding source line. The data driving and latching unit 140 transmits the input data DIN to the atopy cell array 110. In this state, the data driving and latching unit 140 activates the program signal PGM from 0 V to VDD. Thereby, the corresponding apical cell is programmed.

When the data driving and latching unit 140 activates the read signal RD to VDD, the output data DOUT [7: 1] after the access time has elapsed, 0] is output through the data driving and latching unit 140 and the sense amplifier and the comparator 150. At this time, the program signal (PGM) signal should be kept in a "low" state.

It is necessary to test whether the data is normally programmed in the OTFT array 110. [ However, since the number of pins allocated to the OTIF memory device (PMIC chip) 100 is limited, it is difficult to read OTP read data of 8 bits or more. To solve such a problem, a program-verify-read (PVR) mode is continuously performed after the program mode is performed. At this time, in the sense amplifier and comparator 150, the comparator compares the program data latched in the internal latch with the read data of the selected api cell in the read mode by using a dynamic pseudo-NMOS logic circuit, And outputs the result as a pass fail bar signal PFb. For example, when the comparator compares all bits of PD [7: 0] and DOUT [7: 0] with each other, it means that the bits are normally programmed. Therefore, the pass fail bar signal PFb is set to '1 ', And outputs' 0' if one or more of the 8 bits do not match.

5 is a circuit diagram showing an embodiment of the sense amplifier and the comparator 150. The bit line controller 151, the sense amplifier 152, the RS latch 153 and the output buffer 154, .

The bit line control unit 151 includes a PMOS transistor MP51 having one terminal connected to the power supply voltage VDD and a gate supplied with the bit line load bar signal BL_LOADb and the other terminal connected to the other side of the PMOS transistor MP51 A resistor R51 whose one terminal is connected to the bit line BL and one terminal is connected to the bit line BL while the other terminal is connected to the ground terminal VSS and a bit line precharge signal And an NMOS transistor MN51 to which a BL_PCG is supplied.

The sense amplifier 152 is composed of PMOS transistors MP52 and MP53 and NMOS transistors MN52 to MN56 and senses the voltage by comparing the voltage of the bit line BL with the reference voltage VREF, A PMOS transistor MP54 which is turned on by the sense amplifier enable signal SAEN in the standby mode and precharges the node N1 to the power supply voltage VDD, And a PMOS transistor MP55 which is turned on by the sense amplifier enable signal SAEN in the standby mode and precharges the node N2 to the power supply voltage VDD.

The RS latch 153 includes NOR gates NOR51 and NOR52 for latching the voltages input through the nodes N1 and N2.

6 is a detailed circuit diagram showing an embodiment of the reference voltage generating circuit 155 for supplying the reference voltage VREF to the sense amplifier 151 of FIG. 5. As shown in FIG. 6, one terminal of the reference voltage generating circuit 155 is connected to the power supply voltage VDD A PMOS transistor MP56 having a gate connected to the bit line load bar signal BL_LOADb is connected to the other terminal of the PMOS transistor MP56 and the other terminal is connected to the output terminal of the reference voltage VREF An NMOS transistor MN57 having one end connected to the output terminal of the reference voltage VREF and the gate of which is supplied with the normal control signal PVDD_NORMAL, An NMOS transistor MN58 connected to the output terminal and supplied with a TM control signal PVDD_TM at the gate thereof, an NMOS transistor MN58 having one terminal connected to the other terminal of the NMOS transistors MN57 and MN58, (R53), (R54), phase An inverter I54 for inverting and outputting the bit line load bar signal BL_LOADb is connected in common to the other terminals of the resistors R53 and R54 and the other terminal is connected to the ground terminal VSS An NMOS transistor MN59 whose gate is connected to the output terminal of the inverter I54 and an NMOS transistor MN59 whose one terminal is connected to the output terminal of the reference voltage VREF and the bit line precharge signal BL_PCG is supplied to the gate thereof. (MN60).

The operation of the sense amplifier and the comparator 150 will be described in detail with reference to FIGS. 5 and 6. FIG.

In the stand-by state, the bit line precharge signal BL_PCG is held at 0V, and the bit line load bar signal BL_LOADb is maintained at the level of the power supply voltage VDD. In this state, the line to which the reference voltage VREF is supplied and the bit line BL are in a floating state, and the first node N1 and the second node N2 are connected to the sense amplifier enable signal SAEN And is precharged to the power supply voltage VDD supplied through the PMOS transistors MP54 and MP55, which are turned on each other.

The NMOS transistor MN51 of the bit line control section 151 is turned on by the bit line precharge signal BL_PCG of "HIGH" when the read signal RD is activated to " Quot ;, and the NMOS transistor MN60 of the reference voltage generating circuit 155 is turned on and the line to which the reference voltage VREF is supplied is precharged to "0V ".

Then, the NMOS transistor MN2, which is a read transistor, is turned on by the read word line signal RWL.

Thereafter, when the bit line load bar signal BL_LOADb is activated to a low level at the power supply voltage VDD, the reference voltage VREF in the normal read mode is reduced to the level of the resistor R53, Is set according to the ratio of the resistance value of the resistor R52 connected in series with one resistor selected by any one of the NMOS transistors MN57 and MN58 in the resistor R54. The values of the resistors R52 to R54 are not particularly limited, but the values of the resistors R52 and R53 are 1.5 k ?, and the value of the resistor R54 is 3 k? .

Since the resistance value of the eFuse link varies depending on the presence or absence of the programming of the selected OTFT cell on the OTFT array 110, the voltage of the bit line BL is different from that of the eFuse link.

When the data of the atopy cell is sufficiently transferred to the bit line BL, the sense amplifier enable signal SAEN is activated to "high ". Accordingly, the sense amplifier 152 senses the voltage by comparing the voltage of the bit line BL with the reference voltage VREF, and outputs the voltage to the nodes N1 and N2.

At this time, the RS latch 153 latches the sensing voltage output to the nodes N1 and N2 and outputs the output data DOUT and DOUTb from the sensing data output unit 154 according to the latched voltage .

On the other hand, in consideration of the case where the resistance value of the eFuse link programmed during the data retention time is reduced, the PMOS transistor MN58 is turned to the Tm control signal PVDD_TM in the PVR (Program-Verify-Read) Is turned on so that the reference voltage VREF is set by the resistors R52 and R54 connected in series. In the read mode, considering that the resistance value of the eFuse link programmed during the retention time is reduced, the NMOS transistor MN57 is turned on with the normal control signal PVDD_NORMAL, and the resistance R52, (VREF) is set. By doing so, even if the resistance value of the programmed e-fuse fluctuates to some extent, normal data can be sensed.

FIG. 7 shows a layout image of an orthopedic memory device (32-bit eFuse OTP memory) 100 according to an embodiment of the present invention, which is designed using a Magnachip 0.18 mu m GF-ACL process. As a result of the simulation, the layout area of the orthophilic memory device 100 is 187.845 mu m X 113.180 mu m (= 0.0213 mm < 2 >) and the layout of the orthopedic memory device to which the differential paired differential pair Which is 11.6% smaller than the area of 228.525 μm × 105.435 μm (= 0.0241 mm 2).

8A and 8B are waveform diagrams showing simulation results of the orthopy memory device 100 according to the embodiment of the present invention. The voltage of the reference voltage VREF and the voltage of the bit line BL are precharged to 0V by the bit line precharge signal BL_PCG of the "high" state when the read signal RD is activated to the "high" state. Then, when the read word line signal RWL is activated at a high level and the bit line load bar signal BL_LOADb is activated at a low level, a reference voltage VREF is thereby generated, BL. When the data of the cell is sufficiently transmitted to the bit line BL, the sense amplifier enable signal SAEN is activated to be "High ", and the sense amplifier 152, the RS latch 153 and the output buffer 154, The D-type flip-flop (DF / F) circuit of FIG. 1 senses the bit line (BL) voltage by comparing it with the reference voltage VREF and generates the corresponding output data DOUT.

Table 2 below shows simulation results for the read current when a bit line sense amplifier according to the prior art is used and Table 3 shows the results of the sense amplifier 152 according to the embodiment of the present invention. And the read current is simulated using the test circuit shown in FIG. Referring to [Table 2] and [Table 3], as compared with the prior art in which the reference voltage generating circuit is used for every eight columns, one reference voltage generating circuit 155 ), It can be seen that the lead current can be reduced from a maximum of 6.399 mA to 3.887 mA.

Table 4 below shows simulation results of a program-verify-read (PVR) mode for an orthotropic memory device 100 according to an embodiment of the present invention, (read) mode. As a result of the simulation, it was confirmed that the sensing resistance in the VW mode and the lead mode in the Worst condition were 9 kΩ and 5 kΩ, respectively. In the case of using the conventional technique under the same conditions, it was confirmed that the sensing resistances in the FV and MOD modes were 61 k OMEGA and 21 OMEGA, respectively. In the case of a differential eFuse OTP cell designed for lowering the sensing resistance, the simulation results in the worst condition show that the sensing resistance values in the VB mode and the lead mode are 11 k ?, 5 k? appear. In order to design the fuse sensing resistor of the dual port fuse type at several k [Omega], as can be seen from the simulation result of the sensing resistance described above, digital sensing is impossible and the voltage of the reference voltage VREF is compared with the voltage of the bit line BL It is preferable to use an analog sensing method.

Although the preferred embodiments of the present invention have been described in detail above, it should be understood that the scope of the present invention is not limited thereto. These embodiments are also within the scope of the present invention.

100: OTFT memory device 110: OTFT cell array
120: control logic section 130: low driver
140: Data driving and latching unit 150: Sense amplifier and comparator
151: bit line control unit 152: sense amplifier
153: RS latch 154: output buffer

Claims (6)

An orthotropic cell array in which an eutectic cell array of a fuse type is arranged;
A control logic unit for outputting an internal control signal corresponding to the operation mode according to a read signal, a program signal, and a test mode enable signal;
A row driver for receiving a row address and driving a selected row on the atopy cell array under the control of the control logic unit;
A data driving and latch unit which decodes a column address to selectively drive a desired one of all columns on the atopy cell array and latches program data; And
The data of the bit line is read by sensing the voltage of the bit line on the atopy cell array in comparison with the reference voltage, And comparing whether the program data stored in the latch unit and the data currently read in the atopy cell array coincide with each other,
And a sense amplifier and a comparator that use only one reference voltage generating circuit for generating the reference voltage for a plurality of columns on the atopy array.
2. The method of claim 1,
A transistor having one terminal connected to the bit line and a read word line signal supplied to a gate;
A program transistor in which one terminal is connected to the other terminal of the read transistor, the other terminal is connected to the ground terminal, and a write word line signal is supplied to the gate; And
A dual port having an e-fuse having one terminal connected to a common connection point of the other terminal of the read transistor and one terminal of the programming transistor and the other terminal connected to a source line on the atopy cell array, And a memory for storing the data.
2. The apparatus of claim 1, wherein the sense amplifier and the comparator
A sense amplifier unit for sensing the voltage of the bit line by comparing the reference voltage with the reference voltage and outputting the voltage to the first node and the second node;
A fourth PMOS transistor which is turned on by a sense amplifier enable signal in a standby mode and precharges the first node to a power supply voltage; And
And a fifth PMOS transistor that is turned on by the sense amplifier enable signal in the standby mode and precharges the second node to the power supply voltage.
4. The apparatus of claim 3, wherein the orthophilic memory device
And an RS latch having a first input terminal connected to the first node and a second input terminal connected to the second node.
2. The apparatus of claim 1, wherein the sense amplifier and the comparator
A first PMOS transistor having one terminal connected to a power supply voltage and a gate supplied with a bit line load bar signal;
A first resistor having one terminal connected to the other terminal of the first PMOS transistor and the other terminal connected to the bit line; And
And a bit line control unit having an NMOS first NMOS transistor having one terminal connected to the bit line and the other terminal connected to a ground terminal and a gate supplied with a bit line precharge signal. Device.
2. The semiconductor memory device according to claim 1, wherein the reference voltage generating circuit
A sixth PMOS transistor having one terminal connected to the power supply voltage and a gate supplied with a bit line load bar signal;
A second resistor having one terminal connected to the other terminal of the sixth PMOS transistor and the other terminal connected to the output terminal of the reference voltage;
A seventh NMOS transistor having one terminal connected to an output terminal of the reference voltage and a gate supplied with a normal control signal;
An eighth NMOS transistor having one terminal connected to an output terminal of the reference voltage and a gate supplied with a Tm control signal;
A third resistor and a fourth resistor each having one terminal connected to the other terminal of the seventh NMOS transistor and the eighth NMOS transistor and the other terminal connected to each other;
An inverter for inverting and outputting the bit line load bar signal;
A ninth NMOS transistor having one terminal commonly connected to the other terminal of the third resistor and the fourth resistor, the other terminal connected to the ground terminal, and a gate connected to the output terminal of the inverter; And
And a tenth NMOS transistor having one terminal connected to an output terminal of the reference voltage and a gate supplied with a bit line precharge signal.

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