KR20140003533A - Iii-v semicondcutor structures with diminished pit defects and methods for forming the same - Google Patents

Abstract

Embodiments relating to semiconductor structures and methods of manufacturing the same are disclosed. In some embodiments, the methods can be used to fabricate semiconductor structures of III-V materials such as InGaN. The In-III-V semiconductor layer is grown to an indium concentration higher than the saturation period by generating a super-saturation period by controlling growth conditions such as the temperature of the growth surface, and the In-III-V semiconductor layer is compared with the saturation period. It will grow to have a lower density of V-pits.

Description

III-V semicondcutor structures with diminished pit defects and methods for forming the same}

Embodiments of the present invention generally relate to III-V semiconductor structures and methods of forming III-V semiconductor structures.

For example, III-arsenides (eg, indium gallium arsenide (InGaAs)), III-phosphides (eg, indium gallium phosphide (InGaP) and III-nitrides (eg III-V semiconductor materials, such as indium gallium nitride (InGaN), can be used in a variety of electronic device structures As some exemplary electronic devices, switching structures (eg, transistors, etc.), light emitting structures (E.g., laser diodes, laser light emitting diodes (LEDs), etc.), light receiving structures (e.g., waveguides, splitters, mixers, photodiodes, solar cells) cells, solar subcells, and / or microelectromechanical system structures (eg, accelerometers, pressure sensors, etc.), etc. Electronic device structures including such III-V semiconductor materials Various types of applications For example, such device structures can often be used to generate radiation (eg, visible light) at one or more various wavelengths. Not only can be utilized in, but also can be used, for example, in media storage and recovery devices, communication devices, printing devices, spectroscopic devices, biological pathogen detection devices, image projection devices.

More specifically, the InGaN layer may initially grow "pseudomorphically" in the underlying substrate, such that the lattice parameter of the InGaN layer is grown on the underlying substrate, thereby increasing the lattice parameter of the underlying substrate. To be substantially matched, it is caused (eg, forced by atomic forces). Lattice mismatch between the InGaN layer and the underlying layer (e.g. GaN) can cause strain in the crystal lattice of the InGaN layer, and the induced strain can cause strain energy and the strain energy May increase with increased thickness of the InGaN layer. As the thickness of the InGaN layer increases with its continuous growth, the strain energy of the InGaN layer no longer grows in an irregular fashion, at a thickness generally referred to as "critical thickness". It may not and may increase until you can experience strain relaxation. Strain relaxation of the InGaN layer can lead to poor quality of the InGaN layer. For example, such deterioration of crystal quality in the InGaN layer may result in the formation of crystal defects (eg, dislocations), roughening of the InGaN layer surface, and / or heterogeneous material regions. of inhomogenous material composition).

In some cases, these defects can cause inefficiency of the device. For example, the defects may be significant enough to cause a short across the P-N junction of the LEDs or laser diodes, such that the light emitting device does not produce the desired electromagnetic energy.

In III-V semiconductor structures and methods of forming such III-V semiconductor structures, there is a need to have a reduced defect density in order to improve the quality of the device in which it is formed. In particular, with respect to III-V semiconductor structures comprising indium alloyed with other materials and methods of forming them, a relatively thick, relatively high indium concentration, or a combination thereof, reduced defects There is a need to form an indium containing layer having a density.

The problem to be solved by the present invention is to provide a semiconductor structure capable of meeting the above requirements, i.e. a semiconductor structure having a high indium concentration and having a reduced defect density (e.g., V-pit density) even for relatively thick indium containing layers. To provide.

Various embodiments of the present invention generally relate to III-V semiconductor structures and methods of forming such III-V semiconductor structures. For example, in some embodiments, the present invention includes indium gallium nitride (InGaN) structures and a method of forming InGaN structures.

Solution to the present invention is provided to introduce the selected technical idea in a simple form, which is further described in the following description with reference to some exemplary embodiments of the present invention. Means for solving the problems are not intended to define the main features or essential features of the technical spirit described in the claims, nor are they intended to be used to limit the scope of the technical spirit described in the claims.

In some embodiments, the present invention includes a method of forming a semiconductor structure, the method comprising forming a III-V semiconductor layer on a substrate and lowering V- on a growth surface of the III-V semiconductor layer. Forming an indium-III-V semiconductor layer having a pit density. The indium-III-V semiconductor layer is formed at an indium solid state concentration higher than the indium saturation period and includes a chamber temperature lower than the chamber temperature corresponding to the indium saturation period. And an indium precursor, the indium precursor, another group III element precursor, and a group V element precursor.

In further embodiments, the present invention includes a method of growing an indium gallium nitride (InGaN) layer. A Group III element precursor at Group III partial pressure is introduced into a processing chamber comprising a substrate having a III-V semiconductor layer formed thereon. A group V element precursor at group V partial pressure is introduced into the processing chamber and an indium precursor at indium partial pressure is introduced into the processing chamber. The indium-III-V semiconductor layer is formed with an indium super-saturation section in the processing chamber that includes a chamber temperature lower than the corresponding chamber temperature of the indium saturation section, resulting in a lower V-pit density and greater than the critical thickness. It is formed in thickness.

In further embodiments, the present invention includes a method of determining processing parameters for an InGaN layer. The indium saturation interval for the InGaN layer is determined based on the range of indium partial pressure for Group III element pressure in combination with the substantially constant temperature and pressure of the processing chamber. The indium super-saturation zone is determined to include a growth-surface temperature lower than that of the growth-surface temperature in the indium saturation zone, and the indium super-saturation zone is lowered at higher indium solid state concentrations. Sufficient to build feed density.

In further embodiments, the present invention includes a semiconductor structure comprising a substrate and a III-V semiconductor layer formed on the substrate. The semiconductor structure also includes an InGaN layer having a lowered V-pit density and an indium concentration in the solid state that is greater than the indium concentration in the solid state of the indium saturation section, wherein the InGaN layer has a lower chamber temperature than that of the saturation section. It is formed in the indium super-saturation section with.

Further aspects, details, and optional combinations of the components of the embodiments of the present invention will become apparent from the following detailed description.

Some embodiments of the present invention may produce a lowered V-pit density of solid state indium concentrations ranging from about 6% to 9%. Further, in some embodiments, the lowered V-pit densities can be achieved even for relatively thick InGaN layers of up to about 150 nanometers and possibly up to about 200 nanometers.

The invention will be more fully understood by reference to the following detailed description in connection with the exemplary embodiments of the invention shown in the accompanying drawings.
1 is a schematic cross-sectional view of a semiconductor structure having a substrate, a III-V semiconductor layer, and an In-III-V semiconductor layer formed thereon, showing potentials and V-pits formed therein.
FIG. 2 is a schematic isometric view showing V-pits in an In-III-V semiconductor layer. FIG.
3 is a schematic cross-sectional view of a substrate having a III-V semiconductor layer and an In-III-V semiconductor layer formed thereon, illustrating the lowered density of V-pits formed therein in accordance with one or more embodiments of the present invention. Illustrated.
FIG. 4 is a graph showing indium solid state concentrations versus indium gas state concentrations to show indium saturation intervals over a particular gaseous indium concentration.
FIG. 5 is a graph showing indium solid state concentration versus indium partial pressure showing the labeled interval of FIG. 4 and super-saturated intervals in accordance with one or more embodiments of the present invention.
6A-6C are graphs illustrating indium solid state concentration, V-bit density, and V-pit width, respectively, for indium partial pressure, in accordance with one or more embodiments of the present invention.

Although shown here, the cities are not intended to be in any way actual appearance of any particular material, apparatus, or method, and correspond to the purely ideal cities used to describe embodiments of the present invention.

It is to be understood that any reference herein using a reference to a component, such as “first”, “second”, etc., does not limit the quantity or order of such components, unless expressly stated to be limiting. do. Rather, these designations can be used herein as examples of components or as a convenient way to distinguish between two or more components. Reference to the first and second components does not mean that only two components can be used therein or that the first component must precede the second component in some way. Also, unless stated otherwise a set of components may include one or more components.

The components described herein may include a number of examples for the same component. Such components are generally referred to by an abbreviation (eg, 110), and specifically, an alphanumeric mark (eg, 110A) after the numeric display or a numeric mark (eg, 110) after the "dash". -1). In the following description, for the sake of convenience, in most cases, the member identification number starts with the number of the figures in which the components are introduced or mostly fully discussed. Thus, for example, the absent numbers in FIG. 1 will mostly be number format 1xx and the components in FIG. 4 will mostly be number format 4xx.

The following description provides specific details such as material types and process conditions in order to provide a thorough explanation regarding embodiments of the present disclosure and its implementation. However, one of ordinary skill in the art will understand that embodiments of the present disclosure may be practiced using conventional fabrication techniques without using these specific details. In addition, the description provided herein does not form an entire process flow for manufacturing a semiconductor device or system. Only the structures and those process steps necessary to understand the embodiments of the present invention are described in detail herein. The materials described herein may be formed (eg, deposited or grown) by any suitable techniques, and any of the above techniques may include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition ( PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition, physical vapor deposition (PVD), but is not limited thereto. Although the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three dimensional configurations.

As used herein, the terms “horizontal” and “vertical” define the relative positions of components or structures relative to the major plane or surface of a semiconductor structure (eg, wafer, die, substrate, etc.) , Orthogonal dimensions, which define relative positions independent of the orientation of the semiconductor structure and are interpreted for the orientation of the structure described. As used herein, the term "vertical" means and includes a dimension substantially perpendicular to the major surface of the semiconductor structure, and the term "horizontal" means a dimension substantially parallel to the major surface of the semiconductor structure.

As used herein, the term "semiconductor structure" means and includes any structure used to form a semiconductor device. For example, semiconductor structures may comprise assemblies and composite structures comprising dies and wafers (eg, carrier substrates and device substrates) and two or more dies and / or wafers integrated three-dimensionally into one another. Include. Semiconductor structures also include prefabricated semiconductor devices and intermediate structures formed during fabrication of semiconductor devices. Semiconductor structures may include conductive materials, semiconductive materials, non-conductive materials (eg, electrical insulators), and combinations thereof.

As used herein, the term “processed semiconductor structure” means and includes any semiconductor structure that includes one or more at least partially formed device structures. Processed semiconductor structures are a collection of semiconductor structures, and all processed semiconductor structures are semiconductor structures.

As used herein, the term “III-V semiconductor” refers to at least mainly one or more periodic table IIIA elements (eg, B, Al, Ga, In, and Ti) and one or more periodic table group VA elements (eg, For example, it means and includes any semiconductor material consisting of N, P, As, Sb, and Bi).

As used herein, the terms "indium gallium nitride" and "InGaN" refer to an alloy of indium nitride (InN) and gallium nitride (GaN), which have a composition ratio of In _X Ga _{1 - X} N. , Where 0 <x ≤ 1.

As used herein, the term “critical thickness” means the average total thickness of a layer of semiconductor material at which point or beyond that stops pseudomorphic growth and the layer experiences strain relaxation. .

As used herein, the term "growth surface" means any surface of a semiconductor substrate or layer on which further growth of the semiconductor substrate or layer can be performed.

As used herein, the term "potential" refers to the region of the semiconductor material in which there is an imperfection of the crystal lattice with respect to the semiconductor material, which means, for example, missing elements and crystals in the crystal structure. It can be characterized by properties such as broken bonds in the structure.

As used herein, the term "substantially" is used herein to refer to a complete result except for any imperfections generally expected in the art.

Embodiments of the invention can be applied to a wide range of III-V semiconductor materials. For example, the structures and methods of the embodiments of the present invention are double, triple, quadruple, and in III-nitrides, III-arsenides, III-phosphides and III-antimonides, and It can be applied in five forms. Specific applications relate to growing a group of III-nitride semiconductors containing indium such as indium gallium nitride (InGaN). Thus, for convenience and brevity, not limitation, the following description and figures may reflect the general properties of III-nitriles, in particular focusing on InGaN.

Experiments in III-nitride material systems show that heteroepitaxially grown InGaN layers with thicknesses above the critical thickness may experience strain relaxation to reduce strain in the crystal lattice resulting from lattice mismatch. With onset of strain relaxation in InGaN layers, an increased amount of indium may be included, which may result in a non-uniform concentration profile of indium over the thickness of the InGaN layers. For example, the InGaN layer may include increased indium content close to the growth surface of the layer. The non-uniform indium configuration of such InGaN layer may be undesirable in at least some applications.

Experiments also show that strain relaxation of the InGaN layer may cause roughening of the growth surface of the InGaN layer. Such surface roughness can be detrimental to the production of semiconductor devices using InGaN layers. Furthermore, experiments show that strain relaxation of InGaN layers can lead to an increase in the defect density of the crystalline material. Such defects may include, for example, dislocations and regions of non-uniform configuration (ie, phase separated regions).

As a non-limiting example, for InGaN (III-nitride material), InGaN layers can be heteroepitaxially deposited on a lower substrate, which has a crystal lattice that does not match that of the upper InGaN layer. Can be. For example, InGaN layers may be deposited on a semiconductor substrate comprising gallium nitride (GaN). The GaN may have a relaxed (ie substantially strain free) in-plane lattice parameter of about 3.189 kPa, and the InGaN layers, depending on the corresponding indium content content, of (7%) in the case of indium, i.e., in _{0 .07} Ga _{0 .93} N) of about 3.21 Å, (the case of a 15% indium, i.e., in _{0 .15} Ga _{0 .85} N) of about 3.24 Å, (of a 25% indium If, that is, it may have a plane lattice parameter of the relaxed in _{0 .25} Ga _{0 .75} N) of about 3.26 Å.

1 shows dislocations 132, 142 and V-pits 150 formed therein with a semiconductor material charge 130 and an indium-III-V semiconductor layer 140 formed thereon. It is a cross-sectional view schematically showing a semiconductor structure 100. The semiconductor structure 100 may be manufactured or otherwise provided to include the substrate 110. The substrate 110 forms one or more additional semiconductor material layers thereon as part of the fabrication of the indium-III-V semiconductor layer 140, and the semiconductor material layer 130, as will be described in more detail below. It may include a semiconductor material that can be used as the seed layer used.

The semiconductor material layer 130 may be attached to and carried by the substrate 110. However, in some embodiments, the semiconductor material layer 130 is a free-standing, bulk semiconductor material layer that is not disposed on or carried by the substrate or any other material. It may include.

In some embodiments, the semiconductor material layer 130 may include an epitaxial layer of semiconductor material. By way of example, and not limitation, semiconductor material layer 130 may comprise an epitaxial layer of III-V semiconductor material. As a non-limiting example, the III-V semiconductor material layer 130 may be a GaN epitaxial layer.

For example, the substrate 110 may include aluminum oxide (Al ₂ O ₃ ) (eg, sapphire), zinc oxide (ZnO), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), lithium It may be a material such as gallate (LiGaO ₂ ), lithium aluminate (LiAlO ₂ ), yttrium aluminum oxide (Y ₃ Al ₅ O ₁₂ ), or magnesium oxide (MgO).

Optionally, one or more intermediate material layers (not shown), such as another semiconductor material layer or one or more dielectric material layers, may be disposed between the semiconductor material layer 130 and the substrate 110. Such intermediate material layers may be used to bond the semiconductor material layer 130 to the substrate 110 so that it can be performed, for example, when it is impossible to form the semiconductor material layer 130 directly on the substrate 110. It can be used as a bonding layer or as a seed layer for forming a semiconductor material layer thereon. In addition, it may be desirable to bond the semiconductor material layer 130 to the substrate 110 when the semiconductor material 130 includes polar crystal orientations. In such embodiments, the bonding process may be utilized to change the polarity of the polar semiconductor material.

The figures herein are not drawn to scale, and in practice, the III-V semiconductor layer 130 may be relatively thin relative to the substrate 110.

Dislocations 132B and 132D may be formed when III-V semiconductor layer 130 is formed. As shown in FIG. 1, these dislocations may be threading dislocations that extend as the layer is formed to an increased thickness. In other words, once a dislocation occurs, the dislocation may tend to propagate as the layer is formed and thus will appear on the final surface of the III-V semiconductor layer 130 after its formation is complete.

Any of a variety of methods known in the art may be used to reduce the dislocation density of the III-V semiconductor layer 130. Such methods include, for example, epitaxial lateral overgrowth (ELO), Pendeo epitaxy, in-situ masking techniques, and the like. The semiconductor material layer 130 may be deposited using a process such as, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor stage epitaxy (HVPE).

1 also shows an additional III-V semiconductor material 140 on the III-V semiconductor layer 130. As a non-limiting example, the additional III-V semiconductor material 140 may be combined with an InGaN layer 140 or other types of III-V semiconductor materials such as gallium phosphide (GaP) and gallium arsenide (GaAs). Indium may be included. Herein, the semiconductor layer of indium in combination with the III-V semiconductor material may be referred to as an indium-III-V semiconductor material or an indium-III-V semiconductor layer 140.

InGaN alloy layers are lattice mismatched grown on a GaN template (eg, GaN 130 on sapphire 110). The more indium in InGaN layer 140, the greater the lattice mismatch between InGaN layer 140 and GaN template. In general, lattice mismatch growth (ie, mismatch between InGaN layer 140 and GaN template) involves strain relaxation when the strain energy stored in InGaN layer 140 is greater than the strain energy to nucleate dislocations. do. This lattice mismatch growth occurs in lattices arranged in cubic systems, but is more complex in materials with hexagonal crystal structures such as GaN, InGaN, or AlGaN.

In the hexagonal layers, there may be no easy gliding plane for dislocations and thus much higher strain energy may be stored in InGaN layer 140 before nucleating dislocations. When relaxation is reached, plastic relaxation occurs by growth surface modification. If the growth surface is hexagonal (0001), pit defects 150 may occur. These pit defects may appear like inverted pyramids with vertices near the potential (often threading potential) of the GaN subsurface, and are referred to as V-pits 150. As the InGaN layer 140 grows, the inverted pyramid also grows. With thick InGaN layers, the V-pits 150 can also be very large.

In general, thinner InGaN layers 140 may be grown with little or no V-pits 150. The thin layer may not reach the thickness at which strain relaxation will occur (ie, critical thickness) because the strain energy in the InGaN layer 140 increases with the layer thickness. However, for some applications a thick InGaN layer may be desirable. As a result, in conventional processing, V-pits 150 are present in thicker InGaN layers 140 and the V-pits 150 become deeper and wider as InGaN layers 140 become thicker. All.

In addition to thinner InGaN layers, it is generally possible to form a relatively V-pit free InGaN layer if the indium concentration is kept relatively low compared to the gallium concentration. However, many applications require thick InGaN layers, high indium concentrations in InGaN layers, or a combination thereof, all of which can result in deep, wide V-pits.

As mentioned, the V-pits are often dislocations, such as threading potentials, represented by reference numbers 132B and 132D in III-V semiconductor layer 130 and by reference numbers 142A and 142E in indium-III-V semiconductor layer 140. Starts from. V-pits 150A, 150B, 150D, and 150E are formed from these dislocations 132 and grow larger as the indium-III-V semiconductor layer 140 grows. V-pits may also start as intrinsic potential, such as V-pit 150C.

These deep V-pits 150 may cause holes after further processing for layer transfer, ie processing through smart-cut and bonding processes. The V-pits 150 can also locally change the ion implantation depth and cause splitting defects. In addition, further regrowth after layer transfer onto the pitted InGaN layers results in very deep pits that are detrimental to the LED device. For example, if V-pit 150 occurs across the entire InGaN layer 140, the V-pit may short out the diode portion of the LED device and the device performs the intended function. Makes it impossible to do.

FIG. 2 schematically shows an isometric view showing V-pit 150 as a non-limiting example in indium-III-V semiconductor layer 140 as a non-limiting example. The hexagonal shape of the opening on the growth surface 148 is due to the growth of the crystal structure of InGaN. Furthermore, the V-pit sidewalls 152 are prepared from the vertex 155 where the V-pit 150 begins to form due to the growth of the crystal structure, so that the V-pit 150 generally has a width 156. ) Has a fixed ratio from depth to depth 154. Thus, the depth 154 of the V-pit 150 can be accurately estimated based on the width 156 of the V-pit.

Embodiments of the present invention may reduce the number, size, or combination thereof of the V-pits 150 formed when the indium-III-V semiconductor layer 140 is formed on the III-V semiconductor layer 130. Can be. This reduction in V-pits 150 is also referred to herein as "diminished V-pit density" and "lower density of V-pit". Thus, the lowered V-pit density may be a combination of fewer V-feet in a given surface area, smaller V-feet in a given surface area, or less V-feet and smaller V-feet in a given surface area. May be referred to.

Although certain specific theories for V-pit formation have not been established, Shijijiri's paper (M. Shiojiri, CC Chuo, JT Hsu, JR Yang, H. Saijo, J. Appl. Phys. 99, 073505) (2006) suggest that the growth rate is different compared to the {0001} basal plane of growth surface 148 at {10-11} planes, which are V-pit sidewalls 152. The {10-11} planes of the V-pit sidewalls 152 may also have a higher sticking coefficient for Indium than the {0001} base plane of the growth surface 148. Thus, embodiments of the present invention may saturate the indium concentration on the {0001} base surface of the growth surface 148 of the formed solid material by increasing the indium content in the gas phase during processing. While allowing a higher indium concentration on the {10-11} faces of the V-pit sidewalls 152 to promote growth of InGaN on the V-pit sidewalls, thereby reducing the V-pit density. Can be.

3 is a schematic cross-sectional view of a semiconductor substrate 110 having a semiconductor material layer 130 and an indium-III-V semiconductor material layer 140 formed thereon, the V formed in accordance with one or more embodiments of the present invention. The lower density of the feet is shown. As shown in FIG. 1, the semiconductor structure 100 may be manufactured or otherwise provided to include the substrate 110. Substrate 110, semiconductor material layer 130, and indium-III-V semiconductor material layer 140 are similar to those described in FIG. 1.

However, FIG. 3 shows conventional V-pits 152A, 152B, 152C (ie, V-pits that may be formed when conventional processing is used). 3 also shows smaller V-pits 158A, 158B, 158C, which results in lowered V-pits density in accordance with one or more embodiments of the present invention. Lowered V-pits 158A, 158C have more V-pits resulting from threading dislocations 132B, 132C, respectively, compared to V-pits 152A, 152C formed using conventional processing. It shows growth at low speed (ie, not larger). Lowered V-pit 158B shows a smaller V-pit compared to V-pit 152B, which may be formed directly from the potential using conventional processing.

4 is a graph showing the indium concentration in the gas state versus the indium concentration in the solid state, showing an indium saturation interval for a predetermined concentration of indium in the gas state. 4 can be constructed through experiments in a processing chamber at a relatively constant temperature, a relatively constant pressure, a relatively constant total gas flow, and a relatively constant rotational speed of the wafer. Based on the particular gallium flow rate, the indium flow rate can be varied by changing the gaseous indium influence, as shown on the x-axis. The content of indium in the solid state to develop an InGaN layer is shown on the y-axis as a function of the indium content in the gas state.

In some embodiments, the indium precursor for the formation of the InGaN layer may include, for example, trimethylindium (TMI), triethylindium (TEI), or a combination thereof. In some embodiments, the gallium precursor for the formation of an InGaN layer may include, for example, triethylgallium (TEG) or other suitable material. In some embodiments, the nitrogen precursor for the formation of the InGaN layer may include, for example, ammonia (NH ₃ ) or other suitable material.

Thus, in one embodiment:

% Indium in gas = 100 * (TMI flow / (TMI flow + TEG flow))-(1)

Initially, as shown in section 410A, as the indium content in the gaseous state increases, the indium content in the solid state increases proportionally. However, upon reaching the inflection point 410B, as shown in section 410C, an additional increase in the indium content of the gaseous state does not cause an increase in the indium content of the solid state. Here, this gaseous indium concentration span without a proportional increase in indium concentration to the solid state will be referred to as an indium saturation regime.

FIG. 5 is a graph of indium partial pressure versus solid state indium concentration, showing the super-saturation intervals and the saturation interval of FIG. 4 in accordance with one or more embodiments of the present invention. FIG.

As will be appreciated by those skilled in the art, the gas flow rate in the processing chamber is related to the partial pressure due to each of the other gases in the processing chamber. Therefore, the indium concentration in the gaseous state can be expressed as follows.

% Indium in gas = 100 * (P _TMI / (P _TMI + P _TEG ))-(2)

In other words, the relationship between the indium partial pressure (P _TMI ) to the group III total partial pressure (P _TMI + P _TEG ), which is a combination of indium partial pressure and gallium partial pressure, can be determined without difficulty. For clarity of explanation, most of the description herein relates to partial pressures; However, one of ordinary skill in the art will understand that the above descriptions may also apply to related flow velocities.

Of course, other inert gases (eg, nitrogen), and other reactants, such as, for example, dopants, may be in the reaction chamber. As non-limiting examples, the N-dopant may comprise a silicon containing vapor such as, for example, silane (SiH ₄ ), and the P-dopant may be, for example, bis (chloropentadienyl) magnesium (Bis). and magnesium-containing vapors such as cyclopentadienylmagnesium (Cp ₂ Mg).

In FIG. 5, the y-axis shows the indium content in the solid state (also referred to as the indium concentration in the solid state) as a function of the x-axis showing the indium partial pressure (also referred to as the indium concentration in the gaseous state).

The sections 510A, 510C are saturated with a proportional increase 510A of the solid indium concentration relative to the indium concentration in the gaseous state, and the subsequent indom concentration remains relatively constant as the indium concentration in the gaseous state increases. Interval 510C is shown.

Line 520 shows the indium super-saturation section in which a higher solid indium concentration can be obtained compared to the saturation section. Thus, as used herein, the term indium super-saturation interval is configured to establish an indium concentration in the formed solid state semiconductor layer that is higher than that formed in the solid state semiconductor layer using the saturation interval described above. Means the conditions in the chamber.

As a non-limiting example, the saturation interval may be defined as a specific chamber pressure, growth surface temperature, III-element precursor partial pressure, V element precursor partial pressure, and indium precursor partial pressure. The higher partial pressure or concentration of the indium precursor compared to that of the saturation section can build up a super-saturation section that forms a higher indium concentration in the formed semiconductor layer.

As other non-limiting examples, the saturation defined by a particular growth surface temperature, a particular growth surface temperature, a certain chamber pressure, a certain wafer rotation rate, and a specific partial pressure combination of an indium precursor, a Group III element precursor, and a Group V element precursor In the section, the reduction of the growth surface temperature may create a super-saturation section, resulting in a solid state growth condition that establishes an indium concentration of the formed semiconductor layer, which is higher than that obtainable in the saturation section. have. Similarly, indium super-saturation zones can be established when increasing chamber pressure or changing wafer rotational speed while maintaining temperature at the saturation zone temperature.

At line 520, to build an indium super-saturation interval, chamber parameters such as, for example, chamber pressure and wafer rotational speed can be kept relatively constant, and the temperature can be reduced. The temperature can be determined by the chamber temperature or the growth-surface temperature. As a non-limiting example, the chamber temperature for the sections 510A, 510C is about 839 ° C and the chamber temperature at line 520 is about 811 ° C. In addition, the relative concentrations between Group V precursors and Group III precursors (eg, indium precursors in combination with gallium precursors) remain relatively constant at the rate of V / III = 3560. In other words, in one embodiment, as line 520 moves from left to right, the partial pressure for TEG can remain relatively constant, and as the TMI partial pressure increases, the partial pressure for ammonia increases proportionally. This is to maintain the V / III ratio at about 3560.

As a non-limiting example, line 530 may be constructed with a chamber temperature of about 811 ° C. and a Group V partial pressure (eg, a partial pressure of ammonia) that remains substantially constant with varying indium partial and group III partial pressures. Can be. In other words, in one embodiment, as line 530 moves from left to right, the partial pressure for TMI increases while the partial pressures for TEG and ammonia may remain constant.

More specifically, with reference to FIGS. 3 and 5, the flow of the indium precursor to InGaN layer 140 allows the incoming flow of indium species to act on growth surface 148 and V-pit sidewalls 152. flux). Indium can be highly volatile. At the surface, the TMI will break down and release metals (eg, indium) that may be incorporated into the solid layer or dispersed as vapor. At higher temperatures, the higher the temperature, the more likely the metal is to be dispersed without dispersion.

Thus, there is a trade-off between the incorporation of indium into InGaN layer 140 and the desorption of indium from InGaN layer 140 (also referred to herein as desorption flow rate). By dropping temperature, or by increasing pressure, incorporation to increase the solid state concentration of indium in InGaN layer 140 may be advantageous. Furthermore, the saturation interval can reach the growth surface 148, the V-pit sidewalls 148, with different growth facets, and be modified at higher growth rates than the growth surface 148. This can result in a lower V-pit density.

6A-6C are graphs illustrating solid state concentration, V-pit density, and V-pit width, respectively, of indium, all related to indium partial pressure in accordance with one or more embodiments of the present invention.

As can be seen in line 610 of FIG. 6A, as the indium concentration in the gaseous state increases, the indium concentration in the solid state also increases to an indium concentration of about 94%. At this point, an increase in gaseous concentration results in a lower solid state concentration.

As can be seen in line 620 of FIG. 6B, as the indium concentration in the gaseous state increases, the V-pit density also increases to an indium concentration of about 94%. At this point, an increase in gaseous concentration results in a lower solid state concentration.

However, as shown by line 630 in FIG. 6C, the V-pit width decreases as the indium concentration in the gaseous state increases. The points in FIG. 6C show the average V-feet width and the upper bars 632 and the lower bars 634 show 3-sigma dispersion points for the V-feet width. As a result, as the indium partial pressure increases, the lowered V-pit density may be one of fewer V-pits per predetermined area, smaller V-pits, or a combination of the size and number per predetermined area of such V-pits. Can be observed.

A method of measuring V-pits with an atomic force microscope (AFM) to measure the pit width is preferred, since the AFM tip may not be sharp enough to penetrate the entire depth of the V-pits, so that the depth can be accurately measured. Because it can. Based on crystallographic considerations (eg, the angle between (10-11) and (0001) planes), the pit depth can be calculated from the pit width. (J.E.Norrup, L.T. Romano, J. Neugebauer, Appl. Phys. Lett. 74 (6), 2319 (1999)

It should also be noted that for very thin InGaN layers, V-pits may be present but not sensed because their width may be less than the resolution of the AFM.

As mentioned above, many applications require thick InGaN layers, high indium concentrations in the InGaN layers, or a combination thereof, all of which can lead to deep and wide V-pits. Some embodiments of the present invention may produce a lowered V-pit density of solid state indium concentrations ranging from about 6% to 9%. Further, in some embodiments, the lowered V-pit densities can be achieved even for relatively thick InGaN layers of up to about 150 nanometers and possibly up to about 200 nanometers.

Claims (15)

Forming a III-V semiconductor layer on the substrate;
Forming an indium-III-V semiconductor layer on the growth surface of the III-V semiconductor layer at an indium solid state concentration higher than the indium saturation period, the chamber temperature being lower than the chamber temperature corresponding to the indium saturation period. At least combining the indium precursor, the indium precursor with another Group III element precursor, and a Group V element precursor in a processing chamber comprised of an indium super-saturation section to form an indium-III-V semiconductor layer. The method of forming a semiconductor structure. The method of claim 1,
And forming the indium-III-V semiconductor layer to a thickness thicker than a critical thickness. The method of claim 1,
Forming the indium-III-V semiconductor layer may comprise forming a V-pit of the indium-III-V semiconductor layer relative to a desorption flux of indium from the growth surface of the indium-III-V semiconductor layer. Reducing the desorption flow rate of indium from the sidewalls. The method of claim 1,
Forming the indium-III-V semiconductor layer further includes increasing the incorporation of indium in the V-pit sidewalls as compared to the incorporation of indium in the growth surface of the indium-III-V semiconductor layer. Comprising, a method of forming a semiconductor structure. 5. The method of claim 4,
Increasing the incorporation of the indium in the V-pit sidewalls includes at least one of reducing the chamber temperature, increasing chamber pressure, and increasing indium partial pressure. Way. The method of claim 1,
Forming the indium-III-V semiconductor layer further comprises increasing an indium partial pressure in the processing chamber relative to an overall group III partial pressure. The method of claim 1,
Forming the indium-III-V semiconductor layer comprises forming an indium gallium nitride (InGaN) layer. The method of claim 1,
Further comprising selecting the group V element precursor to comprise ammonia. The method of claim 1,
And selecting the indium precursor to include trimethylindium. The method of claim 1,
And selecting the group III element precursor to comprise triethylgallium. The method of claim 1,
Forming the indium-III-V semiconductor layer further comprises increasing the indium partial pressure in the processing chamber relative to the Group III total partial pressure. A semiconductor structure obtained by the method according to any one of claims 1 to 11,
Board;
A III-V semiconductor layer formed on the substrate; And
A semiconductor structure comprising an InGaN layer having an indium solid state concentration higher than the indium solid state concentration from an indium saturation interval. The method of claim 12,
And the InGaN layer comprises an indium concentration of about 6% to about 9%. The method of claim 12,
And the InGaN layer comprises a total thickness of at least about 150 nm. The method of claim 12,
The InGaN layer further comprises a thickness thicker than the critical thickness.

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