JP5961633B2 - III-V semiconductor structure with reduced pit defects and method for forming the same - Google Patents

Description

  Embodiments of the present invention generally relate to III-V semiconductor structures and methods of forming III-V semiconductor structures.

  Group III-V semiconductor materials such as group III-arsenides (eg indium gallium arsenide (InGaAs)), group III-phosphides (eg indium gallium phosphide (InGaP)), and group III-nitrides (eg indium gallium arsenide) Nitride (InGaN)) and the like may be used in multiple electronic device structures. Some examples of electronic devices include switching structures (eg, transistors), light emitting structures (eg, laser diodes, light emitting diodes, etc.), light receiving structures (eg, waveguides, splitters, mixers, photodiodes, solar cells). , Solar cell subcells, etc.), and / or microelectromechanical system structures (eg accelerometers, pressure sensors, etc.) Such electronic device structures comprising III-V semiconductor materials can be used in a variety of applications. For example, such device structures are often used to generate radiation (eg, visible light) at one or more of various wavelengths. The light emitted by such structures can be used not only in lighting applications, but also in media storage and retrieval applications, communication applications, printing applications, spectroscopic applications, biological agent detection applications, and image projection applications, etc. Can also be used.

  More specifically, the InGaN layer can initially grow “pseudomorphically” with respect to the underlying substrate, and the lattice parameter of the InGaN layer is the lattice parameter of the underlying substrate that serves as the growth base. Are substantially aligned with each other (eg, by interatomic forces). Mismatching of the lattice between the InGaN layer and the underlying substrate (eg GaN) may induce strain in the crystal lattice of the InGaN layer, and this induced strain increases with increasing InGaN layer thickness. Possible strain energy can be induced. As the thickness of the InGaN layer increases as it continues to grow, the strain energy in the InGaN layer undergoes strain relaxation as the InGaN layer no longer grows pseudomorphically at what is commonly referred to as the “critical thickness”. You can rise until you get. Due to strain relaxation in the InGaN layer, the quality of the InGaN layer can be degraded. For example, such a decrease in crystal quality in the InGaN layer can include the formation of crystal defects (eg, dislocations), roughening of the surface of the InGaN layer, and / or formation of regions of inhomogeneous material composition.

  In some examples, these defects can invalidate the device. For example, the defect may be a significant defect that causes a short circuit between the PN junctions of a light emitting diode (LED) or laser diode, making it impossible for the light emitting device to generate the desired electromagnetic energy.

  There is a need for group III-V semiconductor structures and methods for forming such group III-V semiconductor structures that have a low defect density to improve the quality of the devices formed therewith. In particular, indium is alloyed with other materials to form an indium-containing layer with a reduced defect density, which is relatively thick, has a relatively high indium concentration, or a combination thereof, III-V There is a need for group semiconductor structures and methods for forming such III-V semiconductor structures.

M. Shiojiri, C.C.Chuo, J.T.Hsu, J.R.Yang, H. Saijo, J. Appl.Phys. 99, 073505 (2006) J.E.Northrup, L.T.Romano, J. Neugebauer, Appl.Phys. Lett. 74 (6), 2319 (1999)

  Various embodiments of the present invention generally relate to III-V semiconductor structures and methods for forming such III-V semiconductor structures. For example, in some embodiments, the present invention includes an indium gallium nitride (InGaN) structure and a method of forming an InGaN structure.

  This summary is further described in the following detailed description of some example embodiments of the invention and is provided to briefly introduce the selection of concepts. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

  In some embodiments, the present invention includes forming a group III-V semiconductor layer on a substrate and an indium-III- having a reduced V pit density on the growth surface of the group III-V semiconductor layer. Forming a group V semiconductor layer, and a method of forming a semiconductor structure. The indium-III-V semiconductor layer is at least different from the indium precursor, the indium precursor, in a processing chamber configured to have an indium supersaturation situation having a chamber temperature less than the chamber temperature corresponding to the indium saturation situation. By combining a group III element precursor and a group V element precursor, an indium solid phase concentration exceeding the indium saturation state is formed.

  In a further embodiment, the present invention includes a method of growing an indium gallium nitride (InGaN) layer. A group III element precursor of group III partial pressure is introduced into a processing chamber that includes a substrate on which a group III-V semiconductor layer is formed. A V group partial pressure group V element precursor is introduced into the process chamber and an indium partial pressure indium precursor is introduced into the process chamber. The indium-III-V semiconductor layer has a thickness that exceeds the reduced V pit density and critical thickness by developing an indium supersaturation situation in a processing chamber having a chamber temperature that is less than the chamber temperature corresponding to the indium saturation situation. Is formed.

  In a further embodiment, the present invention includes a method for determining processing parameters for an InGaN layer. Indium saturation conditions are determined for InGaN layers over a range of indium partial pressures for combined Group III element pressure and a substantially constant temperature and process chamber pressure. An indium supersaturation situation having a growth temperature below the growth surface temperature of the indium saturation situation is determined, and the indium supersaturation situation is sufficient to develop a reduced V pit density at higher indium solid phase concentrations.

  In a further embodiment, the present invention includes a semiconductor structure comprising a substrate and a III-V semiconductor layer formed on the substrate. The semiconductor structure also includes an InGaN layer having a low V pit density and an indium solid phase concentration that is greater than the indium solid state concentration due to the indium saturation condition, the InGaN layer being less than the chamber temperature of the indium saturation condition. Formed in an indium supersaturated situation with chamber temperature.

  Further aspects, details, and alternative combinations of elements of embodiments of the present invention will become apparent from the following detailed description.

The invention will be more fully understood by reference to the following detailed description of example embodiments of the invention illustrated in the accompanying drawings.
Schematic cross-sectional view of a semiconductor structure having a substrate, a III-V semiconductor layer, and an In-III-V semiconductor layer formed thereon, showing dislocations and V pits formed therein It is. It is a schematic isometric view showing a V pit in an In-III-V group semiconductor layer. A reduced density V pit is shown having a III-V semiconductor layer and an In-III-V semiconductor layer formed thereon, and formed therein according to another embodiment of the present invention. 1 is a schematic cross-sectional view of a substrate. 6 is a graph of indium solid phase concentration versus indium vapor phase concentration to show indium saturation for a given vapor phase indium concentration. 5 is a graph of indium solid phase concentration versus indium partial pressure showing the saturation situation of FIG. 4 and the supersaturation situation according to one or more embodiments of the present invention. 4 is a graph showing indium solid phase concentration versus indium partial pressure according to one or more embodiments of the present invention. 4 is a graph showing V pit density versus indium partial pressure according to one or more embodiments of the present invention. 4 is a graph showing V pit width versus indium partial pressure according to one or more embodiments of the present invention.

  The figures presented herein are not to be actual illustrations of any particular materials, devices, or methods, but are merely ideal representations used to describe embodiments of the present invention.

  It is understood that references to any elements herein using "first", "second", etc. designations do not limit the quantity or permutation of those elements, unless a limitation is explicitly stated. I want to be. Rather, these directives may be used herein as a convenient way of distinguishing between two or more elements or example elements. Thus, a reference to a first element and a second element means that only two elements can be used there, or that the first element must precede the second element in some way. do not do. Also, unless stated otherwise, a set of elements may include one or more elements.

  Elements described herein may include multiple examples of the same element. These elements can generally be indicated by a numeric indicator (eg, 110), specifically a numeric indicator followed by an alphabetic indicator (eg, 110A) or a number that precedes a “dash”. It may be indicated by an indicator (eg 110-1). To facilitate following this description, for the most part, element number indicators begin with a drawing number in which the elements are introduced or nearly fully discussed. Thus, for example, the element designator of FIG. 1 will most likely be in the numerical form 1xx, and the element in FIG. 4 will most likely be in the numerical form 4xx.

  The following description presents specific details, such as material types and processing conditions, in order to fully describe the embodiments of the present disclosure and their implementation. However, one of ordinary skill in the art will appreciate that embodiments of the present disclosure may be practiced without using these specific details and in combination with conventional assembly techniques. Further, the description presented herein does not form a complete process flow for manufacturing a semiconductor device or system. In this specification, only the process actions and structures necessary to understand the embodiments of the present invention are described in detail. The materials described herein can be chemical vapor deposition (“CVD”), plasma enhanced chemical vapor deposition (“PECVD”), atomic layer deposition (“ALD”), plasma ALD, or physical vapor It can be formed (eg, deposited or grown) by any suitable technique, including but not limited to growth methods (“PVD”). Although the materials described and shown herein may be formed as layers, these materials are not limited to layers and may be formed in other three-dimensional configurations.

  As used herein, the terms “horizontal” and “vertical” refer to an element or structure relative to a major plane or surface of a semiconductor structure, regardless of the orientation of the semiconductor structure (eg, wafer, die, substrate, etc.) It defines the relative position and is an orthogonal dimension that is interpreted relative to the orientation of the structure being described. As used herein, the term “vertical” means and encompasses a dimension that is substantially perpendicular to the major surface of the semiconductor structure, and the term “horizontal” refers to the major surface of the semiconductor structure. On the other hand, it means a substantially horizontal dimension.

  As used herein, the term “semiconductor structure” means and encompasses any structure used in the formation of semiconductor devices. Semiconductor structures include, for example, dies and wafers (eg, carrier substrates and device substrates), and assemblies or composite structures having two or more dies and / or wafers that are three-dimensionally stacked together. The semiconductor structure also includes a fully manufactured semiconductor device and an intermediate structure formed during the manufacture of the semiconductor device. The semiconductor structure can include conductive materials, semiconductor materials, non-conductive materials (eg, electrical insulators), and combinations thereof.

  As used herein, the term “processed semiconductor structure” means and encompasses any semiconductor structure comprising one or more at least partially formed device structures. A processed semiconductor structure is a subset of a semiconductor structure, and every processed semiconductor structure is a semiconductor structure.

  As used herein, the term “III-V semiconductor” refers to one or more elements from group IIIA of the periodic table (eg, B, Al, Ga, In, and Ti), and group VA of the periodic table. Means and encompasses any semiconductor material composed at least primarily of one or more elements from (eg, N, P, As, Sb, and Bi).

  As used herein, the terms “indium gallium nitride” and “InGaN” refer to alloys of indium nitride (InN) and gallium nitride (GaN) having the composition InxGa1-xN. Here, 0 <x ≦ 1.

  In this specification, the term “critical thickness” means the average total thickness of a semiconductor material layer after the point in time when pseudomorphic growth does not continue and the layer undergoes strain relaxation.

  As used herein, the term “growth surface” means any surface of a semiconductor substrate or semiconductor layer on which further growth of the semiconductor substrate or semiconductor layer can be performed.

  As used herein, the term “dislocation” has imperfections in the crystal structure of a semiconductor material that can be characterized by characteristics such as, for example, elemental deficiencies in the crystal structure and bond breaks in the crystal structure. It means a region of semiconductor material.

  As used herein, the term “substantially” is used to refer to a result that is complete except for any deficiencies normally expected in the art.

  Embodiments of the present invention may have application to a variety of III-V semiconductor materials. For example, the methods and structures of the embodiments of the present invention include group III-nitrides, group III-arsenides, group III-phosphides in two-component, three-component, four-component, and five-component forms, And Group III-antimonides. A particular application relates to the growth of group III-nitride semiconductors containing indium, such as indium gallium nitride (InGaN). Thus, for reasons of simplicity and convenience only, and not for purposes of limitation, the following description and drawings reflect the general characteristics of Group III-nitrides and may focus specifically on InGaN.

  Experiments with III-nitride material systems have shown that InGaN layers that are pseudomorphically grown to a thickness exceeding the critical thickness can undergo strain relaxation and can relax crystal lattice distortion resulting from lattice mismatch. Has been demonstrated. At the beginning of strain relaxation in the InGaN layer, a large amount of indium may be taken in, which may result in a non-uniform concentration profile of indium across the thickness of the InGaN layer. For example, an InGaN layer may contain a high proportion of indium proximal to the growth surface of the layer. Such a non-uniform indium composition in the InGaN layer may not be desirable for at least some applications.

  In addition, experiments have demonstrated that the growth surface of the InGaN layer may be roughened due to strain relaxation of the InGaN layer. Such roughening of the surface may not be preferable for the production of a semiconductor device using this InGaN layer. Furthermore, experiments have demonstrated that the defect density in the crystalline material may increase due to strain relaxation of the InGaN layer. Such defects can include, for example, dislocations and heterogeneous composition regions (ie, phase separation regions).

  As a non-limiting example, in the case of InGaN (Group III-Nitride material), the InGaN layer is heteroepitaxially deposited on an underlying substrate that may have a crystal lattice that does not match the crystal lattice of the superimposed InGaN layer. Can be deposited. For example, the InGaN layer can be deposited on a semiconductor substrate comprising gallium nitride (GaN). GaN has a relaxed (ie, substantially unstrained) in-plane lattice parameter of about 3.189 Ｉｎ, and the InGaN layer is about 3.21 Å (7%), depending on the corresponding percentage of indium content. Indium, i.e. In0.07Ga0.93N), about 3.24? (15% indium, i.e. In0.15Ga0.85N), and about 3.26? (25% indium, i.e. In0.25Ga0.75N) May have a relaxed in-plane lattice parameter.

  FIG. 1 shows a semiconductor structure having a semiconductor material layer 130 and an indium-III-V semiconductor layer 140 formed thereon, showing dislocations (132 and 142) and V pits 150 formed therein. 1 is a schematic sectional view of a body 100. FIG. The semiconductor structure 100 may be manufactured with a substrate 110 or may be otherwise prepared. Substrate 110 forms one or more additional semiconductor material layers thereon as part of the assembly of semiconductor material layer 130 and indium-III-V semiconductor layer 140, as will be described in more detail below. It may include a semiconductor material that can be used as a seed layer for use.

  The semiconductor material layer 130 may be attached to the substrate 110 and carried by the substrate 110. However, in some embodiments, the semiconductor material layer 130 may comprise a separate semiconductor material bulk layer that is not disposed or supported on the substrate or any other material.

  In some embodiments, the semiconductor material layer 130 may comprise a semiconductor material epitaxial layer. As a non-limiting example, the semiconductor material layer 130 may comprise a III-V semiconductor material epitaxial layer. As a non-limiting example, the III-V semiconductor layer 130 may be a GaN epitaxial layer.

  The substrate 110 is made of, for example, aluminum oxide (Al 2 O 3) (for example, sapphire), zinc oxide (ZnO), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), lithium gallate (LiGaO 2), or lithium aluminate. It may be a material such as (LiAlO2), yttrium aluminum oxide (Y3Al5O12), or magnesium oxide (MgO).

  Optionally, one or more intermediate material layers (not shown), such as another semiconductor material layer, or one or more dielectric material layers are disposed between the semiconductor material layer 130 and the substrate 110. May be provided. Such an intermediate material layer is, for example, as a seed layer for forming the semiconductor material layer 130 thereon, or when it is difficult or impossible to form the semiconductor material layer 130 directly on the substrate 110. It may be used as a bonding layer for bonding the semiconductor material layer 130 to the substrate 110 as can be implemented in FIG. Further, bonding the semiconductor material layer 130 to the substrate 110 may be desirable when the semiconductor material layer 130 has a polar crystal orientation. In such embodiments, the bonding process can be used to change the polarity of the polar semiconductor material.

  In the present specification, the drawings are not drawn to scale, and in fact, the group III-V semiconductor layer 130 may be relatively thinner than the substrate 110.

  Dislocations (132B and 132D) may be formed when the III-V semiconductor layer 130 is being formed. As shown in FIG. 1, these dislocations can be threading dislocations that continue as the layer is formed with a greater thickness. In other words, when dislocations occur, they tend to propagate as the layers are formed and thus appear on the final surface of the III-V semiconductor layer 130 after layer formation is complete.

  Any of a variety of methods known in the art may be used to reduce the dislocation density in the III-V semiconductor layer 130. Such methods can include, for example, epitaxial lateral growth (ELO), pendeo epitaxy, in-situ masking techniques, and the like. The semiconductor material layer 130 is deposited using a process such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). Also good.

  FIG. 1 also shows additional group III-V semiconductor material 140 on group III-V semiconductor layer 130. By way of non-limiting example, this additional III-V semiconductor material 140 may be an InGaN layer 140 or another type of III-V semiconductor material such as gallium phosphide (GaP) and gallium arsenide (GaAs). Combined indium may be provided. An indium semiconductor layer combined with a III-V semiconductor material may be referred to herein as an indium-III-V semiconductor material or an indium-III-V semiconductor layer 140.

  An InGaN alloy layer grows a mismatched lattice on a GaN template (eg, GaN 130 on sapphire 110). As more indium is present in the InGaN layer 140, the lattice mismatch between the InGaN layer 140 and the GaN template becomes greater. In general, configuration mismatch growth (ie, mismatch between the InGaN layer 140 and the GaN template) is when the strain energy accumulated in the InGaN layer 140 is greater than the strain energy that agglomerates dislocations, Accompanies strain relaxation. This lattice mismatch growth occurs for a lattice arranged in a cubic system, but is more complicated for a material having a hexagonal lattice structure such as GaN, InGaN, or AlGaN.

  In a hexagonal layer, there may be no slip planes that are easy to dislocation, and thus much higher strain energy can be accumulated in the InGaN layer 140 by dislocation aggregation. When relaxation is reached, plastic relaxation is caused by modification of the growth surface. If the growth surface is a (0001) hexagonal system, pit defects 150 may occur. These pit defects appear as inverted pyramids having apexes near dislocations (often threading dislocations) in the GaN substrate, and are often referred to as V pits 150. As the InGaN layer 140 grows, this inverted pyramid also grows. In the case of a thick InGaN layer, the V pit 150 can be very large.

  In general, a thinner InGaN layer 140 can be grown with little or no V pit 150. Since the strain energy in the InGaN layer 140 increases with the layer thickness, the thin layer may not reach the thickness at which strain relaxation occurs (ie, the critical thickness). However, in some applications, a thick InGaN layer may be desirable. As a result, with conventional processing, the V pit 150 exists in the thicker InGaN layer 140, and the V pit 150 becomes deeper and wider as the InGaN layer 140 becomes thicker.

  In addition to the thinner InGaN layer, it may generally be possible to form an InGaN layer that is relatively free of V pits when the indium concentration is kept relatively low relative to the gallium concentration. However, many applications require thick InGaN layers, high indium concentrations in InGaN layers, or a combination thereof, any of which can result in deep and wide V pits.

  As already mentioned, V pits often begin with dislocations such as 132B and 132D in III-V semiconductor layer 130 and threading dislocations shown as 142A and 142E in indium-III-V semiconductor layer 140. From these dislocations 132, V pits (150A, 150B, 150D, and 150E) can be formed and grow larger as the indium-III-V semiconductor layer 140 grows. The V pit can also begin as an original dislocation as indicated by V pit 150C.

  These deep V-pits 150 can become holes after further processing for layer transfer, i.e. by smart cut and bonding processes. Also, the V pit 150 may locally change the ion implantation depth, resulting in splitting defects. Furthermore, further regrowth after layer transfer onto the pit-formed InGaN layer results in very deep pits that are undesirable for LED devices. For example, if the V pit 150 occurs throughout the InGaN layer 140, the V pit 150 may cause a short circuit in the diode portion of the LED device, thereby preventing the device from performing its intended function. is there.

  FIG. 2 is a schematic isometric view illustrating a non-limiting example of a V pit 150 in a non-limiting example In-III-V group semiconductor layer 140. The hexagonal shape of the opening on the growth surface 148 is due to the crystal structure growth of InGaN. Further, the V pit side wall 152 continues upward from the apex 155 where the V pit 150 begins to be formed by crystal structure growth, so that the V pit 150 has a certain width 156 with respect to the depth 154. Generally have. Therefore, the depth 154 of the V pit 150 can be accurately estimated based on the width 156 of the V pit.

  Embodiments of the present invention reduce the number, size, or combination of V pits 150 formed when the indium-III-V semiconductor layer 140 is formed on the III-V semiconductor layer 130. be able to. This reduction in V pit 150 is also referred to herein as “reduced V pit density” and “reduced V pit density”. Thus, a reduction in V pit density may refer to a reduction of V pits at a given surface area, a reduction of V pits at a given surface area, or a combination of V pit reduction and reduction at a given surface area. .

  Although not bound by any particular theory regarding the formation of V pits, Shiojiri (see Non-Patent Document 1) has a growth rate higher than that of the {0001} base surface of the growth surface 148. This suggests a different point in the {10-11} plane. Further, the {10-11} plane of the V pit sidewall 152 may have a higher adhesion coefficient to indium than the {0001} base plane of the growth surface 148. As a result, embodiments of the present invention can saturate the indium concentration on the {0001} base of the growth surface 148 of the solid material that is formed by increasing the proportion of indium in the gas phase during processing, and The higher concentration of indium on the {10-11} plane of the V pit sidewall 152 can promote the growth of InGaN on the V pit sidewall, thereby reducing the V pit density.

  FIG. 3 includes a semiconductor material layer 130 and an indium-III-V semiconductor layer 140 formed thereon and mitigation of V pits formed therein according to one or more embodiments of the present invention. FIG. 3 is a schematic cross-sectional view of a semiconductor substrate 110 where the density is shown. Similar to FIG. 1, the semiconductor structure 100 may be manufactured or otherwise prepared with a substrate 110. The substrate 110, the semiconductor material layer 130, and the indium-III-V semiconductor layer 140 are similar to those described in FIG.

  However, FIG. 3 shows conventional V pits 152A, 152B, and 152C (ie, V pits that can be formed when conventional processing is utilized). FIG. 3 also shows smaller V pits (158A, 158B, and 158C), which provide a reduction in V pit density according to one or more embodiments of the present invention. Reduced V pits 158A and 158C have V pits originating from threading dislocations 132B and 132C, respectively, grown slower than V pits 152A and 152C formed using conventional processing (ie, Does not have the same size). Mitigated V pits 158B exhibit smaller V pits than V pits 152B that can be formed directly from dislocations using conventional processing.

  FIG. 4 is a graph of indium solid phase concentration versus indium vapor phase concentration to show indium saturation for a given vapor phase indium concentration. FIG. 4 can be developed from experiments in a processing chamber using a relatively constant temperature, a relatively constant pressure, a relatively constant total gas flow, and a relatively constant wafer rotation speed. With a specific gallium flow rate, the indium flow rate can be varied to change the proportion of indium in the gas phase as shown by the x-axis. The proportion of solid phase indium developed in the InGaN layer is shown on the y-axis as a function of the proportion of vapor phase indium.

  In some embodiments, the indium precursor for forming the InGaN layer may include, for example, trimethylindium (TMI), triethylindium (TEI), or combinations thereof. In some embodiments, the gallium precursor for forming the InGaN layer may include, for example, triethylgallium (TEG) or other suitable material. In some embodiments, the nitrogen precursor for forming the InGaN layer may include, for example, ammonia (NH 3) or other suitable material.

Thus, for one embodiment,
% Indium in gas phase = 100 * (TMI flow / (TMI flow + TEG flow)) (1)
It becomes.

  Initially, as the proportion of vapor phase indium increases, the proportion of solid phase indium increases proportionally as shown by segment 410A. However, when the inflection point 410B is reached, further increase in the vapor phase indium ratio does not lead to an increase in the solid phase indium ratio as indicated by the segment 410C. This range of vapor phase indium concentration where no proportional increase in solid phase indium concentration occurs is referred to herein as the indium saturation regime.

  FIG. 5 is a graph of indium solid phase concentration versus indium partial pressure showing the saturation situation of FIG. 4 and the supersaturation situation according to one or more embodiments of the present invention.

As will be appreciated by those skilled in the art, the gas flow rate in the processing chamber correlates with the partial pressure of each different gas in the processing chamber. As a result, the indium concentration in the gas phase is
% Indium in gas phase = 100 * (P _TMI / (P _TMI + P _TEG )) (2)
It can also be expressed as

In other words, it is possible to easily determine the relationship of the indium partial pressure to the group III partial pressure total (P _TMI + P _TEG ), which is a combination of the indium partial pressure (P _TMI ) and the gallium partial pressure. To simplify the description, most of the description herein relates to partial pressure, but those skilled in the art will understand that these descriptions may also apply to correlated flow rates. Like.

Of course, other inert gases (eg, nitrogen) and other reactants such as dopants may be present in the reaction chamber. As a non-limiting example, the N dopant may include a silicon-containing vapor such as silane (SiH ₄ ), and the P dopant includes a vapor such as bis (cyclopentadienyl) magnesium (Cp 2 Mg). May be included.

  In FIG. 5, the y-axis is the ratio of solid-phase indium to the x-axis (also referred to herein as solid-phase indium concentration) indicating the partial pressure of indium (also referred to herein as vapor-phase indium concentration). ).

  Segments 510A and 510C have a proportional increase in the solid phase indium concentration relative to the vapor phase indium concentration (510A) and the subsequent saturation of the indium concentration remains relatively constant with the increase in the vapor phase indium concentration (510C). Indicates the situation.

  Line 520 shows an indium supersaturation situation where a higher solid phase indium concentration can be obtained than a saturation situation. Therefore, in this specification, the term indium supersaturation situation refers to the indium in the solid phase semiconductor layer formed compared to the indium concentration formed in the solid phase semiconductor layer utilizing the saturation situation discussed above. It means the situation in the processing chamber set to be higher in concentration.

  As a non-limiting example, saturation conditions can be defined as a given chamber pressure, growth surface temperature, group III element precursor partial pressure, group V element precursor partial pressure, and indium precursor partial pressure. A higher concentration or partial pressure of the indium precursor than a saturation situation can develop a supersaturation situation that creates a higher indium concentration in the formed semiconductor layer.

  Another non-limiting example is a given growth surface temperature, a given chamber pressure, a given wafer spin rate, and a given indium precursor, group III element precursor, and group V element precursor. In the saturation situation defined by the combination of the partial pressures of the growth, a decrease in the growth surface temperature results in a supersaturation situation, which is formed compared to the proportion of indium obtained for the saturation situation. A solid phase growth condition is provided in which the proportion of indium in the semiconductor layer is higher. Similarly, an indium supersaturation situation can be developed by an increase in chamber pressure or a change in wafer rotation speed while the temperature is maintained at this saturation situation temperature.

  In line 520, chamber parameters such as chamber pressure and wafer rotation speed, for example, can be kept relatively constant, but the temperature drops and develops an indium supersaturation situation. The temperature can be determined as the chamber temperature or the growth surface temperature. As a non-limiting example, the chamber temperature of segments 510A and 510C is about 839 ° C. and the chamber temperature of line 520 is about 811 ° C. Furthermore, the relative concentration of the group III precursor (eg, an indium precursor combined with a gallium precursor) and the group V precursor is kept relatively constant at a V / III ratio of 3560. In other words, in one embodiment, as the line 520 moves from left to right, the TEG partial pressure may remain relatively constant, but as the TMI partial pressure increases, the ammonia partial pressure increases. Rising proportionally to maintain a V / III ratio of about 3560.

  As a non-limiting example, line 530 can be developed at a chamber temperature of about 811 ° C., and group V partial pressure (eg, partial pressure of ammonia) is relative to group III partial pressure and variable indium partial pressure. Is maintained substantially constant. In other words, in one embodiment, as line 530 moves from left to right, the TEG and ammonia partial pressures may remain relatively constant while the TMI partial pressure increases.

  In more detail and with reference to FIGS. 3 and 5, the flow of indium precursor to the InGaN layer 140 causes the indium species to be used for interaction on the growth surface 148 and V pit sidewalls 152. It can affect the incoming flux. Indium can be highly volatile. At the surface, the TMI is destroyed and releases a metal (eg, indium), which can be incorporated into the solid layer or dissipate as a vapor. The higher the temperature, the more likely it will dissipate than the metal is taken up.

  As a result, there is a trade-off between indium incorporation into the InGaN layer 140 and indium desorption from the InGaN layer 140 (also referred to herein as desorption flux). By decreasing the temperature or increasing the pressure, the uptake can be favorable to increase the solid phase indium concentration in the InGaN layer 140. Furthermore, while the growth surface 148 may reach a saturation situation, the V pit sidewall 152 having a different growth surface is more likely to have a higher growth rate than the growth surface 148, thereby A reduction in V-pit density can be provided.

  FIGS. 6A-6C are graphs illustrating indium solid phase concentration, V pit density, and V pit width, respectively, with respect to indium partial pressure according to one or more embodiments of the present invention.

  As indicated by line 610 in FIG. 6A, as the vapor phase indium concentration increases, the solid phase indium concentration also increases to an indium concentration of up to about 94%. At this point, an increase in the gas phase concentration leads to a decrease in the solid phase concentration.

  As shown by line 620 in FIG. 6B, as the vapor phase indium concentration increases, the V pit density also increases to an indium concentration of up to about 94%. At this point, an increase in the gas phase concentration leads to a decrease in the solid phase concentration.

  However, as indicated by line 630 in FIG. 6C, the V pit width decreases as the vapor phase indium concentration increases. The dashed line in FIG. 6C indicates the average V pit width, and the upper bar 632 and the lower bar 634 indicate 3 sigma distribution points for the V pit width. As a result, as the indium partial pressure increases, there are fewer V pits for a given area, smaller V pits, or the number of V pits and their V pit size for a given area. A reduction in V pit density due to any of the combinations can be observed.

  The pit width is a preferred method for measuring V pits by atomic force microscopy (AFM). This is because the AFM tip may not have enough sharpness to penetrate through this depth to accurately measure the total depth of the V pit. From crystallographic consideration (for example, the angle between the (10-11) plane and the (0001) plane), the pit depth can be calculated from the pit width (see Non-Patent Document 2).

  It should also be noted that in the case of very thin InGaN layers, V-pits, even if present, can become undetectable because their width can be below the AFM resolution.

  As previously noted, many applications require thick InGaN layers, high indium concentrations in InGaN layers, or combinations thereof, all of which can result in deep and wide V-pits. Some embodiments of the present invention can provide a reduction in V pit density for solid phase indium concentrations in the range of about 6% to 9%. Further, in some embodiments, the reduction in V pit density may be achieved for relatively thick InGaN layers of about 150 nanometers and possibly up to about 200 nanometers.

Claims (10)

Forming a group III-V semiconductor layer on the substrate;
In a processing chamber configured to have an indium supersaturation situation that includes a chamber temperature that is less than the chamber temperature corresponding to the indium saturation situation, at least an indium precursor, a group III element precursor different from the indium precursor, and a group V by combining element precursor, seen including a step of forming said group III-V indium -III-V group semiconductor layer having indium solid concentrations above the indium saturation conditions on the growth surface of the semiconductor layer,
The step of forming the indium-III-V semiconductor layer includes a step of increasing the indium incorporation in the V pit side wall as compared with the indium incorporation into the growth surface of the indium-III-V semiconductor layer. Further including
A method of forming a semiconductor structure, wherein the growth surface is a {0001} plane, and the growth surface of the V pit sidewall is a {10-11} plane .   The method of claim 1, further comprising forming the indium-III-V semiconductor layer having a thickness greater than a critical thickness.   The step of forming the indium-III-V semiconductor layer includes a step of forming a V pit of the indium-III-V semiconductor layer as compared to a desorption flow of indium from the growth surface of the indium-III-V semiconductor layer. The method of claim 1, further comprising reducing the desorption flow of indium from the sidewall. Increasing the indium uptake in the V pit sidewall includes at least one of lowering the chamber temperature, increasing the chamber pressure, and increasing the indium partial pressure. The method according to claim 1 .   The method of claim 1, wherein forming the indium-III-V semiconductor layer further comprises increasing an indium partial pressure in the processing chamber as compared to a total group III partial pressure. the method of.   The method of claim 1, wherein forming the indium-III-V semiconductor layer comprises forming an indium gallium nitride (InGaN) layer.   The method of claim 1, further comprising selecting the group V element precursor to include ammonia.   The method of claim 1, further comprising selecting the indium precursor to include trimethylindium.   2. The method of claim 1, further comprising selecting the group III element precursor to include triethylgallium.   The method of claim 1, wherein forming the indium-III-V semiconductor layer further comprises increasing an indium partial pressure in the processing chamber as compared to a total group III partial pressure. the method of.

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