KR20130133199A - 절연성 기판, 금속장 적층판, 프린트 배선판, 및 반도체 장치 - Google Patents
절연성 기판, 금속장 적층판, 프린트 배선판, 및 반도체 장치 Download PDFInfo
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- KR20130133199A KR20130133199A KR1020137013803A KR20137013803A KR20130133199A KR 20130133199 A KR20130133199 A KR 20130133199A KR 1020137013803 A KR1020137013803 A KR 1020137013803A KR 20137013803 A KR20137013803 A KR 20137013803A KR 20130133199 A KR20130133199 A KR 20130133199A
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Images
Classifications
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- B32B5/00—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts
- B32B5/02—Layered products characterised by the non- homogeneity or physical structure, i.e. comprising a fibrous, filamentary, particulate or foam layer; Layered products characterised by having a layer differing constitutionally or physically in different parts characterised by structural features of a fibrous or filamentary layer
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- B32B27/00—Layered products comprising a layer of synthetic resin
- B32B27/12—Layered products comprising a layer of synthetic resin next to a fibrous or filamentary layer
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K1/036—Multilayers with layers of different types
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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-
- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- B32B2457/08—PCBs, i.e. printed circuit boards
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/0275—Fibers and reinforcement materials
- H05K2201/029—Woven fibrous reinforcement or textile
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
- Y10T428/24967—Absolute thicknesses specified
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Abstract
본 발명의 절연성 기판은, 1층 이상의 섬유기재층 및 2층 이상의 수지층을 포함하며, 또 양면의 최외층이 수지층인 적층체의 경화물로 이루어지며, 적어도 1개의 섬유기재층이, 기준 위치 즉 절연성 기판의 전체 두께를 섬유기재층수로 균등하게 분할한 각 영역의 두께를 균등하게 더 2 분할했을 때의 분할 위치 보다 제1면 측 또는 그 반대의 면인 제2면 측에 편재하고, 섬유기재층 중에는 상이한 방향으로 편재하는 것이 없는 것이다.
본 발명의 상기 절연성 기판을 포함하는 금속장 적층판을 코어 기판으로서 이용하여, 프린트 배선판을 제작할 수 있다. 또, 상기 프린트 배선판에 반도체 소자를 탑재하여 반도체 장치를 제작할 수 있다.
Description
도 2에서 도 2A는, 1층의 섬유기재층과 3층의 수지층을 포함하는 본 발명에 관한 절연성 기판의 일례의 단면을 모식적으로 나타내는 도면이다. 도 2B는, 도 2A에 나타낸 절연성 기판이 상온에서 휘어진 상태를 나타내는 도면이다.
도 3에서 도 3A는, 2층의 섬유기재층과 4층의 수지층을 포함하는 본 발명에 관한 절연성 기판의 일례의 단면을 모식적으로 나타내는 도면이다. 도 3B는, 도 3A에 나타낸 절연성 기판이 상온에서 휘어진 상태를 나타내는 도면이다.
도 4에서 도 4A는, 2층의 섬유기재층과 4층의 수지층을 포함하는 본 발명에 관한 절연성 기판의 다른 일례의 단면을 모식적으로 나타내는 도면이다. 도 4B는, 도 4A에 나타낸 절연성 기판이 상온에서 휘어진 상태를 나타내는 도면이다.
도 5에서 도 5A는, 3층의 섬유기재층과 6층의 수지층을 포함하는 본 발명에 관한 절연성 기판의 일례의 단면을 모식적으로 나타내는 도면이다. 도 5B는, 도 5A에 나타낸 절연성 기판이 상온에서 휘어진 상태를 나타내는 도면이다.
도 6에서 도 6A는, 3층의 섬유기재층과 6층의 수지층을 포함하는 본 발명에 관한 절연성 기판의 다른 일례의 단면을 모식적으로 나타내는 도면이다. 도 6B는, 도 6A에 나타낸 절연성 기판이 상온에서 젖혀진 상태를 나타내는 도면이다.
도 7은 본 발명에 이용되는 비대칭 프리프레그를 얻는 방법의 일례를 설명하는 도면이다.
도 8은 본 발명에 이용되는 적층체를 얻는 방법의 일례를 설명하는 도면이다.
도 9는 본 발명에 이용되는 적층체를 얻는 방법의 다른 일례를 설명하는 도면이다.
도 10은 본 발명에 이용되는 적층체를 얻는 방법의 다른 일례를 설명하는 도면이다.
도 11은 본 발명에 이용되는 적층체를 얻는 방법의 다른 일례를 설명하는 도면이다.
도 12는 도 1에 나타내는 절연성 기판을 코어층으로서 갖는 프린트 배선판 위에 반도체 소자를 탑재한 반도체 장치의 단면을 모식적으로 나타내는 도면이다.
도 13은 도 5에 나타내는 절연성 기판을 코어층으로서 갖는 프린트 배선판 위에 반도체 소자를 탑재한 반도체 장치의 단면을 모식적으로 나타내는 도면이다.
도 14는 도 6에 나타내는 절연성 기판을 코어층으로서 갖는 프린트 배선판 위에 반도체 소자를 탑재한 반도체 장치의 단면을 모식적으로 나타내는 도면이다.
도 15에서 도 15A는 반도체 장치의 플러스 휨을 설명하는 도면이며, 도 15B는 반도체 장치의 마이너스 휨을 설명하는 도면이다.
102 캐리어 필름 부착 비대칭 프리프레그
103, 103', 103'' 대칭 프리프레그
111, 112, 113, 114, 115, 116 절연성 기판
121, 122, 123, 124 적층체
131, 132, 133 반도체 장치
C1~C3 섬유기재층
r1~r6 수지층
1 섬유기재층
2 제1 수지층
3 제2 수지층
2' 제1 캐리어 재료
3' 제2 캐리어 재료
4 수지층
5 코어층
7 프린트 배선판
8 반도체 소자
9 도체 회로층(내층 회로)
10 층간절연층
11 도체 회로층(외층 회로)
12 비아 홀
13 쓰루홀
14 솔더 레지스트
15 액상 봉지 수지
16 솔더 범프
17 도체 회로층(내층 회로)
18 층간절연층
Claims (14)
상기 절연성 기판에 포함되는 상기 섬유기재층을 제1면 측으로부터 순차적으로 Cx(x는 1~n으로 나타내는 정수이며, n은 섬유기재층의 수이다.)로 하고,
상기 절연성 기판의 전체 두께(B3)를 상기 섬유기재층의 수(n)로 균등하게 분할하고, 분할한 각 영역의 두께(B4)를 균등하게 더 2 분할하였을 때의 분할 위치를 섬유기재층의 기준 위치로 하고, 상기 각각의 기준 위치를 제1면 측으로부터 순차적으로 Ax(x는 1~n으로 나타내는 정수이며, n은 섬유기재층의 수이다.)로 하였을 때에,
상기 섬유기재층 중의 적어도 1개(Cx)가, 대응하는 순위(x)의 기준 위치(Ax) 보다 제1면 측 또는 그 반대의 면인 제2면 측에 편재하고, 상기 섬유기재층(Cx) 중에 상이한 방향으로 편재하는 것이 없는 것을 특징으로 하는, 절연성 기판.
상기 섬유기재층 중의 적어도 1개가, 대응하는 순위의 기준 위치 보다 제1면 측에 편재하고,
상기 편재하는 섬유기재층은,
상기 섬유기재층의 제1면 측에 있는 수지 충전 영역의 두께(B5)와,
상기 섬유기재층의 제2면 측에 있는 수지 충전 영역의 두께(B6)의 비(B5/B6)가, 0.1<B5/B6<1.2인 절연성 기판.
상기 섬유기재층의 수가 1개 또는 2개인 절연성 기판.
상기 균등하게 분할된 두께(B4)의 각 영역 내에, 각각 1개의 섬유기재층이 존재하는 것을 특징으로 하는 것인 절연성 기판.
상기 균등하게 분할된 두께(B4)의 각 영역 중의 적어도 1개가, 1개의 섬유기재층을 대응하는 순위의 기준 위치 보다 제1면 측에 편재하여 갖고,
상기 편재하는 섬유기재층은,
상기 섬유기재층의 제1면 측의 계면으로부터 상기 섬유기재층이 속하는 두께(B4)의 영역의 상기 제1면 측의 경계까지의 거리(B7)와,
상기 섬유기재층의 제2면 측의 계면으로부터 상기 섬유기재층이 속하는 두께(B4) 영역의 상기 제2면 측의 경계까지의 거리(B8)의 비(B7/B8)가, 0.1<B7/B8<0.9인 것인 절연성 기판.
상기 절연성 기판을 갖는 섬유기재층 중에, 가장 제1면 측에 위치하는 섬유기재층이, 대응하는 순위의 기준 위치 보다 상기 제1면 측에 편재하여 배치되어 있는 것인 절연성 기판.
상기 절연성 기판을 갖는 섬유기재층 중에, 가장 제2면 측에 위치하는 섬유기재층이, 대응하는 순위의 기준 위치 보다 상기 제1면 측에 편재하여 배치되어 있는 것인 절연성 기판.
상기 전체 두께가 0.03mm 이상 0.5mm 이하인 절연성 기판.
프리프레그 1매 또는 프리프레그를 2매 이상 중첩시킨 적층체의 경화물로 이루어진 절연성 기판에 있어서,
섬유기재층의 1면에 제1 수지층, 다른 면에 제2 수지층이 설치되고 상기 제1 수지층의 두께가 상기 제2 수지층의 두께보다 작은 비대칭 프리프레그를 적어도 1매 포함하는 것을 특징으로 하는 절연성 기판.
상기 프린트 배선판에 포함되는 절연성 기판에 있어서, 섬유기재층이 편재하는 방향에 있는 제1면 측과는 반대 측의 제2면 측에 설치된 도체 회로층 위에 반도체 소자를 탑재하여 이루어진 것을 특징으로 하는 반도체 장치.
상기 프린트 배선판에 포함되는 절연성 기판이 갖는 섬유기재층 중에, 가장 제1면 측에 위치하는 섬유기재층이, 대응하는 순위의 기준 위치 보다 상기 제1면 측에 편재하여 배치되어 있으며,
상기 반도체 소자가, 섬유기재층이 편재하는 방향의 제1면 측과는 반대 측의 제2면 측에 설치된 도체 회로층 위에 탑재되어 있는 것인 반도체 장치.
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PCT/JP2011/076254 WO2012067094A1 (ja) | 2010-11-18 | 2011-11-15 | 絶縁性基板、金属張積層板、プリント配線板、及び半導体装置 |
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EP1976001A3 (en) * | 2007-03-26 | 2012-08-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
JP5138267B2 (ja) * | 2007-04-18 | 2013-02-06 | 日立化成工業株式会社 | プリプレグ、それを用いた多層基配線板及び電子部品 |
JP2010087402A (ja) * | 2008-10-02 | 2010-04-15 | Hitachi Chem Co Ltd | プリント配線板用多層基板の製造方法 |
-
2011
- 2011-09-26 JP JP2011209540A patent/JP5115645B2/ja not_active Expired - Fee Related
- 2011-11-14 TW TW100141393A patent/TWI477208B/zh not_active IP Right Cessation
- 2011-11-15 US US13/885,321 patent/US20130242520A1/en not_active Abandoned
- 2011-11-15 KR KR1020137013803A patent/KR20130133199A/ko not_active Ceased
- 2011-11-15 CN CN201180064929.5A patent/CN103298612B/zh not_active Expired - Fee Related
- 2011-11-15 WO PCT/JP2011/076254 patent/WO2012067094A1/ja active Application Filing
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160036247A (ko) * | 2014-09-25 | 2016-04-04 | 코닝정밀소재 주식회사 | 집적회로 패키지용 기판 |
US10134652B2 (en) | 2014-09-25 | 2018-11-20 | Corning Precision Materials Co., Ltd. | Substrate for integrated circuit package |
Also Published As
Publication number | Publication date |
---|---|
US20130242520A1 (en) | 2013-09-19 |
JP5115645B2 (ja) | 2013-01-09 |
JP2012124460A (ja) | 2012-06-28 |
TW201233260A (en) | 2012-08-01 |
WO2012067094A1 (ja) | 2012-05-24 |
TWI477208B (zh) | 2015-03-11 |
CN103298612A (zh) | 2013-09-11 |
CN103298612B (zh) | 2015-09-16 |
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