KR20130101363A - Method for manufacturing solar cell - Google Patents

Abstract

The method of manufacturing a solar cell according to the present embodiment includes preparing a semiconductor substrate having a first surface and a second surface opposite to each other, and a side surface intersecting the first surface and the second surface; A first doping to cross-dope a first conductivity type impurity to the first surface of the semiconductor substrate; Etching the side surface of the semiconductor substrate to remove the first conductivity type impurities remaining in the corresponding portion; And a second doping in which the second surface of the semiconductor substrate is doped with a second conductivity type impurity.

Description

[0001] METHOD FOR MANUFACTURING SOLAR CELL [0002]

The present invention relates to a method for manufacturing a solar cell, and more particularly to a method for manufacturing a solar cell with improved process.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such a solar cell, an impurity layer is formed so as to cause photoelectric conversion to form a pn junction and the like, and an electrode connected to an n-type impurity layer and / or a p-type impurity layer is formed. Undesirable electrical shorts may occur due to unpredictable process errors during the formation of such impurity layers. As a result, the current density and the open voltage of the solar cell may be reduced, and thus the efficiency of the solar cell may be reduced, and the life may be reduced due to heat generation.

The present invention is to provide a method for manufacturing a solar cell that can improve the efficiency of the solar cell and can extend the life of the solar cell.

The method of manufacturing a solar cell according to the present embodiment includes preparing a semiconductor substrate having a first surface and a second surface opposite to each other, and a side surface intersecting the first surface and the second surface; A first doping to cross-dope a first conductivity type impurity to the first surface of the semiconductor substrate; Etching the side surface of the semiconductor substrate to remove the first conductivity type impurities remaining in the corresponding portion; And a second doping in which the second surface of the semiconductor substrate is doped with a second conductivity type impurity.

According to the present exemplary embodiment, the side surface of the semiconductor substrate is etched between the first doping and the second doping which are respectively performed by single-sided doping on both surfaces of the semiconductor substrate. As a result, the side doped portions formed unnecessary can be removed, and unnecessary electrical shorts can be prevented. Accordingly, the reverse current and the saturation current can be reduced to improve the current density and the open voltage. In addition, it is possible to minimize hot spots and heat generation that may occur at the end of the solar cell. That is, the efficiency of the solar cell can be improved and the life can be extended.

In addition, in the present embodiment, the back side of the semiconductor substrate may also be etched together in the step of etching and isolating the side surface of the semiconductor substrate to improve back passivation characteristics. That is, the characteristics of the solar cell can be improved while simplifying the process.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
3A to 3G are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4 is a cross-sectional view showing the step of isolating a method of manufacturing a solar cell according to an embodiment of the present invention.
5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to clarify the description. The thickness, the width, and the like of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. First, after explaining the structure of the solar cell manufactured by the method for manufacturing a solar cell according to an embodiment of the present invention, a method for manufacturing a solar cell according to an embodiment of the present invention will be described.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.

Referring to FIG. 1, the solar cell 100 according to the present exemplary embodiment is positioned on the semiconductor substrate 10 and the first surface (hereinafter, “front surface”) of the semiconductor substrate 10 and includes a first conductivity type impurity. The reflector formed on the front surface of the semiconductor substrate 10 and the emitter layer 20, the back surface field layer 30 positioned on the second side (hereinafter referred to as “back side”) of the semiconductor substrate 10 and including the second conductivity type impurities. The barrier layer 22 and the first electrode 24, the passivation layer 32 and the second electrode 34 positioned on the rear surface of the semiconductor substrate 10 may be included. This will be described in more detail as follows.

The semiconductor substrate 10 may comprise various semiconductor materials, for example silicon containing a second conductivity type impurity. As the silicon, single crystal silicon or polycrystalline silicon may be used, and the second conductivity type impurity may be n-type, for example. That is, the semiconductor substrate 10 may be formed of single crystal or polycrystalline silicon doped with a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb)

When the semiconductor substrate 10 having the n-type impurity is used, the emitter layer 20 having the p-type impurity is formed on the entire surface of the semiconductor substrate 10 to form a pn junction. When the pn junction is irradiated with light, electrons generated by the photoelectric effect move toward the rear surface of the semiconductor substrate 10, are collected by the second electrode 34, and the holes move toward the front surface of the semiconductor substrate 10 1 electrode 24, respectively. Thereby, electric energy is generated.

In this case, holes having a slower moving speed than electrons may move to the front surface of the semiconductor substrate 10 instead of the rear surface, thereby improving conversion efficiency.

The front surface of the semiconductor substrate 10 may be textured to have irregularities in the form of a pyramid or the like. If unevenness is formed on the front surface of the semiconductor substrate 10 by such texturing and the surface roughness is increased, the reflectance of light incident through the front surface of the semiconductor substrate 10 may be lowered. Therefore, the amount of light reaching the pn junction formed at the interface between the semiconductor substrate 10 and the emitter layer 20 can be increased, thereby minimizing the optical loss.

An emitter layer 20 having a first conductivity type impurity may be formed on the front surface of the semiconductor substrate 10. [ In the present embodiment, the emitter layer 20 is a first conductivity type impurity, and a p-type impurity such as boron (B), aluminum (Al), gallium (Ga), or indium (In) as a Group III element can be used.

The anti-reflection film 22 and the first electrode 24 are formed on the emitter layer 20 in front of the semiconductor substrate 10.

The antireflection film 22 may be formed substantially entirely on the entire surface of the semiconductor substrate 10 except for the portion where the first electrode 24 is formed. The antireflection film 22 reduces the reflectivity of light incident on the front surface of the semiconductor substrate 10 and immobilizes defects existing in the surface or bulk of the emitter layer 20. [

By decreasing the reflectance of light incident through the front surface of the semiconductor substrate 10, the amount of light reaching the pn junction formed at the interface between the semiconductor substrate 10 and the emitter layer 20 may be increased. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. In addition, the defects in the emitter layer 20 may be immobilized to remove recombination sites of the minority carriers, thereby increasing the open voltage Voc of the solar cell 100. As described above, the conversion voltage of the solar cell 100 may be improved by increasing the open voltage and the short circuit current of the solar cell 100 by the anti-reflection film 22.

The anti-reflection film 22 may be formed of various materials. For example, the antireflection film 22 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , Layer structure having a combination of at least two layers. However, the present invention is not limited thereto, and it goes without saying that the anti-reflection film 22 may include various materials.

The first electrode 24 may include various metals having excellent electrical conductivity. For example, the first electrode 24 may include silver (Ag) having excellent electrical conductivity. However, the present invention is not limited thereto, and may be formed of a single layer including a transparent conductive material, or may have a form in which a metal material layer (called “busbar” or “finger electrode”) is stacked on the transparent conductive material layer. .

In addition, a back surface field layer 30 including a second conductivity type impurity is formed on the back side of the semiconductor substrate 10 at a higher doping concentration than the semiconductor substrate 10. The rear electric field layer 30 may contribute to improving efficiency of the solar cell by minimizing rear recombination of electrons and holes. The back surface layer 30 may include phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), and the like.

In addition, a passivation film 32 and a second electrode 34 may be formed on the rear surface of the semiconductor substrate 10.

The passivation film 32 may be formed substantially on the entire rear surface of the semiconductor substrate 10 except for the portion where the second electrode 34 is formed. This passivation film 32 can pass the defects present on the back surface of the semiconductor substrate 10 to remove recombination sites of minority carriers. As a result, the open voltage Voc of the solar cell 100 may be increased.

The passivation film 32 may be made of a transparent insulating material so that light can be transmitted. Therefore, light can be incident also on the rear surface of the semiconductor substrate 10 through the passivation film 32, thereby improving the efficiency of the solar cell 100. For example, the passivation film 32 may be formed of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, any single film selected from the group consisting of MgF ₂ , ZnS, TiO _2, and CeO ₂ or two or more films. It can have a combined multilayer structure. However, the present invention is not limited thereto, and it goes without saying that the passivation film 32 may include various materials.

The second electrode 34 may include various metals having excellent electrical conductivity. For example, the second electrode 34 may include silver (Ag) having excellent electrical conductivity and high reflectance. When silver having a high reflectance is used as the second electrode 34, light exiting to the rear surface of the semiconductor substrate 10 may be reflected and directed back into the semiconductor substrate 10, thereby increasing the amount of light used.

The second electrode 34 is formed on a surface other than the light incident surface, and may have a larger width than the first electrode 24.

In the above description, the semiconductor substrate 10 has an n-type and the emitter layer 20 has a p-type, but the present invention is not limited thereto. Accordingly, the semiconductor substrate 10 may have a p-type, and the emitter layer 20 may have a n-type.

A method of manufacturing the solar cell 100 according to the present embodiment will be described in detail with reference to FIGS. 2, 3A to 3G, and FIG. 4. The above-described parts will not be described in detail, and will not be described in detail.

2 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention, and FIGS. 3A to 3G are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention. 4 is a cross-sectional view showing the step of isolating a method of manufacturing a solar cell according to an embodiment of the present invention.

Referring to FIG. 2, in the method of manufacturing a solar cell according to the present embodiment, a method of preparing a semiconductor substrate (ST10), a first doping step (ST20), an isolation step (ST30), and a second doping step ( ST40), simultaneous heat treatment (ST50), forming an antireflection film and a passivation film (ST60), and forming an electrode (ST70).

First, as shown in FIG. 3A, in the preparing of the semiconductor substrate (ST10), the semiconductor substrate 10 having the second conductivity type impurities is prepared. In this case, the front and rear surfaces of the semiconductor substrate 10 may have irregularities by texturing. As texturing, wet or dry texturing can be used. The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

Subsequently, as illustrated in FIG. 3B, in the first doping step ST20, the first layer 200 is formed by cross-sectional doping the first conductivity type impurities on the entire surface of the semiconductor substrate 10. As the cross-sectional doping, an ion implantation method, a plasma doping method, a spin on doping method, a spray doping method, or the like may be used. For example, an ion implantation method may be used.

Even when the semiconductor substrate 10 is doped only by the cross-sectional doping, unwanted doping may occur on the side surface of the semiconductor substrate 10 to form the side doped portion 202. In the drawings and description, the side doped portion 202 is formed continuously on one side of the semiconductor substrate 10, but the present invention is not limited thereto. That is, the side doped portions 202 may be partially formed to be spaced apart from each other on the side surface of the semiconductor substrate 10.

Subsequently, as illustrated in FIG. 3C, the side surface doped portion 202 formed on the semiconductor substrate 10 is removed by etching the side surface of the semiconductor substrate 10. That is, the first conductivity type impurities remaining on the side surface of the semiconductor substrate 10 are unnecessarily removed.

In this case, etching for isolation may be performed by wet etching. Such wet etching can shorten the process time and improve productivity. More specifically, in the present embodiment, etching for isolation may be performed by an inline process between the first doping step ST20 and the second doping step ST40. This can simplify the process further.

That is, referring to FIG. 4, between the first device 210 where the first doping step ST20 is performed and the second device 410 where the second doping step ST40 is performed, the frame 320 is performed. This is located. The auto transport member 310 is positioned on the frame 320, and the etching solution 330 may be accommodated between the auto transport members 310. The etching solution 330 may be positioned in the frame 320 such that only a part of the automatic transfer member 310 is locked.

In the present embodiment, the automatic transfer member 310 may have a variety of ways and structures, for example, it may be composed of a plurality of cylindrical rolls. As such, when the automatic transfer member 310 includes a cylindrical roll, the semiconductor substrate 10 is positioned on the automatic transfer member 310 in a state where the etching solution 330 is located in the space between the rolls.

That is, after the first doping step ST20 is performed, the semiconductor substrate 10 discharged from the first device 210 is laid down such that the rear surface of the semiconductor substrate 10 is located on the automatic transfer member 310 side. Is transferred to the second equipment 410 by the automatic transfer member (310). Then, the rear surface and the side surface of the semiconductor substrate 10 are brought into contact with the etching solution 330 by the rotating automatic transfer member 310, and the rear surface of the semiconductor substrate 10 while being transferred by the automatic transfer member 310. This can be etched. In this case, since the etching solution 330 contacts the side surface of the semiconductor substrate 10 due to the surface tension, the side surface of the semiconductor substrate 10 may be etched together. In the present exemplary embodiment, side surfaces of the semiconductor substrate 10 and the emitter layer 20 may be uniformly etched as a whole. As a result, it is possible to effectively remove the first conductivity type impurities remaining unnecessarily on the side surfaces of the semiconductor substrate 10.

As described above, in the present exemplary embodiment, the rear surface of the semiconductor substrate 10 is etched along with the side surface of the semiconductor substrate 10 on which the side doped portion 202 is formed. Then, the unevenness (unevenness formed by texturing) on the rear side of the semiconductor substrate 10 can be removed, thereby reducing the area of the rear surface of the semiconductor substrate 10. Thereby, the back passivation characteristic of the semiconductor substrate 10 can be improved.

In this case, the etching thickness T1 of the rear surface of the semiconductor substrate 10 may be greater than the etching thickness T2 of the side surface. For example, the etching thickness T1 of the rear surface of the semiconductor substrate 10 may be 1 to 2 μm, and the etching thickness T2 of the side surface may be 0.5 to 1 μm. In the case of exceeding the above-described range, a process time for sufficiently etching the semiconductor substrate 10 may be increased, and the efficiency of the solar cell 100 may be reduced by reducing the area where photoelectric conversion occurs. If less than the above-described range it may be difficult to remove the unnecessary side doped portion 202 sufficiently.

The etching thicknesses T1 and T2 of the semiconductor substrate 10 may be adjusted by adjusting the speed of transferring the semiconductor substrate 10 on the automatic transfer member 310 to adjust the time immersed in the etching solution 330. have.

Subsequently, as shown in FIG. 3D, in the second doping step ST40, the second layer 300 is formed by cross-doping the second conductivity type impurities on the rear surface of the semiconductor substrate 10. As the cross-sectional doping, an ion implantation method, a plasma doping method, a spin on doping method, a spray doping method, or the like may be used. For example, an ion implantation method may be used.

Subsequently, as shown in FIG. 3E, in the simultaneous heat treatment step ST50, the first and second implanted steps ST20 and ST40 are annealed to the first and second dopants by annealing the semiconductor substrate 10. Simultaneously activate conductive impurities.

In general, when the first and second conductivity type impurities are implanted into the semiconductor substrate 10, the implanted first and second conductivity type impurities are not activated at positions other than the lattice position. Annealing the semiconductor substrate 10 in this state causes the first and second conductivity-type impurities to be moved to the lattice position to be activated.

The temperature of the step ST50 may be varied depending on the first and second conductivity type impurities and the type of the semiconductor substrate 10. For example, annealing may be performed at a temperature of 950-1300 ° C., but the present invention is not limited thereto.

By the simultaneous activation, the emitter layer 20 is formed from the first layer 200 formed on the front surface of the semiconductor substrate 10, and the back surface field layer is formed from the second layer 300 formed on the rear surface of the semiconductor substrate 10. 30) is formed.

Subsequently, as shown in FIG. 3F, in the step ST60 of forming the anti-reflection film and the passivation film, the anti-reflection film 22 is formed on the front surface of the semiconductor substrate 10, and the passivation film ( 32).

The antireflection film 22 and the passivation film 32 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating.

Subsequently, as shown in FIG. 3G, in the forming of the electrode (ST70), the first electrode 24 and the rear electric field layer 30 (or the semiconductor substrate 10) are electrically connected to the second portion 20a. The second electrode 34 is electrically connected to the ()).

In the openings formed in the first passivation film 21 and the anti-reflection film 22, the first electrode 24 may be formed by various methods such as a plating method and a deposition method. An opening may be formed in the rear electric field layer 30, and the second electrode 34 may be formed in the opening by various methods such as a plating method and a deposition method.

Alternatively, the first and second electrode forming pastes are applied to the anti-reflection film 22 and the passivation film 32 by screen printing or the like, and then fire through or laser firing contact or the like is applied. It is also possible to form the first and second electrodes 32, 34 of the above-described shape. In this case, it is not necessary to carry out the step of forming the opening separately.

As described above, in the method of manufacturing a solar cell according to the present embodiment, side doping is unnecessary by etching side surfaces of the semiconductor substrate 10 between the first doping step ST20 and the second doping step ST40. The portion 202 can be removed. As a result, an electrical short (shunt) may occur when cross-sectional doping is performed on both surfaces of the semiconductor substrate 10. This will be described in more detail as follows.

In the related art, when single-sided doping is performed on both surfaces of a semiconductor substrate, it is considered that a problem such as an electrical short through the side of the semiconductor substrate does not occur. In practice, however, if the reverse current of a solar cell manufactured by doping each side on both sides is measured, the value is very high. This is expected to be due to some doping on the side of the semiconductor substrate even in the case of single-sided doping. In this case, when the reverse current is high, the saturation current of the solar cell is increased to reduce the current density and the open voltage. In addition, hot spots and heat generation may occur at the ends of the solar cell, which may greatly affect the lifetime and power.

On the other hand, in the present exemplary embodiment, the side doped portion 202 that is unnecessary by etching the side surface of the semiconductor substrate 10 between the first doping step ST20 which is the doping step and the second doping step ST40 which is the doping step. Can be removed Therefore, unnecessary electric short circuit can be prevented, so that reverse current and saturation current can be reduced, thereby improving current density and open voltage. In addition, hot spots and heat generation that may occur at the end of the solar cell 100 can be minimized. That is, the efficiency of the solar cell 100 can be improved and its life can be extended.

In addition, in the present embodiment, the back side of the semiconductor substrate 10 may also be etched together in the step of etching and isolating the side surface of the semiconductor substrate 10 to improve the passivation characteristics at the back side. That is, the characteristics of the solar cell 100 can be improved while simplifying the process.

In the above description, the emitter layer 20 and the back surface field layer 30 have a uniform doping concentration. However, the present invention is not limited thereto, and at least one of the emitter layer 20 and the rear electric field layer 30 may have a selective structure.

That is, as shown in FIG. 5, the emitter layer 20 may be formed adjacent to the anti-reflection film 22 between the first electrodes 24, the first electrode 20, and the first electrode 24. It may include a second portion 20b formed in contact and doped at a higher doping concentration than the first portion 20a and having a lower resistance than the first portion 20a.

Then, the efficiency of the solar cell 100 may be improved by implementing a shallow emitter in the first portion 20a corresponding to the first electrode 24 to which light is incident. In addition, the contact resistance with the first electrode 24 can be reduced in the second portion 20b in contact with the first electrode 24. That is, the emitter layer 20 of the present embodiment may have a selective emitter structure to maximize the efficiency of the solar cell.

In addition, the rear electric field layer 30 is formed in contact with the first portion 30a formed between the second electrodes 34 and the second electrode 34 and has a higher doping concentration than the first portion 30a. It may include a second portion 30b that is doped and has a lower resistance than the first portion 30a.

Then, while effectively preventing the recombination of electrons and holes in the first portion 30a of the rear electric field layer 30, the second portion 30b has a relatively small resistance to provide contact resistance with the second electrode 34. Can be reduced. Accordingly, the loss due to the recombination of electrons and holes is reduced, and at the same time, the ability to transfer electrons or holes generated by the photoelectric effect to the second electrode 34 is further improved, thereby further improving the efficiency of the solar cell 100a. can do.

The emitter layer 20 and the rear electric field layer 30 of this optional structure may be formed by various methods. For example, when the impurities are doped, impurities are doped at a relatively high doping concentration with respect to the portions corresponding to the second portions 20b and 30b by using a comb-shaped mask or the like, and the portions corresponding to the first portions 20a and 30a. Impurities can be doped with a relatively small doping concentration. Alternatively, an impurity doping process may be additionally performed only on the second portions 20b and 30b to form an emitter layer 20 or a backside electric field layer 30 having a selective structure.

Hereinafter, the present invention will be described in more detail with reference to examples of the present invention. However, the following experimental examples are merely illustrative of the present invention and the present invention is not limited to the following experimental examples.

Experimental Example

An n-type semiconductor substrate was prepared. The first doping step was performed by doping boron B on the entire surface of the semiconductor substrate by ion implantation. In the in-line wet etching process, an isolation step of etching the side surface of the semiconductor substrate by 0.6 μm and the back surface of the semiconductor substrate by 1.2 μm was performed. Thereafter, a second doping step was performed by doping phosphorus (P) on the rear surface of the semiconductor substrate by an ion implantation method. Annealing at 1000 ° C. simultaneously activated boron and phosphorus. As a result, an emitter layer including boron was formed, and a back field layer including phosphorus was formed.

An antireflection film was formed on the entire surface of the semiconductor substrate, and a passivation film was formed on the rear surface of the semiconductor substrate. The solar cell was completed by forming a first electrode electrically connected to the emitter layer and a second electrode electrically connected to the rear field layer.

Comparative example

A solar cell was manufactured in the same manner as in Experimental Example, except that the step of isolating was not performed.

The open voltage (Voc), current density (Jsc), charge density (FF), efficiency, the first saturation current (Jo1), the second saturation current (Jo2) of the solar cells manufactured according to the experimental and comparative examples The results are shown in Table 1. Here, the first saturation current means the saturation current in the bulk region, and the second saturation current means the saturation current in the emitter layer.

Experimental Example Comparative example Open voltage (mV) 642.7 638.2 Current density (mA) 39.1 39 Fill density (%) 78.6 78.5 efficiency(%) 19.77 19.57 First saturation current (pA) 0.48 0.57 Second saturation current (nA) 9.98 14.12

Referring to Table 1, it can be seen that in the experimental example, the values of the first and second saturation currents are significantly lower than those of the comparative example, whereby the open voltage value is much higher than that of the comparative example. Accordingly, it can be seen that the experimental example shows higher efficiency than the comparative example.

That is, in the experimental example, it can be seen that an electrical short circuit between the emitter layer and the rear electric field layer was prevented by adding an isolation step between the first doping step and the second doping step. It can be seen that the solar cell according to the experimental example has a high open voltage and efficiency.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: emitter layer
30: rear electric layer
210: first equipment
310: automatic transfer member
320: frame
330: etching solution
410: second equipment

Claims (14)

Preparing a semiconductor substrate having a first surface and a second surface opposite to each other, and side surfaces intersecting the first surface and the second surface;
A first doping to cross-dope a first conductivity type impurity to the first surface of the semiconductor substrate;
Etching the side surface of the semiconductor substrate to remove the first conductivity type impurities remaining in the corresponding portion; And
A second doping in which the second surface of the semiconductor substrate is doped with a second conductivity type impurity
Wherein the method comprises the steps of: The method of claim 1,
And in the isolating step, etching the second surface together with the side surface of the semiconductor substrate. The method of claim 2,
In the isolating step, the etching thickness of the second surface is larger than the etching thickness of the side surface of the semiconductor substrate. The method of claim 1,
The manufacturing method of the solar cell whose etching thickness of the said side surface of the said semiconductor substrate is 0.5-1 micrometer. The method of claim 2,
Etching thickness of the side surface of the semiconductor substrate is 0.5 ~ 1㎛,
The manufacturing method of the solar cell whose etching thickness of the said 2nd surface of the said semiconductor substrate is 1-2 micrometers. The method of claim 1,
The isolating step is a method of manufacturing a solar cell is performed by a wet etching method. The method of claim 1,
And said isolating step is performed by an inline process between said first doping step and said second doping step. The method of claim 1,
Between the equipment in which the first doping step is performed and the equipment in which the second doping step is performed, a frame containing an etching solution and an automatic conveying member is located,
The isolating step is performed while moving on the automatic transfer member with the rear surface of the semiconductor substrate located on the automatic transfer member side. 9. The method of claim 8,
The automatic transfer member includes a plurality of rolls manufacturing method of a solar cell. The method of claim 1,
The first doping step and the second doping step are each performed by the ion implantation method of the solar cell manufacturing method. The method of claim 1,
The semiconductor substrate includes the second conductivity type impurity,
The first conductivity type impurity includes a p type impurity,
The method for manufacturing a solar cell, wherein the second conductivity type impurity contains n type impurity. The method of claim 1,
And annealing the semiconductor substrate after the second doping to co-activate the first conductivity type impurity and the second conductivity type impurity. The method of claim 12,
The emitter layer is formed by the first conductivity type impurities doped to the first surface of the semiconductor substrate by the simultaneous activation, and the second conductivity type impurities doped to the second surface of the semiconductor substrate. The manufacturing method of the solar cell by which a back electric field layer is formed. The method of claim 13,
After the second doping step,
Forming an anti-reflection film on the first surface of the semiconductor substrate and forming a passivation film on the second surface; And
Forming a first electrode electrically connected to the emitter layer and a second electrode electrically connected to the rear field layer
Method for producing a solar cell further comprising.

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