KR20140114537A - Method for manufacturing solar cell - Google Patents

Abstract

A method of manufacturing a solar cell according to an embodiment includes: preparing a semiconductor substrate; Doping the semiconductor substrate with a conductive impurity to form an impurity layer; Depositing a passivation film on the impurity layer by atomic layer deposition; And heat treating the passivation film.

Description

[0001] METHOD FOR MANUFACTURING SOLAR CELL [0002]

The present invention relates to a method of manufacturing a solar cell, and more particularly, to a method of manufacturing a solar cell capable of improving characteristics of the solar cell.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

The solar cell may be formed by forming a conductive region and an electrode electrically connected to the conductive region on the semiconductor substrate so as to cause photoelectric conversion. In addition, a solar cell is formed with a passivation film for passivating a conductive region to improve characteristics, and an antireflection film for preventing reflection.

However, in the conventional solar cell, the passivation film may be easily deformed or damaged in the process of forming a passivation film or in a subsequent process. As a result, the passivation effect may deteriorate and the characteristics of the solar cell may be deteriorated.

The present invention provides a method of manufacturing a solar cell capable of improving characteristics of a solar cell.

A method of manufacturing a solar cell according to an embodiment includes: preparing a semiconductor substrate; Doping the semiconductor substrate with a conductive impurity to form an impurity layer; Depositing a passivation film on the impurity layer by atomic layer deposition; And heat treating the passivation film.

According to this embodiment, after the deposition of the passivation film, heat treatment can be performed to densify the passivation film, and the thickness of the silicon oxide layer formed between the passivation film and the semiconductor substrate can be reduced or the silicon oxide layer can be removed. Thereby, the passivation effect of the passivation film can be improved. In particular, it is possible to prevent a blister phenomenon that may occur in the case of a passivation film containing aluminum oxide.

Accordingly, various characteristics (for example, open voltage, current density, efficiency, etc.) of the solar cell can be improved.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
2 is a plan view of the solar cell shown in Fig.
3 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4A to 4F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
6 is a transmission electron microscope (TEM) photograph of a section of a solar cell manufactured according to Example 6. Fig.
7 is a transmission electron microscope (TEM) photograph of a section of a solar cell manufactured according to Comparative Example 5. FIG.
8 is a graph showing the measurement of the useful life according to Example 6 and Comparative Example 5. Fig.
FIG. 9 is a graph showing implied Voc results according to Example and Comparative Example 5 measured. FIG.
10 is a graph showing the current density of the solar cell according to Example 6 and Comparative Example 5 measured.
11 is a graph showing the open-circuit voltage of the solar cell according to Example 6 and Comparative Example 5 measured.
12 is a graph showing the filling density of the solar cell according to Example 6 and Comparative Example 5 measured.
13 is a graph showing the efficiency of the solar cell according to Example 6 and Comparative Example 5 measured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described with reference to the accompanying drawings. Hereinafter, a solar cell manufactured by the method of manufacturing a solar cell according to an embodiment of the present invention will be described first, and then a method of manufacturing a solar cell according to an embodiment of the present invention will be described in detail.

FIG. 1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention, and FIG. 2 is a plan view of the solar cell shown in FIG.

1, a solar cell 100 according to the present embodiment includes a substrate (e.g., a semiconductor substrate) (hereinafter, referred to as a "semiconductor substrate") 110, an impurity layer 20 30 and electrodes 24, 34 electrically connected to the impurity layers 20, 30. The impurity layers 20 and 30 may include an emitter layer 20 and a back front layer 30 and the electrodes 24 and 34 may include a first electrode 24 electrically connected to the emitter layer 20, And a second electrode 34 electrically connected to the rear front layer 30. In addition, the solar cell 100 includes a first passivation film 21, and may further include an antireflection film 22, a second passivation film 32, and the like. This will be explained in more detail.

The semiconductor substrate 110 includes a region in which the impurity layers 20 and 30 are formed and a base region 10 in which the impurity layers 20 and 30 are not formed. The base region 10 may comprise, for example, silicon containing a first conductivity type impurity. As the silicon, single crystal silicon or polycrystalline silicon may be used, and the first conductivity type impurity may be n-type, for example. That is, the base region 10 may be formed of single crystal or polycrystalline silicon doped with Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb)

When the base region 10 having the n-type impurity is used as described above, the emitter layer 20 having the p-type impurity is formed on the first surface (hereinafter referred to as the "front surface") of the semiconductor substrate 110 to form the pn junction junction. When the pn junction is irradiated with light, electrons generated by the photoelectric effect move toward the second surface (hereinafter referred to as "back surface") of the semiconductor substrate 110 and are collected by the second electrode 34, 110 and collected by the first electrode 24. Thereby, electric energy is generated. In this case, a hole having a slower moving speed than the electron moves to the front surface of the semiconductor substrate 110, not the rear surface, so that the conversion efficiency can be improved.

Although not shown in the drawing, the front surface and / or the rear surface of the semiconductor substrate 110 may be textured to have irregularities in the form of a pyramid or the like. If the surface roughness of the semiconductor substrate 110 is increased due to such irregularities formed on the front surface of the semiconductor substrate 110, the reflectance of light incident through the front surface of the semiconductor substrate 110 can be reduced. Therefore, the amount of light reaching the pn junction formed at the interface between the semiconductor substrate 110 and the emitter layer 20 can be increased, thereby minimizing optical loss.

An emitter layer 20 having a second conductivity type impurity may be formed on the front surface of the semiconductor substrate 110. In this embodiment, the emitter layer 20 may be a p-type impurity such as boron (B), aluminum (Al), gallium (Ga), indium (In) or the like as a Group III element as the second conductivity type impurity.

In this embodiment, the emitter layer 20 includes a first portion 20a having a high impurity concentration and a relatively low resistance, a first portion 20b having a lower impurity concentration than the first portion 20a and having a relatively high resistance And may have a second portion 20b. The first portion 20a is formed to be in contact with a part or all (i.e., at least a part of) the first electrode 24.

 As described above, in the present embodiment, a second portion 20b having a relatively high resistance is formed at a portion corresponding to a portion between the first electrodes 24 to which light is incident, thereby implementing a shallow emitter. Thus, the current density of the solar cell 100 can be improved. In addition, it is possible to reduce the contact resistance with the first electrode 24 by forming the first portion 20a having a relatively low resistance at the portion adjacent to the first electrode 24. [ That is, the emitter layer 20 of this embodiment can maximize the efficiency of the solar cell 100 by the selective emitter structure.

However, the present invention is not limited thereto, and the emitter layer 20 may have a homogeneous emitter structure having a uniform doping concentration. In this embodiment, the emitter layer 20 is formed only on the front surface of the semiconductor substrate 110, but the present invention is not limited thereto. That is, the emitter layer 20 may extend to the backside, and the solar cell 100 may have a rear electrode structure.

The first passivation film 21, the antireflection film 22, and the first electrode 24 are formed on the semiconductor substrate 110, more precisely on the emitter layer 20 formed on the semiconductor substrate 110.

The first passivation film 21 and the antireflection film 22 may be formed substantially entirely on the entire surface of the semiconductor substrate 110 except for the portion where the first electrode 24 is formed.

The first passivation film 21 immobilizes defects present in the surface or bulk of the emitter layer 20. The first passivation film 21 can increase the open-circuit voltage (Voc) of the solar cell 100 by immobilizing defects present in the emitter layer 20 and removing recombination sites of minority carriers.

In this embodiment, the first passivation film 21 may include aluminum oxide, zirconium oxide, hafnium oxide, or the like, which is suitable for passivation of the emitter layer 20 of p-type. These oxides can induce field effect passivation due to the high negative charge as compared with other materials used as a passivation film. Thereby effectively passivating the p-type emitter layer 20. Particularly, aluminum oxide can be used because it enables efficient passivation and is easy to manufacture.

In this embodiment, the first passivation film 21 is formed by atomic layer deposition and then heat-treated to have a densified structure. A silicon oxide layer 210 formed at the time of forming the first passivation film 21 may be positioned between the semiconductor substrate 110 (more specifically, the emitter layer 20) and the first passivation film 21 . In this embodiment, the silicon oxide layer 210 may also be densified by heat treatment after deposition to form the first passivation film 21 to reduce its thickness, and preferably the silicon oxide layer 210 may be removed . That is, in this embodiment, the silicon oxide layer 210 located between the emitter layer 20 and the first passivation film 21 may have a thickness of 1.5 nm or less, and may have a thickness of 0.01 nm to 1 nm . This will be explained in more detail in the manufacturing method of the solar cell.

The antireflection film 22 reduces the reflectance of light incident on the front surface of the semiconductor substrate 110. The amount of light reaching the pn junction formed at the interface between the base portion 10 and the emitter layer 20 can be increased by lowering the reflectance of the light incident through the front surface of the semiconductor substrate 110. Accordingly, the short circuit current Isc of the solar cell 100 can be increased.

The anti-radiation film 22 may be formed of various materials. For example, the antireflection film 22 may be formed of any one single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , And may have a combined multilayer structure. At this time, the anti-reflection film 22 may be a silicon nitride film which can be easily formed and has high reflection characteristics, or a silicon nitride film containing hydrogen. However, the present invention is not limited thereto, and it goes without saying that the anti-reflection film 22 may include various materials.

The first electrode 24 is electrically connected to the emitter layer 20 through an opening formed in the antireflection film 22 (i.e., through the antireflection film 22). The first electrode 24 may be formed to have various shapes, which will be described with reference to FIG.

A rear front layer 30 including a first conductive impurity at a doping concentration higher than that of the semiconductor substrate 110 is formed on the rear surface of the semiconductor substrate 110. In the present embodiment, the rear front layer 30 may be an n-type impurity such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb) which is a Group 5 element as the first conductive impurity.

In this embodiment, the rear front layer 30 has a first portion 30a having a high impurity concentration and a relatively low resistance and a second portion 30b having a relatively high impurity concentration and having a lower impurity concentration than the first portion 30a And may have a second portion 30b. The first portion 30a is formed to be in contact with a part or all (i.e., at least a part) of the second electrode 34. [

As described above, in this embodiment, the second portion 30b having a relatively high resistance is formed at the portion corresponding to the space between the second electrodes 34, so that recombination of holes and electrons can be prevented. Thus, the current density of the solar cell 100 can be improved. In addition, it is possible to reduce the contact resistance with the second electrode 34 by forming a first portion 30a having a relatively low resistance at a portion adjacent to the second electrode 34. [ That is, the rear front layer 30 of the present embodiment can maximize the efficiency of the solar cell 100 by the selective rear field structure.

However, the present invention is not limited thereto, and the rear front layer 30 may have a homogeneous back surface field structure having a uniform doping concentration. Alternatively, the backside front layer 30 may have a local back surface field structure formed locally only at a portion adjacent to the second electrode 34 at the rear surface of the semiconductor substrate 110. [

 In addition, a second passivation film 32 and a second electrode 34 may be formed on the rear surface of the semiconductor substrate 110.

The second passivation film 32 may be formed substantially on the entire rear surface of the semiconductor substrate 110 except for the portion where the second electrode 34 is formed. The second passivation film 32 can pass the defects present on the back surface of the semiconductor substrate 110 to remove recombination sites of minority carriers. Accordingly, the open-circuit voltage of the solar cell 100 can be increased.

The second passivation film 32 may be made of a transparent insulating material so that light can be transmitted therethrough. Therefore, light can be incident on the rear surface of the semiconductor substrate 110 through the second passivation film 32, thereby improving the efficiency of the solar cell 100. For example, the second passivation film 32 may be formed of any one single film selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , The above-described films can have a combined multi-layer film structure. However, the present invention is not limited thereto, and it goes without saying that the second passivation film 32 may include various materials.

The second electrode 34 is electrically connected to the rear front layer 30 through an opening formed in the second passivation film 32 (i.e., through the second passivation film 32). The second electrode 34 may be formed to have various shapes. That is, the first electrode 24 and / or the second electrode 34 according to the present embodiment may have various planar shapes, and an example thereof will be described with reference to FIG. Although the first electrode 24 and the second electrode 34 may have different widths, pitches, and the like, their basic shapes may be similar. Accordingly, the first electrode 24 will be mainly described in FIG. 2, and the description of the second electrode 34 will be omitted. The following description can be applied to the first and second electrodes 24 and 34 in common. Alternatively, the first electrode 24 may have the following shape and the second electrode 34 may be formed entirely on the rear surface of the semiconductor substrate 110.

Referring to FIG. 2, the first electrode 24 may include a plurality of finger electrodes 24a having a first pitch P1 and disposed in parallel with each other. In addition, the electrode 24 may include a bus bar electrode 24b formed in a direction crossing the finger electrodes 24a and connecting the finger electrodes 24a. Only one bus electrode 24b may be provided or a plurality of bus electrodes 24b may be provided with a second pitch P2 larger than the first pitch P1 as shown in FIG. At this time, the width W2 of the bus bar electrode 24b may be larger than the width W1 of the finger electrode 24a, but the present invention is not limited thereto and may have the same width. The shape of the first electrode 24 described above is merely an example, and the present invention is not limited thereto.

The finger electrode 24a and the bus bar electrode 24b are both formed through the antireflection film 22 (or the second passivation film 32 when the second electrode 34 is the same) . Alternatively, the finger electrode 24a may pass through the antireflection film 22 and the bus bar electrode 24b may be formed on the antireflection film 22.

As described above, in the present embodiment, the first passivation film 21 for passivating the p-type emitter layer 20 is made of aluminum oxide, zirconium oxide, hafnium oxide, or the like suitable for passivation of the p- . This first passivation film 21 is formed by thermal treatment after being deposited by an atomic layer deposition method capable of deposition at a low temperature. As a result, the first passivation film 21 can have a densified structure, and a problem (for example, the first passivation film 21 including aluminum oxide) generated in the process of forming the first passivation film 21 It is possible to prevent a blister phenomenon that may occur in the case of forming. Accordingly, the current density, open voltage, efficiency, etc. of the solar cell 100 can be improved. The manufacturing method of the solar cell 100 will be described in detail with reference to FIG. 3 and FIGS. 4A to 4F.

FIG. 3 is a flow chart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention, and FIGS. 4A to 4F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

Referring to FIG. 3, a method of manufacturing a solar cell according to an embodiment of the present invention includes a step ST10 of preparing a substrate, a step ST20 of forming an impurity layer, a step ST30 of forming a first passivation film, And forming a second passivation film (ST40) and forming an electrode (ST50). Each step will be described in detail with reference to Figs. 4A to 4F.

First, as shown in FIG. 4A, a semiconductor substrate 110 having a first conductivity type impurity is prepared in a step ST10 of preparing a substrate. In this embodiment, the semiconductor substrate 110 may be made of silicon having an n-type impurity. As the n-type impurity, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used.

Although not shown in the drawing, at least one of the front surface and the rear surface of the semiconductor substrate 110 can be textured.

Texturing can be either wet or dry texturing. The wet texturing can be performed by immersing the semiconductor substrate 110 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 110 is cut by using a diamond grill or a laser, so that irregularities can be uniformly formed, but the processing time is long and damage to the semiconductor substrate 110 may occur. As described above, the semiconductor substrate 110 can be textured in various ways in the present invention.

Subsequently, as shown in FIG. 4B, at least one of the emitter layer 20 and the rear front layer 30, which is an impurity layer, is formed in the step of forming the impurity layer (ST20).

That is, in this embodiment, the emitter layer 20 and the rear front layer 30 may be formed by doping the semiconductor substrate 110 with conductive impurities by various methods such as ion implantation and thermal diffusion. At this time, an ion implantation method suitable for doping different impurities on the front surface and both surfaces of the semiconductor substrate 110 can be used. For example, the emitter layer 20 and the rear front layer 30 having an optional structure can be formed by a method such as ion implantation using a comb mask.

As another example, only the emitter layer 20 may be formed on the semiconductor substrate 110 in the step of forming the impurity layer (ST20). The backside front layer 30 may be formed at a later stage. For example, the backside front layer 30 may be formed by a method of diffusing a material contained in the second electrode 34 in the process of forming the second electrode 34 or the like.

The emitter layer 20 may have a p-type conductivity type including a p-type impurity which is a second conductivity type impurity. As the p-type impurity, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) can be used.

The back front layer 30 may have an n-type impurity so as to have a higher doping concentration than the base region 10. As the n-type impurity, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used.

Next, as shown in FIGS. 4C and 4D, a first passivation film 21 is formed in a step ST30 of forming a first passivation film. At this time, the step of forming the first passivation film (ST30) may include a deposition step (ST32) and a heat treatment step (ST34). This will be explained in more detail.

First, as shown in FIG. 4C, in the deposition step ST32, aluminum oxide, zirconium oxide, and hafnium oxide are deposited by atomic layer deposition to form a first passivation film 21. For example, the aluminum oxide layer may be formed by atomic layer deposition using a precursor material such as trimethyl aluminum (TMA) and an oxidizing agent (e.g., H ₂ O).

Atomic layer deposition is a technique of forming a layer by increasing the atomic layer by one layer, which can form a film with high surface defect density, excellent film density, and excellent stability. In addition, the deposition can be performed at a low temperature of 300 to 500 ° C, so that the cost can be reduced and the stability can be improved by the low temperature process.

At this time, in this embodiment, the deposition film 21a is formed thicker than the desired thickness. This is because the thickness of the vapor deposition film 21a is reduced by the subsequent heat treatment. In one example, the thickness T1 of the vapor deposition film 21a may be 12 nm to 30 nm (more specifically, 18 nm to 25 nm).

When the deposition film 21a is formed by the atomic layer deposition method, silicon constituting the semiconductor substrate 110 reacts with oxygen used in the atomic layer deposition method to form a silicon oxide layer 21b may be formed. In one example, the thickness T2 of the silicon oxide layer 21b may be between 2 nm and 5 nm (4 to 5 nm in the worst case). The silicon oxide layer 21b is a layer which is inevitably formed when the evaporation film 21a is formed by the atomic layer deposition method, but is a layer that can lower the passivation property of the first passivation film 21. [

Next, as shown in FIG. 4D, in the heat treatment step ST32, the vapor deposition film formed by atomic layer deposition (see reference numeral 21a in FIG. 4C, the same applies hereinafter) is densified by heat treatment to form the first passivation film 21 ).

In the heat treatment step ST34, the temperature is higher than the process temperature of the atomic layer deposition method, so that the outgassing of the deposition film 21a can be performed. Thus, the vapor deposition film 21a can be densified. As a result, the thickness T3 of the first passivation film 21 becomes smaller than the thickness T1 of the vapor deposition film 21a. For example, the ratio (T3 / T1) of the thickness T3 of the first passivation film 21 to the thickness T1 of the vapor deposition film 21a may be 0.6 to 0.8, and the thickness of the first passivation film 21 (T3) may be between 8 nm and 20 nm (more precisely between 8 nm and 15 nm).

The thickness of the silicon oxide layer 21b located between the semiconductor substrate 110 and the deposition film 21a may also be reduced or the silicon oxide layer 21b may be removed by the outgassing effect in the heat treatment step ST34 . That is, the thickness T4 of the silicon oxide layer 21b after the step ST34 which is subjected to the heat treatment is smaller than the thickness T2 of the silicon oxide layer 21b before the heat treatment step ST34. For example, the thickness T4 of the silicon oxide layer 210 after the heat treatment step ST34 may be 1.5 nm or less, and may be 0.01 nm to 1 nm, for example.

More specifically, after the semiconductor substrate 110 on which the evaporation film 21a is formed is placed in a heat treatment furnace, the temperature is raised at a rate of 10 ° C / min to 20 ° C / min, and a heat treatment temperature Lt; / RTI > If the rate of temperature rise is less than 10 ° C / minute, the process time may be prolonged. If the rate of temperature rise exceeds 20 ° C / minute, thermal stress may be applied to the semiconductor substrate 110. After reaching the heat treatment temperature of 400 ° C to 600 ° C, the heat treatment can be performed for 30 minutes to 1 hour. If the heat treatment temperature is lower than 400 占 폚, the effect of densifying the vapor deposition film 21a may not be sufficient. If the heat treatment temperature exceeds 600 ° C, the characteristics of the solar cell may be deteriorated and the process temperature may become high, which may increase the process time and increase the cost. The heat treatment time is determined as a time sufficient to achieve the effect of the heat treatment and not to excessively increase the process time.

After the heat treatment at 400 ° C. to 600 ° C. is completed, the semiconductor substrate 110 on which the first passivation film 21 is formed is directly taken out from the heat treatment furnace without lowering the temperature, and the process time is reduced and the first passivation film 21 can be further improved. However, the present invention is not limited thereto. Therefore, it is also possible to further carry out the step of lowering the temperature separately after the heat treatment at 400 ° C to 600 ° C.

The gas atmosphere in the heat treatment step (ST34) may be a nitrogen gas atmosphere. If a gas other than nitrogen gas is used, an undesired layer may occur due to reaction with the semiconductor substrate 110 or the like.

As described above, according to the present embodiment, after the deposition is performed by the atomic layer deposition method, the first passivation film 21 is formed by performing the heat treatment. Accordingly, the first passivation film 21 has a densified structure, and the passivation effect can be increased by reducing the thickness of the silicon oxide layer 210 or removing the silicon oxide layer 210.

In this embodiment, the blister phenomenon that may occur when the first passivation film 21 including aluminum oxide is formed can be prevented. This will be explained in more detail. Aluminum oxide itself has a stable arrangement, but the blister phenomenon that swells in the process of forming the first passivation film 21 or in a subsequent process can easily occur. If the blister phenomenon occurs as described above, the first passivation film 21 swells up and it is difficult to exhibit a sufficient passivation effect, thereby lowering the filling density of the solar cell. Accordingly, in this embodiment, blistering can be prevented by densifying the first passivation film 21 by performing a heat treatment for densification after deposition of the vapor deposition film 21a.

4E, the antireflection film 22 and the second passivation film 32 are formed on the front and rear surfaces of the semiconductor substrate 110 in the step of forming the antireflection film and the second passivation film ST40, do. The antireflection film 22 and the second passivation film 32 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating.

4F, in the step of forming the electrode (ST50), the first electrode 24 contacting the emitter layer 20 is formed on the entire surface of the semiconductor substrate 110, and the semiconductor substrate 110 The second electrode 34 contacting the rear front layer 30 is formed.

An opening is formed in the first passivation film 21 and the antireflection film 22 and the first electrode 24 can be formed in the opening by various methods such as a plating method and a vapor deposition method. An opening is formed in the second passivation film 32, and the second electrode 34 can be formed in this opening by various methods such as a plating method and a vapor deposition method.

Alternatively, the first and second electrode forming paste may be applied to the first passivation film 21, the antireflection film 22 and the second passivation film 32 by screen printing or the like, It is also possible to form the first and second electrodes 24 and 34 having the above-described shape by laser firing contact or the like. In this case, it is not necessary to carry out the step of forming the opening separately.

According to the manufacturing method of the solar cell 100 according to this embodiment, the first passivation film 21 can be densified and the blister phenomenon can be prevented, and the passivation effect of the first passivation film 21 can be sufficiently realized have. Thus, the current density, lifetime, and open-circuit voltage of the solar cell 100 can be improved.

The emitter layer 20 and the rear front layer 30 are formed and the first passivation film 21 is formed and then the antireflection film 22 and the second passivation film 32 are formed And then the first and second electrodes 24 and 34 are formed. However, the present invention is not limited thereto. Therefore, the order of forming the emitter layer 20, the backside front layer 30, the antireflection film 22, the second passivation film 32, the first electrode 24, and the second electrode 34 may be variously modified .

In the above-described embodiment, the first passivation film 21 for passivating the emitter layer 20 located on the front surface includes aluminum oxide, zirconium oxide, or hafnium oxide. However, the present invention is not limited thereto. That is, the second passivation film 32 for passivating the front whole layer 30 may include aluminum oxide, zirconium oxide, or hafnium oxide. This embodiment will be described with reference to Fig.

5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

5, the solar cell 102 according to the present embodiment includes a semiconductor substrate 110, an emitter layer 20 and a rear front layer 30 formed on the semiconductor substrate 110, And may include a first electrode 24 and a second electrode 34 connected to each other. In addition, the solar cell 100 may further include an antireflection film 22, a second passivation film 32, and the like. This will be explained in more detail.

In this embodiment, contrary to the embodiment of FIG. 1, the semiconductor substrate 110 and the rear front layer 30 have a p-type and the emitter layer 20 has an n-type. The types of impurities which have n-type or p-type are the same as those described above, and therefore, detailed description thereof will be omitted.

Although not shown in the drawing, a textured concave-convex structure may be formed on the front surface of the semiconductor substrate 110.

The antireflection film 22 may be formed of various materials. For example, the antireflection film 22 may be formed of any one single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , And may have a combined multilayer structure. For example, the antireflection film 22 may be a silicon nitride film or a silicon nitride film containing hydrogen. However, the present invention is not limited thereto, and it goes without saying that the anti-reflection film 22 may include various materials. Further, a first passivation film (not shown) may be further provided between the semiconductor substrate 110 and the antireflection film 22 for passivation.

Here, in this embodiment, the second passivation film 32 for passivating the rear front layer 30, which is a p-type conductivity type region, may have a structure including aluminum oxide, zirconium oxide, or hafnium oxide and a dense structure. A silicon oxide layer 310 formed at the time of forming the second passivation film 32 may be positioned between the semiconductor substrate 110 (more specifically, the rear front layer 30) and the second passivation film 32 have. The material, characteristics, manufacturing method, etc. of the silicon oxide layer 310 and the second passivation film 32 are similar to those of the silicon oxide layer 210 and the first passivation film 21 in the embodiment of FIG. 1, It is omitted.

As described above, when the second passivation film 32 for passivating the rear whole layer 30, which is a p-type conductivity type region, contains aluminum oxide having a densified structure, the second passivation film It is possible to reduce the cost and process time for forming the barrier ribs 32 and prevent the blister phenomenon. Thus, the characteristics and productivity of the solar cell 102 can be improved.

Hereinafter, the present invention will be described in more detail with reference to examples of the present invention. However, the following experimental examples are merely illustrative of the present invention and the present invention is not limited to the following experimental examples.

<Experimental Example 1>

Example  One

an n-type semiconductor substrate was prepared. Boron (B) was doped on the entire surface of the semiconductor substrate to form an emitter layer. Then, phosphorus (P) is doped to the rear surface of the semiconductor substrate to form a rear whole layer. An aluminum oxide layer having a thickness of 30 nm was formed on the entire surface of the semiconductor substrate by atomic layer deposition, and the aluminum oxide layer was heated at a rate of 20 DEG C per minute to reach 400 DEG C and then held for 30 minutes to form a first passivation film. An antireflection film including a silicon nitride film was formed, and a second passivation film including a silicon oxide film and a silicon nitride film was formed on the rear surface of the semiconductor substrate.

Example  2

A solar cell was manufactured in the same manner as in Example 1 except that aluminum oxide was formed to a thickness of 16 nm in the deposition step of forming the first passivation film and the heat treatment time was 60 minutes in the heat treatment step.

Example  3

A solar cell was manufactured in the same manner as in Example 1 except that the heat treatment time of the step of forming the first passivation film was 60 minutes.

Example  4

A solar cell was prepared in the same manner as in Example 1, except that aluminum oxide was formed to a thickness of 16 nm in the deposition step of forming the first passivation film.

Example  5

In the step of forming the first passivation film, aluminum oxide was formed to have a thickness of 22 nm, and in the step of heat-treating, in the same manner as in Example 1 except that the heat treatment temperature was maintained at 600 ° C and the heat treatment time was 45 minutes, A solar cell was manufactured.

Comparative Example  One

In the deposition step of forming the first passivation film, aluminum oxide was formed to a thickness of 16 nm and heat treatment was carried out in the same manner as in Example 1 except that the heat treatment temperature was maintained at 800 占 폚 and the heat treatment time was 60 minutes. A solar cell was manufactured.

Comparative Example  2

Three solar cells were fabricated in the same manner as in Example 1, except that the aluminum oxide was formed to a thickness of 16 nm in the deposition step of forming the first passivation film and the heat treatment temperature was maintained at 800 캜 in the heat treatment step .

Comparative Example  3

Three solar cells were manufactured in the same manner as in Example 1, except that the heat treatment temperature was maintained at 800 占 폚 in the heat treatment step of forming the first passivation film.

Comparative Example  4

A solar cell was manufactured in the same manner as in Example 1, except that the heat treatment temperature was maintained at 800 占 폚 and the heat treatment time was 60 minutes in the heat treatment step of forming the first passivation film.

The implied Voc of the solar cells according to Examples 1 to 5 and Comparative Examples 1 to 4 was measured and the results are shown in Table 1 below.

Heat treatment temperature [캜] Heat treatment time [min] Aluminum oxide layer thickness [nm] Implied Voc [mV] Example 1 400 30 30 676.6 Example 2 400 60 16 677.6 Example 3 400 60 30 674.0 Example 4 400 30 16 678.0 Example 5 600 45 22 664.0 600 45 22 658.3 600 45 22 659.5 Comparative Example 1 800 60 16 598.6 Comparative Example 2 800 30 16 603.6 Comparative Example 3 800 30 30 603.6 Comparative Example 4 800 60 30 601.6

Referring to Table 1, it can be seen that the solar cells according to Examples 1 to 5 have a significantly higher implied Voc than the solar cells according to Comparative Examples 1 to 4. That is, after the atomic layer deposition, heat treatment is performed at 400 ° C to 600 ° C to improve the characteristics of the solar cell by improving implied Voc characteristics. On the other hand, in Comparative Examples 1 to 4 where the heat treatment temperature is 800 ° C, implied Voc has a low value.

<Experimental Example 2>

Example  6

In the step of forming the first passivation film, aluminum oxide was formed to have a thickness of 15 nm, and in the step of heat-treating, the solar cell was manufactured in the same manner as in Example 1, except that the heat treatment temperature was 600 캜 and the heat treatment time was 60 minutes Respectively.

Comparative Example  5

A solar cell was fabricated in the same manner as in Example 6, except that aluminum oxide was formed to a thickness of 15 nm in the deposition step of forming the first passivation film and heat treatment was not performed.

6 and 7 show transmission electron microscope (TEM) photographs of a cross section of the solar cell manufactured according to Example 6 and Comparative Example 5. As shown in FIG. Referring to FIG. 6, in Example 6, it is understood that the aluminum oxide layer is densified by the heat treatment step so that the first passivation film has a thickness of 12 nm and the silicon oxide layer has a thickness of 0.8 nm. On the other hand, referring to FIG. 7, it can be seen that in Comparative Example 5, the aluminum oxide layer is less dense than the first passivation film and has a thickness of 15 nm and the silicon oxide layer has a thickness of 2.6 nm. That is, according to the present invention, it is understood that the first passivation film for passivating the p-type impurity layer has a densified structure, thereby improving the characteristics of the solar cell and preventing the blister phenomenon.

The effective lifetime and implied Voc results according to Example 6 and Comparative Example 5 were measured and the results are shown in FIGS. 8 and 9, respectively. And graphs of current density, open-circuit voltage, fill factor and efficiency of the solar cell according to Example 6 and Comparative Example 5 are shown in FIGS. 10 to 13, respectively.

Referring to FIG. 8, it can be seen that the solar cell according to Example 6 has a much longer useful life than the solar cell according to Comparative Example 5. Referring to FIG. 9, it can be seen that the solar cell according to Example 6 has a much higher implied Voc than the solar cell according to Comparative Example 5.

10 to 13, the solar cell according to Example 6 has a similar charge density to that of the solar cell according to Comparative Example 5, and has a much better current density, open-circuit voltage and efficiency . &Lt; / RTI &gt; 10, the current density of the solar cell according to Example 6 is higher than the current density of the solar cell according to Comparative Example 5 by about 0.1 mA. 11, the open-circuit voltage of the solar cell according to the sixth embodiment is about 3.5 mA higher than the open-circuit voltage of the solar cell according to the fifth comparative example. Referring to FIG. 12, it can be seen that the solar cell according to Example 6 has a higher filling density than the solar cell according to Comparative Example 5. 13, the efficiency of the solar cell according to the sixth embodiment is about 0.2% higher than that of the solar cell according to the fifth comparative example.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
110: semiconductor substrate
10: Base area
20: Emitter layer
21: First passivation film
22: Antireflection film
24: first electrode
30: rear front layer
32: second passivation film
34: Second electrode

Claims (16)

Preparing a semiconductor substrate;
Doping the semiconductor substrate with a conductive impurity to form an impurity layer;
Depositing a passivation film on the impurity layer by atomic layer deposition; And
A step of heat-treating the passivation film
Wherein the method comprises the steps of: The method according to claim 1,
Wherein the heat treatment temperature in the heat treatment step is 400 ° C to 600 ° C. 3. The method of claim 2,
Wherein the heat treatment time in the heat treatment step is 30 minutes to 1 hour. 3. The method of claim 2,
Wherein the temperature rising rate is from 10 ° C / min to 20 ° C / min before reaching the heat treatment temperature in the heat treatment step. 3. The method of claim 2,
And the semiconductor substrate is taken out of the heat treatment furnace without a temperature lowering section after the heat treating step. The method according to claim 1,
Wherein the passivation film comprises at least one of an aluminum oxide film, a zirconium oxide film, and a hafnium oxide film. The method according to claim 1,
Wherein the passivation film comprises an aluminum oxide film. The method according to claim 1,
Wherein the heat treatment step is performed in a nitrogen gas atmosphere. The method according to claim 1,
Wherein the thickness of the passivation film after the heat treatment is smaller than the thickness of the passivation film before the heat treatment. 10. The method of claim 9,
Wherein the thickness of the passivation film before the heat treatment is 12 nm to 30 nm and the thickness of the passivation film after the heat treatment is 8 nm to 20 nm. 11. The method of claim 10,
Wherein a thickness of the passivation film before the heat treatment is 18 nm to 25 nm and a thickness of the passivation film after the heat treatment is 8 nm to 15 nm. 11. The method of claim 10,
Wherein the thickness ratio of the passivation film after the heat treatment to the thickness of the passivation film before the heat treatment is 0.6 to 0.8. The method according to claim 1,
Wherein a silicon oxide layer is formed between the semiconductor substrate and the passivation film in the deposition step. The method according to claim 1,
Wherein the thickness of the silicon oxide layer after the heat treatment is smaller than the thickness of the silicon oxide layer before the heat treatment step or the silicon oxide layer is removed in the heat treatment step. 15. The method of claim 14,
Wherein the thickness of the silicon oxide layer before the heat treatment is 2 nm to 5 nm and the thickness of the silicon oxide layer after the heat treatment is 1.5 nm or less. 16. The method of claim 15,
Wherein the thickness of the silicon oxide layer after the heat-treating step is 0.1 nm to 1 nm.

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