KR20130015925A - Semiconductor memory device - Google Patents

Abstract

The present invention improves the configuration of the row select driver and provides a semiconductor memory device capable of reducing the layout by providing a drive signal that transitions between the precharge voltage and the ground voltage through one transistor. In an embodiment, a semiconductor memory device generates a word line driving signal based on a row address signal and a block selection signal and provides the word line driving signal to a word line, and controls the voltage of the word line in response to the word line driving signal. A word line driver including a transistor, and a plurality of memory cells connected to a word line and a bit line crossing the word line, respectively, wherein the word line is driven in response to the word line driving signal.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a row address driver of a semiconductor memory device.

Semiconductor memory devices used in portable devices are required to be highly integrated due to the characteristics of the portable devices. In addition, it is required to reduce the power consumption of the semiconductor memory device in order to continue the power supply of the portable device.

Recently, in order to increase the integration of semiconductor memory devices, an integrated circuit is designed in three dimensions or a research on a nonvolatile memory device using a resistance material has been made. The nonvolatile memory device using a resistor may include a phase change random access memory (PCRAM), a ferroelectric memory (FeRAM), and a magnetic RAM (MRAM).

Dynamic memory devices (DRAMs) or flash memory devices use charge to store data, while nonvolatile memory devices that use resistors are in the state of phase change materials such as chalcogenide alloys. Data is stored using change (PCRAM), resistance change (RRAM) of the variable resistor, resistance change (MRAM) of the magnetic tunnel junction (MTJ) thin film according to the magnetization state of the ferromagnetic material, and the like.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device that can be miniaturized by reducing the layout by improving the structure of a word line driver for selecting a word line of a memory cell array including a word line and a bit line. .

According to an exemplary embodiment, a semiconductor memory device generates and provides a word line driving signal to a word line based on a row address signal and a block selection signal, and controls a voltage of the word line in response to the word line driving signal. A word line driver including a driving transistor, and a plurality of memory cells respectively connected to the word line and a bit line crossing the word line, wherein the word line is driven in response to the word line driving signal.

The semiconductor memory device according to example embodiments may reduce the layout by improving a configuration of a word line driver that selects a plurality of word lines.

In addition, the semiconductor memory device may reduce the word line driving time and thus may operate at a high speed.

In addition, the semiconductor memory device according to the embodiments of the present invention does not leave the unselected word lines floating, thereby reducing leakage current, thereby reducing power consumption.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) device.
2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.
3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
4 and 5 are circuit diagrams illustrating an example embodiment of the semiconductor memory device of FIG. 3.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are diagrams for explaining a conventional phase change resistor (PCR) element 10.

When the phase change resistance element 10 applies a voltage and a current by inserting a phase change material (PCM) 12 between the top electrode 11 and the bottom electrode 13, a phase is applied. The high temperature is induced in the change layer 12 to change the electrical conduction state according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 12. In addition, the phase change layer 12 uses a chalcogenide (chalcogenide) mainly composed of chalcogen elements (S, Se, Te). ₂ Sb ₂ Te ₅ ) can be used.

2A and 2B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 2A, when a small current of less than or equal to the threshold flows through the phase change resistance element 10, the phase change layer 12 is at a temperature suitable for crystallization, and thus the phase change layer 12 is in a crystalline phase. ) To become a material of low resistance state.

On the other hand, as shown in FIG. 2B, when a large current of more than a threshold flows through the phase change resistance element 10, the phase change layer 12 is at a temperature above the melting point, and thus a high resistance material in an amorphous phase. Becomes

As described above, the phase change resistive element 10 may store data corresponding to two resistance states, and the phase change resistive element 10 may be used in a nonvolatile memory device because the state of the phase change resistive element 10 does not change even when the power is cut off.

3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device 300 may include a memory cell array 310 and a word line driver 320. Although not illustrated, the semiconductor memory device 300 may include an address decoder, a sense amplifier, a precharge circuit, and the like.

The memory cell array 310 may include a plurality of memory cells connected between a word line and a bit line crossing the word line. The memory cells may store data, output the stored data to the outside, and may include resistive memory cells having different resistance values according to the stored data as described above.

The word line driver 320 drives a plurality of word lines based on the plurality of row address signals X0, ..., Xl-1 and the plurality of block selection signals BS0, ..., BSl-1. Signals A0, ..., Al-1 may be generated. The word line driver 320 performs a logical operation on the plurality of row address signals X0, ..., Xl-1 and the plurality of block selection signals BS0, ..., BSl-1. Word line driving signals A0,..., And Al-1 may be generated, and a plurality of word line driving signals A0,..., Al-1 may be generated in the memory cell array 310. Are connected to four word lines.

Since the semiconductor memory device 300 according to an embodiment of the present invention drives each of the plurality of word lines based on one word line driving signals A0,. It can be implemented more simply than a word line driver that hierarchically drives word lines, such as a local word line, and can reduce the layout of the semiconductor memory device 300.

4 is a circuit diagram illustrating an example embodiment of the semiconductor memory device of FIG. 3.

Referring to FIG. 4, the semiconductor memory device 300a may include a memory cell array 310a and a word line driver 320a.

The memory cell array 310a may include a plurality of memory cells MC, each memory cell MC having a phase change material GST connected in series between a bit line BL and a word line WL. And a diode (D). The phase change material GST may have a different resistance value based on the voltage between the bit line BL and the word line WL, and may allow a different current to flow based on the resistance value. In FIG. 4, although the diode D is included in the memory cell MC, the diode D serves to supply voltage or current to the phase change resistor GST in a predetermined direction, and includes a selection transistor. It may be implemented in the form.

For example, when the first word line compensation driving signal / A0 provided to the first word line WL0 is activated, the first word line compensation driving signal / A0 may be precharged to have a voltage value corresponding to the boosted voltage VPP. In the case where the voltage of the bit line BL is less than or equal to the boost voltage VPP, the memory cells connected to the first word line WL0 are inactivated.

On the contrary, when the first word line compensation driving signal / A0 is deactivated, that is, when the first word line driving signal A0 is activated, the first word line WL0 is a voltage corresponding to the ground voltage VSS. It may have a value, and a current may be provided to the memory cells MC according to the voltage of the bit line BL to write data.

The word line driver 320a may include word line drivers 321a, 322a, 323a, ... corresponding to each word line of the memory cell array 310a.

The first word line driver 321a may include a first logic operator L1, a first inverter I11, a second inverter I12, and a first driving transistor DN0.

The first logic operator L1 and the second inverter I12 perform a logic operation on the first row address signal X0 and the first block selection signal BS0 to provide a first word line driving signal A0. can do. According to an embodiment, the first logic operator L1 and the second inverter I12 may perform an AND logic operation. That is, the first word line driving signal A0 is activated to have a voltage level corresponding to the boosted voltage VPP when both the first row address signal X0 and the first block selection signal BS0 are configured. Can be. In some embodiments, the word line driver 320a may be driven by the boosted voltage VPP. Therefore, the word line driving signals A0, A1, A2,... Generated by the word line driver 320a may transition between the ground voltage VSS and the boost voltage VPP.

The first driving transistor DN0 is connected to a gate to which the first word line driving signal A0 is applied, a first terminal to which the ground voltage VSS is applied, and a first word line WL0 to drive the first word line. The signal A0 may include a second terminal receiving the first word line compensation driving signal / A0 inverted by the first inverter I11.

When the first word line driving signal A0 is activated, the first driving transistor DN0 may be turned on to pull the first word line WL0 down to the ground voltage VSS. Memory cells connected to the word line WL0 may be activated to write data based on voltages applied to the plurality of bit lines BL0, BL1,..., BLn-1.

When the first word line driving signal A0 is inactivated, the first driving transistor DN0 is turned off, and the first word line compensation copper signal / A0 is activated by the first inverter I11 to generate the first word line driving signal A0. One word line WL0 may be inactivated by the boosted voltage VPP to maintain a precharge state or to block current or voltage from flowing into the memory cell from the bit lines BL0, BL1, ..., BLn-1. have.

Therefore, the semiconductor memory device 300a according to an exemplary embodiment may drive a word line based on one word line driving signal, and may also boost the voltage VPP and the ground voltage regardless of whether the word line is selected. By fixing the voltage of the word line between the (VSS) it is possible to minimize the power consumption by blocking the leakage current that can occur when the word line is floating (floating).

Since the configuration of the second and third word line drivers 322a and 323a included in the wordline driver 320 is substantially the same as the configuration of the first wordline driver 321a, the operation characteristics thereof are also the same. Detailed description will be omitted.

5 is a circuit diagram illustrating another example of the semiconductor memory device of FIG. 3.

Compared with the semiconductor memory device 300a of FIG. 4, the semiconductor memory device 300b of FIG. 5 includes a plurality of driving transistors corresponding to the number of memory cells in which each word line driver is connected to the bit line BL. DN).

In the case of including the plurality of driving transistors DN, when the voltage of the word lines WL is transitioned, the state of the word line may be stabilized sooner.

In FIG. 5, the same elements as in FIG. 4 are illustrated using the same reference numerals, and detailed description thereof will be omitted below.

Referring to FIG. 5, the semiconductor memory device 300b may include a plurality of wordline drivers 321b, 322b, 323b,... And a wordline driver with reference to the first wordline driver 321b. To explain the configuration and operation of the.

The first word line driver 321b may operate the first logic operator L1, the first and second inverters I11 and I12, and the plurality of first driving transistors DN01, DN02, DN03,... It may include.

The plurality of first driving transistors DN01, DN02, DN03,..., A gate to which the first word line driving signal A0 is applied, a first terminal to which the ground voltage VSS is applied, and a first word are respectively provided. The first word line driving signal A0 may be connected to the line WL0 and may include a second terminal receiving the first word line compensation driving signal / A0 inverted by the first inverter I11.

However, each of the first driving transistors DN01, DN02, DN03, ... is connected between the bit lines BL0, BL1, ..., BLn-1 included in the memory cell array 310b. The voltage of the word line corresponding to each memory cell MC can be adjusted.

That is, the driving transistors DN0, DN1, and DN2 included in the word line driver 320a of FIG. 4 correspond to one word line, but the word line driver 320b of FIG. 5 is connected to one word line. When the driving transistors are connected to each of the memory cells to change the voltage of the word line, the transition speed may be improved.

For example, when the first word line WL0 transitions from the boosted voltage VPP to the ground voltage VSS, the plurality of driving transistors are connected to the word line rather than one driving transistor pulling down the voltage of the word line. Driving voltage can be improved by simultaneously pulling the voltage down to ground voltage (VSS).

Accordingly, the semiconductor memory device according to an embodiment of the present invention can reduce the layout by simplifying the configuration of a word line driver for driving a plurality of word lines and reduce leakage current by not leaving unselected word lines in a floating state. Can be.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

300, 300a, 300b: semiconductor memory device
310, 310a, 310b: memory cell array
320, 320a, 320b: wordline drivers

Claims (6)

A word line driver generating a word line driving signal based on a row address signal and a block selection signal and providing the word line driving signal to a word line, the driving transistor controlling a voltage of the word line in response to the word line driving signal; And
And a plurality of memory cells respectively connected to the word line and a bit line crossing the word line, wherein the word line is driven in response to the word line driving signal. The method according to claim 1,
The word line driver,
And a plurality of word line drivers respectively driving the word lines included in the memory cell array. The method according to claim 2,
The word line driver,
A logic calculator configured to generate the wordline driving signal by performing a logic operation on the row address signal and the block selection signal;
An inverter configured to invert the wordline driving signal to generate a wordline compensation driving signal; And
And at least one driving transistor connecting the word line and a ground voltage in response to the word line driving signal. The method according to claim 3,
The driving transistor,
And a second terminal receiving the word line driving signal, a first terminal receiving the ground voltage, and a second terminal connected to the word line and receiving the word line compensation driving signal. The method according to claim 1,
And the word line driving signal transitions between a boosted voltage and a ground voltage. The method according to claim 1,
And the memory cell array includes a plurality of phase change memory cells having different resistance values based on voltages applied to both ends of the phase change element, including a phase change element.

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