JP6137180B2 - Programming circuit, semiconductor device, and programming method - Google Patents

Description

  The present invention relates to a programming circuit for writing data to a variable resistance nonvolatile element (hereinafter referred to as “resistance variable element”), a semiconductor device including the programming circuit, and a programming method for the variable resistance element.

  In recent years, MRAM (Magnetic Random Access Memory), PRAM (Phase Change Random, Memory), which has a resistance change element in a memory cell, is a non-volatile memory that can rewrite a large amount of data at high speed with low power consumption. Access memory), ReRAM (resistive random access memory), etc. are attracting attention.

  For example, the MRAM is a storage device that stores data by using the characteristic that the magnetization direction of a ferromagnetic material set by an external magnetic field remains in the ferromagnetic material even after the magnetic field is removed.

  The resistance change element used in each memory cell of the MRAM has, for example, a configuration having two ferromagnetic layers and an insulating layer sandwiched between the two ferromagnetic layers. Of these two ferromagnetic layers, the magnetization direction of one ferromagnetic layer (fixed layer) is the reference magnetization direction, and the magnetization direction of the other ferromagnetic layer (free layer) is changed according to the stored data. To do. In this resistance change element, the tunnel currents flowing in the insulating layers differ depending on the coincidence / mismatch of the magnetization directions of the two ferromagnetic layers, and logic “1” or “ 0 "is assigned.

  At the time of data writing, the current direction is determined according to the data to be stored, and the magnetization direction of the ferromagnetic layer (free layer) for data storage is set by the magnetic field induced by this current.

  As a data writing method for the MRAM, there is a current magnetic field writing method in which a current is passed through a write wiring provided in the vicinity of the free layer and the magnetization direction of the free layer is reversed by a magnetic field generated by the current. There is also a spin injection magnetization reversal method in which the magnetization direction of the free layer is reversed by passing a current directly through the resistance change element.

  The PRAM is a storage device that stores data by using a characteristic that a phase change material changes to a crystalline state or an amorphous state by an externally supplied current. The resistance change element used in each memory cell of the PRAM has a configuration including two electrodes and a phase change layer made of a phase change material sandwiched between the two electrodes. This resistance change element has different electric resistance depending on the crystal structure of the phase change layer, and logic “1” or “0” is assigned to these two different electric resistances.

  As a method of writing data to the PRAM, there is a method of changing the crystal structure of the phase change layer by flowing a pulsed current corresponding to the data to be stored through the resistance change element. As a typical phase change material used in a PRAM memory cell, a chalcogenide alloy is known, for example, Ge2Sb2Te5 made of germanium (Ge), antimony (Sb), and tellurium (Te). This phase change material is commonly referred to as “GST”.

  The phase change material (GST) reversibly changes to a crystalline state or an amorphous state by Joule heat generated by flowing a pulsed current (programming current). Generally, the state in which the phase change material is crystallized is called a set state, and the phase change material in the set state has a low electrical resistance. On the other hand, the state in which the phase change material is non-crystallized is called a reset state, and the phase change material in the reset state has a higher electrical resistance than the set state. When the phase change material (GST) is changed to the reset state, a relatively large current is allowed to flow with a short pulse width. On the other hand, when changing the phase change material (GST) to the set state, a current smaller than the reset programming current pulse is supplied with a long pulse width.

  ReRAM uses a variable resistance element, that is, a switching element, having a characteristic that a conductive path is formed inside when a voltage or current is supplied from the outside, or the formed conductive path disappears. Is a storage device.

  The variable resistance element used in each memory cell of the ReRAM has a configuration including two electrodes and a variable resistance element film sandwiched between the two electrodes. This resistance change element has different electric resistances depending on the presence or absence and shape of conductive paths (filaments) formed in the resistance change element film. For example, logic “1” or “0” is assigned to these different electric resistances. It is done.

  When writing data into the ReRAM, the voltage value, current value, and pulse width corresponding to the data to be stored are determined, and the filament structure formed inside the resistance change element film is set.

  For example, Non-Patent Document 1 includes, as a switching element (resistance change element) applicable to ReRAM, an ion conductor that is a solid in which ions can freely move by application of an electric field or the like, and the ion conduction A solid electrolyte switch is described that can control the formation / disappearance of conductive paths (filaments) using the movement of metal ions and electrochemical reactions in the body.

  The switching element disclosed in Non-Patent Document 1 includes an ion conductive layer made of an ion conductor, and a first electrode (active electrode) and a second electrode (inactive electrode) provided to face each other across the ion conductive layer. It is the structure which has. The first electrode has a role of supplying metal ions to the ion conductive layer. Metal ions are not supplied from the second electrode to the ion conductive layer.

  The operation of the switching element disclosed in Non-Patent Document 1 will be briefly described.

  For example, when the inert electrode of the switching element is grounded and a positive voltage is applied to the active electrode, metal ions in the ion conductive layer are deposited as metal. At this time, the metal in the active electrode becomes metal ions and dissolves in the ion conductive layer, so that the balance of positive and negative ions in the ion conductive layer is maintained. The metal deposited in the ion conductive layer forms a metal bridge (filament) that connects the active electrode and the inert electrode, and the switching element is turned on by connecting the active electrode and the inert electrode by this metal bridge. It becomes a state.

  On the other hand, when the active electrode is grounded and a positive voltage is applied to the inactive electrode in the ON state, a part of the metal bridge is dissolved and disappears due to the reverse electrochemical reaction. As a result, the connection between the active electrode and the inactive electrode is disconnected, and the switching element is turned off.

  By the way, in the variable resistance element used in the MRAM, PRAM, ReRAM, etc., it is appropriate to write (program) desired data in each memory cell including the variable resistance element without increasing the circuit area. It is important to pass a write current.

  FIG. 1 is a circuit diagram showing an equivalent circuit of a memory cell including a resistance element of the background art.

  As shown in FIG. 1, the memory cell of the background art has a resistance change element 101 having one end connected to a plate line (PL) 102 and the other end of the resistance change element 101 having different electric resistances depending on stored data. Is turned on or off by a signal voltage (word voltage) applied to the word line (WL) 105, and the other end of the resistance change element 101 is connected to the bit line line (BL) when turned on. ) 103 and an access transistor (AT) 106 connected to 103. In MRAM, PRAM, ReRAM, and the like, the memory cells shown in FIG. 1 are arranged in a matrix to form a memory cell array that holds data.

  When data is written to the variable resistance element 101 shown in FIG. 1, for example, the bit line line (BL) 103 is grounded and a predetermined programming voltage is applied to the plate line (PL) 102. Further, in the state where the programming voltage is applied to the plate line (PL) 102, the access transistor (AT) 106 is turned on by applying a pulsed signal voltage to the word line (WL) 105, and the resistance change element 101. The required pulse current is supplied to

  In the memory cell having such a configuration, the magnitude of the current flowing to the variable resistance element 101 during data writing (programming) depends on the current driving capability of the access transistor (AT) 106. Therefore, when a large programming current is required, an access transistor (AT) 106 having a large current driving capability, that is, a large area access transistor (AT) 106 is required. Some variable resistance elements 101 have a characteristic that the electrical resistance after programming decreases as the programming current increases, for example. When such variable resistance element 101 is used, a relatively large programming current is required.

  However, the large-area access transistor (AT) 106 becomes a factor that hinders high integration of a semiconductor device that stores data using the resistance change element 101 and an increase in storage capacity.

  A technique for reducing the programming current itself of the variable resistance element is described in Patent Document 1, for example. A technique for suppressing the peak power supply current of the semiconductor device during programming is described in Patent Document 2, for example.

  In Patent Document 1, an effective value of a programming current is reduced by supplying a current having a waveform that overshoots at the time of rising, generated by using two current source circuits, to the resistance change element for MRAM. Along with this, it is described that the programming time (pulse width) is shortened.

  Further, in Patent Document 2, a capacitor or a charge pump circuit is provided in the PRAM, and the charge accumulated in the capacitor included in the capacitor or the charge pump circuit is supplied to the variable resistance element at the time of programming. Suppressing the peak power supply current of the PRAM.

  The technique described in Patent Document 1 described above requires a circuit (current source) for generating a current waveform having an overshoot in addition to a circuit for writing data to the variable resistance element. Therefore, the circuit area for each memory cell is increased.

  Further, the technique described in Patent Document 2 requires a relatively large capacitor or a charge pump circuit including a large capacitor in order to supply a required programming current to the variable resistance element. Therefore, even the technique described in Patent Document 2 causes an increase in circuit area.

  That is, the techniques described in Patent Documents 1 and 2 do not contribute to high integration of a semiconductor device and an increase in storage capacity even if the programming current and the peak power supply current of the semiconductor device during programming can be suppressed. Absent.

Japanese Patent No. 4837013 JP 2008-165964 A

M. Tada, K. Okamoto, T. Sakamoto, M. Miyamura, N. Banno, and H. Hada, "Polymer Solid-Electrolyte (PSE) Switch Embedded on CMOS for Nonvolatile Crossbar Switch", vol. 58, no. 12 , pp.4398-4405, (2011).

  Accordingly, the present invention provides a programming circuit for writing data to a resistance change element, a semiconductor device including the programming circuit, and a method for programming the resistance change element, which can be highly integrated and have a large storage capacity. The purpose is to do.

In order to achieve the above object, the programming circuit of the present invention includes a variable resistance element that changes its state and changes its electrical resistance when a predetermined voltage is applied and a current flows.
A first load capacitor connected between a ground side terminal of the variable resistance element and a ground potential;
A switching transistor and a second load capacitor connected in series connected between a ground-side terminal of the variable resistance element and a ground potential;
Have

On the other hand, the semiconductor device of the present invention includes the programming circuit,
A drive circuit that applies a predetermined voltage to the variable resistance element and supplies a current necessary for the change in the electrical resistance to the variable resistance element;
Have

Further, the resistance change element programming method of the present invention is a resistance change element programming method in which an electrical resistance is changed by flowing a predetermined current supplied from the outside,
A first load capacitor is connected between the ground side terminal of the variable resistance element and the ground potential;
A switching transistor and a second load capacitor connected in series are further connected between the ground side terminal of the variable resistance element and the ground potential,
Supplying a current having a waveform having an overshoot, including an inrush current generated to charge the first load capacity when supplying a current necessary for the change in the electrical resistance ;
When the state of the resistance change element changes, the switching transistor is turned on to connect the second load capacitor to the ground side terminal of the resistance change element,
In the reading of the resistance value of the variable resistance element, the switching transistor is turned off to disconnect the second load capacitor from the ground side terminal of the variable resistance element .

It is a circuit diagram which shows the equivalent circuit of the memory cell provided with the resistive element of background art. It is a circuit diagram which shows the structural example of the programming circuit of the resistance change element of 1st Embodiment. FIG. 3 is a schematic diagram illustrating a configuration example of a resistance change element illustrated in FIG. 2. FIG. 3 is a schematic diagram illustrating a waveform example of a programming current flowing through the variable resistance element illustrated in FIG. 2. It is a circuit diagram which shows the structural example of the programming circuit of the resistance change element of 2nd Embodiment. FIG. 6 is a circuit diagram illustrating a configuration example of a semiconductor device including the programming circuit illustrated in FIG. 5. It is a schematic diagram which shows the example of a waveform of the programming current which flows into the resistance change element shown in FIG. It is a circuit diagram which shows the example of 1 structure of a semiconductor device provided with the programming circuit of 3rd Embodiment. It is a schematic diagram which shows the example of a waveform of the programming current which flows into the resistance change element shown in FIG. It is a circuit diagram which shows one structural example of a bit line drive circuit and a plate line drive circuit. It is a graph which shows distribution of the resistance value of a resistance change element when programming conditions are changed. It is a block diagram which shows the structural example of the principal part of the semiconductor device of this invention.

Next, the present invention will be described with reference to the drawings.
(First embodiment)
First, a first embodiment of the present invention will be described with reference to the drawings.

  Below, the example which uses the solid electrolyte switch (switching element) described in the said nonpatent literature 1 is demonstrated as a resistance change element. The same applies to second to fifth embodiments described later.

  FIG. 2 is a circuit diagram illustrating a configuration example of a resistance variable element programming circuit according to the first embodiment.

  As illustrated in FIG. 2, the programming circuit according to the first embodiment includes a resistance change element 201 and a load capacitor 204.

  The variable resistance element 201 has one end connected to the plate line (PL) 202 and the other end connected to the bit line (BL) 203. The load capacitor 204 is connected between the bit line (BL) 203 and the ground potential. The load capacitance 204 may be realized by a parasitic capacitance of the bit line (BL) 203, for example. When the load capacitor 204 is realized by the parasitic capacitance of the bit line (BL) 203, for example, the wiring width of the bit line (BL) 203 may be set according to a desired capacitance. Note that the load capacitor 204 may be realized by a fixed capacitor.

  FIG. 3 is a schematic diagram illustrating a configuration example of the resistance change element illustrated in FIG. 2.

  The resistance change element shown in FIG. 3 includes an ion conductor 301 capable of moving metal ions therein, and an inactive electrode 303 and an active electrode 302 arranged with the ion conductor 301 interposed therebetween. For the ion conductor 301, a thin film made of an oxide, an organic polymer, chalcogenide, or the like is used. A metal electrode such as Pt or Ru is used for the inactive electrode 303. As the active electrode 302, an electrode containing Cu, Ag, or a metal thereof is used.

  Next, a programming method for the variable resistance element 201 according to the first embodiment will be described with reference to the drawings.

  Here, the active electrode 302 of the resistance change element 201 shown in FIG. 3 is connected to the plate line (PL) 202 shown in FIG. 2, and the inactive electrode 303 shown in FIG. BL) 203. Further, here, the bit line (BL) 203 is grounded, a positive voltage is applied to the plate line (PL) 202, and a current flows through the resistance change element 201, so that the resistance change element 201 is lowered from the high resistance state. An example of programming to the resistance state will be described.

  FIG. 4 is a schematic diagram showing a waveform example of a programming current flowing through the variable resistance element shown in FIG.

  In the first embodiment, at time t1, a programming voltage having a pulse width Wp (t2-t1) is applied to the plate line (PL) 202 shown in FIG. The programming voltage is set to a voltage value required to change the electrical resistance of the resistance change element 201 (change the state).

When a pulsed programming voltage is applied to the plate line (PL) 202, an inrush current indicated by an arrow flows through the resistance change element 201 to charge the load capacitor 204 when the programming voltage rises. That is, the current I _W flowing through the resistance change element 201 has an overshoot (maximum current Imax) in the inrush current generation period W 1 as shown in FIG. 4, and is then determined by the programming voltage and the resistance value of the resistance change element 201. A waveform in which a substantially constant current Iset flows is obtained.

  During programming, in order to generate the inrush current shown in FIG. 4, the load capacitor 204 needs to be connected to the ground side terminal (downstream side of the current) of the resistance change element 201. On the other hand, the resistance change element 201 grounds the plate line (PL) 202 shown in FIG. 2 and applies a programming voltage to the bit line (BL) 203 in order to change from the low resistance state to the high resistance state. In some cases, a programming current is passed in the opposite direction.

  In general, the resistance change element 201 has a different programming current value for changing from a high resistance state to a low resistance state and a programming current value for changing from a low resistance state to a high resistance state. Depending on the element structure, one of the programming currents is set larger than the other programming current. Therefore, for example, when a larger programming current is passed through the resistance change element 201, the load capacitor 204 may be arranged so as to be positioned on the ground side terminal of the resistance change element 201, that is, on the downstream side of the current. The same applies to the second to fifth embodiments described later.

  According to the present embodiment, by providing the load capacitance 204 on the ground potential side of the resistance change element 201, the resistance change element 201 has an overshoot without adding a current source circuit or the like as in Patent Document 1 described above. A programming current can flow. Therefore, the effective value of the programming current can be reduced, and the programming time (pulse width) can be shortened. Further, since the load capacitor 204 can be realized by, for example, the parasitic capacitance of the bit line BL, the circuit area is not increased. Therefore, high integration of a semiconductor device including a resistance change element and an increase in storage capacity can be realized.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 is a circuit diagram illustrating a configuration example of a resistance variable element programming circuit according to the second embodiment.

  As shown in FIG. 5, the programming circuit of the second embodiment includes a resistance change element 501, a load capacitor 504, and an access transistor (AT) 506.

  One end of the resistance change element 501 is connected to the plate line (PL) 502 via the access transistor (AT) 506, and the other end is connected to the bit line (BL) 503. The load capacitor 504 is connected between the bit line (BL) 503 and the ground potential. The load capacitor 504 may be realized by a parasitic capacitance of the bit line (BL) 503, for example, as in the first embodiment. The load capacity 504 may be realized by a fixed capacity element.

  As the access transistor (AT) 506, for example, an NMOS (Negative channel Metal Oxide Semiconductor) transistor is used. The gate electrode of access transistor (AT) 506 is connected to word line (WL) 505, the drain electrode of access transistor (AT) 506 is connected to one end of resistance change element 501, and the source electrode of access transistor (AT) 506 is A plate line (PL) 502 is connected. In other words, the access transistor (AT) 506 applies a predetermined programming voltage to the variable resistance element 501 and the variable resistance element 501 and supplies a voltage source (non-current) that supplies a current necessary for a change in electrical resistance to the variable resistance element 501. Are connected in series.

  FIG. 6 is a circuit diagram showing a configuration example of a semiconductor device including the programming circuit shown in FIG.

  As shown in FIG. 6, the programming circuit shown in FIG. 5 can be used as a memory cell MC for storing data. Connected to the plate line (PL) 502 is a read amplifier 507 which is a circuit for reading data stored in the variable resistance element 501 shown in FIG. A control transistor 509 for controlling the potential of the bit line (BL) 503 is connected to the bit line (BL) 503.

  When data stored in the resistance change element 501 shown in FIG. 6 is read, for example, the bit line (BL) 503 is grounded, and a constant read current is supplied to the plate line (PL) 502. In this state, when a predetermined word voltage is applied to the access transistor (AT) 506 to turn it on, a voltage corresponding to the resistance value of the resistance change element 501 is generated on the plate line (PL) 502. The read amplifier 507 compares the resistance value of the resistance change element 501, that is, the logic “1” stored in the resistance change element 501 by comparing a predetermined reference voltage generated in advance with the voltage of the plate line (PL) 502. "Or" 0 "can be detected.

  Next, a programming method according to the second embodiment will be described with reference to the drawings.

  Here, as in the first embodiment, the active electrode (see FIG. 3) of the resistance change element 501 is connected to the plate line (PL) 502 via the access transistor (AT) 506, and the resistance change element 501 It is assumed that the inactive electrode is connected to the bit line (BL) 503. Also, here, the bit line (BL) 503 is grounded using the control transistor 509, and the access transistor (AT) 506 is turned on while a positive voltage (programming voltage) is applied to the plate line (PL) 502. An example in which a current is passed through the resistance change element 501 and the resistance change element 501 is programmed from a high resistance state to a low resistance state will be described.

  FIG. 7 is a schematic diagram showing a waveform example of a programming current flowing through the variable resistance element shown in FIG.

  As shown in FIG. 7, in the second embodiment, first, at time t1, the programming voltage VPL is applied to the plate line (PL) 502 shown in FIG. The programming voltage VPL may be set to a voltage value necessary for changing the electric resistance of the resistance change element 501.

  Next, at time t2, a predetermined word voltage VWL is applied to the word line (WL) 505 shown in FIG. 6 to turn on the access transistor (AT) 506, and a programming voltage VPL is applied to the resistance change element 501.

  When the programming voltage VPL is applied to the resistance change element 501, an inrush current for charging the load capacitor 504 flows through the resistance change element 501 when the programming voltage VPL rises. That is, the current Isn of the resistance change element 501 has an overshoot (maximum current Imax) in the inrush current generation period W1, and then a substantially constant current Iset determined by the programming voltage VPL and the resistance value of the resistance change element 501. It becomes a flowing waveform.

  When programming to the resistance change element 501 is completed, at time t4, the application of the word voltage VWL to the word line (WL) 505 is stopped, the access transistor (AT) 506 is turned off, and the programming voltage is applied to the resistance change element 501. Stop. Finally, at time t5, application of the programming voltage VPL to the plate line (PL) 502 shown in FIG. 6 is stopped.

According to the present embodiment, by providing the memory cell MC including the access transistor (AT) 506 and the resistance change element 501 with the load capacitor 504, a current source circuit or the like is added as in the first embodiment. In other words, a programming current having an overshoot can be supplied to the variable resistance element 501. Therefore, the effective value of the programming current can be reduced, and the programming time (pulse width) can be shortened. Further, since the load capacitor 504 can be realized by, for example, the parasitic capacitance of the bit line (BL) 503, the circuit area is not increased. Therefore, high integration of a semiconductor device including the resistance change element 501 and an increase in storage capacity can be realized.
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 8 is a circuit diagram illustrating a configuration example of a semiconductor device including the programming circuit according to the third embodiment.

  As shown in FIG. 8, the programming circuit of the third embodiment includes a resistance change element 901, a switching transistor 908, a first load capacitor 904, a second load capacitor 910, and an access transistor (AT) 906.

  One end of the resistance change element 901 is connected to the plate line (PL) 902 via the access transistor (AT) 906, and the other end is connected to the bit line (BL) 903.

  The first load capacitor 904 is connected between the bit line (BL) 903 and the ground potential. The first load capacitor 904 may be realized by the parasitic capacitance of the bit line (BL) 903 as in the first and second embodiments. The first load capacitor 904 may be realized by a fixed capacitor element.

  The second load capacitor 910 has one end connected to the ground potential and the other end connected to the bit line (BL) 903 via the switching transistor 908. That is, the switching transistor 908 and the second load capacitor 910 are connected in series and inserted between the ground-side terminal of the resistance change element 901 and the ground potential. The second load capacitor 910 may be realized by a fixed capacitor element, for example.

  As the access transistor (AT) 906, for example, an NMOS transistor is used. The gate electrode of access transistor (AT) 906 is connected to word line (WL) 905, the drain electrode of access transistor (AT) 906 is connected to one end of resistance change element 901, and the source electrode of access transistor (AT) 906 is A plate line (PL) 902 is connected. That is, the access transistor (AT) 906 applies a predetermined programming voltage to the resistance change element 901, and supplies a voltage source (not shown) that supplies a current necessary for changing the electrical resistance to the resistance change element 901. The element 901 is connected in series.

  A read amplifier 907 that is a circuit for reading data stored in the resistance change element 901 is connected to the plate line (PL) 902. A control transistor 909 for controlling the potential of the bit line (BL) 903 is connected to the bit line (BL) 903.

  Next, a programming method according to the third embodiment will be described with reference to the drawings.

  Here, as in the first and second embodiments, the active electrode (see FIG. 3) of the resistance change element 901 is connected to the plate line (PL) 902 via the access transistor (AT) 906 to change the resistance. It is assumed that the inactive electrode of the element 901 is connected to the bit line (BL) 903. Also, here, the control transistor 909 is used to ground the bit line (BL) 903 and the access transistor (AT) 906 is turned on while a positive voltage (programming voltage) is applied to the plate line (PL) 902. An example will be described in which a current is passed through the resistance change element 901 and the resistance change element 901 is programmed from a high resistance state to a low resistance state.

  FIG. 9 is a schematic diagram showing a waveform example of a programming current flowing through the variable resistance element shown in FIG. FIG. 9 shows only the waveform of a current flowing through the resistance change element 901 shown in FIG. 8 during programming. The voltage waveforms applied to the plate line (PL) 902, the bit line (BL) 903, and the word line (WL) 905 are the same as those in the second embodiment shown in FIG. 9 corresponds to t2 shown in FIG. 7, and t2 shown in FIG. 9 corresponds to t4 shown in FIG.

As shown in FIG. 9, also in the third embodiment, when the access transistor (AT) 906 is turned on and a predetermined programming voltage is applied to the resistance change element 901, the resistance change occurs at the rise of the programming voltage. An inrush current for charging the first load capacitor 904 flows through the element 901. That is, the current I _W flowing through the resistance change element 901 has an overshoot (maximum current Imax) in the inrush current generation period W1, as shown in FIG. 9, and is then determined by the programming voltage and the resistance value of the resistance change element 901 A waveform in which a substantially constant current Iset flows is obtained.

  In the present embodiment, when the resistance change element 901 is programmed (state change), the switching transistor 908 is turned on to connect the first load capacitor 904 and the second load capacitor 910 between the bit line (BL) 903 and the ground potential. This is a possible configuration. The switching transistor 908 is turned on / off according to a control signal supplied from a control unit (not shown). When the first load capacitor 904 and the second load capacitor 910 are connected to the bit line (BL) 903, the first load capacitor 904 and the second load capacitor 910 are connected to the resistance change element 901 when the programming voltage rises. Inrush currents for charging each flow. Therefore, a current having an overshoot (maximum current Imax) flows through the resistance change element 901 in the inrush current generation period W2. However, W1 <W2.

  According to the third embodiment, the same effects as those of the first and second embodiments can be obtained, and the overshoot period of the programming current can be changed by turning the switching transistor 908 on or off. . Therefore, when the resistance change element 901 has a different resistance value after the state change depending on the magnitude of the programming current, the resistance value after the state change of the resistance change element 901 is set smaller by turning on the switching transistor 908. it can.

In the configuration of this embodiment, when the load capacitance connected between the bit line (BL) 903 and the ground potential is increased, the voltage of the plate line (PL) 902 is read when data stored in the resistance change element 901 is read. Takes time to stabilize, and there is a possibility that the data reading speed becomes slow. Therefore, when reading data (when reading the resistance value of the resistance change element 901), it is desirable to turn off the switching transistor 908 and disconnect the second load capacitor 910 from the bit line (BL) 903.
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to the drawings.

  In the fourth embodiment, the bit line driving circuit for driving the bit line and the plate line used for programming the resistance change element shown in the first to third embodiments are described. A plate line driving circuit for driving will be described.

  FIG. 10 is a circuit diagram illustrating a configuration example of the bit line driving circuit and the plate line driving circuit. A bit line driving circuit (BD) 12A shown in FIG. 10 is provided for each bit line (BL) included in the semiconductor device, and a plate line driving circuit (PD) 12B shown in FIG. PL) is provided for each.

  As shown in FIG. 10, the bit line driving circuit (BD) 12A and the plate line driving circuit (PD) 12B are arranged at both ends of a memory cell (MC) including a resistance change element 1001, a load capacitor 1004, and an access transistor (AT) 1006. Connected to.

  The bit line driving circuit (BD) 12A includes a PMOS (Positive channel Metal Oxide Semiconductor) transistor PT1 connected between the voltage source and the bit line (BL), and an NMOS transistor connected between the bit line (BL) and the ground node. NT1, a timing control circuit 1110 for generating timing control signals CSLP and / CSLN indicating timing for writing (programming) data in the memory cell in accordance with a column selection signal CSL transmitted from a column decoder (not shown), and a memory cell ( MC) outputs the logical product of the write data WDATA, which is the data to be written to MC), and the timing control signal CSLP, and calculates the logical sum of the NAND gate NAND1 that drives the PMOS transistor PT1, and the write data WDATA and the timing control signal / CSLN. Output And a NOR gate NOR1 to drive the N-channel MOS transistor NT1.

  The plate line driving circuit (PD) 12B includes a PMOS transistor PT2 connected between the voltage source and the plate line (PL), an NMOS transistor NT2 connected between the plate line (PL) and the ground node, and a column decoder (not shown). A timing control circuit 1120 for generating timing control signals CSLP and / CSLN indicating a timing for writing (programming) data in the memory cell (MC) in accordance with a column selection signal CSL transmitted from the figure, and write data / WDATA and timing A logical product of the control signal CSLP is output, a NAND gate NAND2 that drives the PMOS transistor PT2, a logical sum of the write data / WDATA and the timing control signal / CSLN, and a NOR gate NO that drives the NMOS transistor NT2 And a 2.

  In such a configuration, for example, when programming the variable resistance element 1001 shown in FIG. 10 from the high resistance state to the low resistance state, first, according to the column selection signal CSL, the N channel MOS transistor NT1 included in the bit line driving circuit (BD). The P channel MOS transistors PT2 included in the plate line driving circuit (PD) are turned on. At this time, in the variable resistance element 1001, the inactive electrode (see FIG. 3) is grounded.

  Next, it is turned on by applying a pulsed word voltage to the gate electrode of the access transistor (AT) 1006. At this time, a predetermined programming voltage (power supply voltage VPL) is applied to the active electrode (see FIG. 3) of the resistance change element 1001.

  When a predetermined programming voltage is applied to the resistance change element 1001, an inrush current for charging the load capacitor 1004 flows through the resistance change element 1001 when the programming voltage rises. Therefore, a current having an overshoot flows through the resistance change element 1001 as described in the first to third embodiments, and then is almost determined by the programming voltage and the resistance value of the resistance change element 1001. A constant current flows. Therefore, a programming current having an overshoot can be supplied to the resistance change element 1001 without adding a current source circuit or the like.

  FIG. 11 is a graph showing the distribution of resistance values of the variable resistance element when the programming conditions are changed. FIG. 11 shows how the resistance value of the variable resistance element changes with respect to the area (gate width) of the access transistor (AT) when the variable resistance element is programmed from the high resistance state to the low resistance state. In addition, the solid electrolyte switch mentioned above shall be used for a resistance change element. In addition, the resistance change element is programmed using the circuit shown in FIG. In FIGS. 11A and 11B, the distribution of measured values (resistance values) with respect to the total number of measurements is shown by setting the vertical axis of the graph to “percent”.

  FIG. 11A shows the low resistance of the variable resistance element when the load capacitance is 2 fF or less and the gate width W of the access transistor (AT) is changed to 0.2 μm, 0.3 μm, 0.5 μm, and 1 μm. The distribution of resistance values in the state is shown. The bit line drive circuit (BD) 12A and the plate line drive circuit (PD) 12B are designed so that the parasitic capacitance on the ground potential side (NT1 side) is larger than that on the power supply voltage side (PT2 side). And

  The area of the access transistor (AT) is proportional to the gate width W, and the larger the gate width W, the greater the current driving capability. As shown in FIG. 11A, it can be seen that the access transistor (AT) having a larger gate width W has a smaller resistance value of the resistance change element after programming. This is because when a large current flows when transitioning from a high resistance state to a low resistance state, copper metal deposited in the ionic conductor increases, and a thick filament (bridge) is formed, resulting in a low resistance value. It is to become. That is, it can be seen that when the load capacitance is small, no inrush current flows, so that the current flowing through the resistance change element is limited according to the current driving capability of the access transistor (AT).

  FIG. 11B shows a variable resistance element when a load capacitance of 4 fF is connected to the bit line and the gate width W of the access transistor (AT) is changed to 0.2 μm, 0.3 μm, 0.5 μm, and 1 μm. The distribution of resistance values in the low resistance state is shown.

  As shown in FIG. 11B, when a large load capacitance is connected to the bit line, the resistance value of the resistance change element after programming does not depend on the gate width W of the access transistor (AT). It turns out that it becomes a small value. This indicates that by passing a programming current having an overshoot, a low resistance value can be obtained in the resistance change element after programming without depending on the current driving capability of the access transistor AT.

When the width of the inrush current (overshoot width) is calculated using a known electronic circuit simulator (such as SPICE), when the load capacity is 3 fF, the inrush current width is 0.2 nsec and the load capacity is 4 fF. In this case, the width of the inrush current was 0.3 nsec. In general, it is known that a resistance change element requires a time of 100 psec or more to change its state (change in electrical resistance). In the configuration including the load capacitance as shown in the present embodiment, if the load capacitance is set to 3 fF or more, an inrush current having a duration longer than the time required for the change in the electrical resistance can be obtained. It becomes possible to program stably.
(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 12 is a block diagram showing a configuration example of a main part of the semiconductor device of the present invention. FIG. 12 shows one configuration of a semiconductor device including the programming circuit shown in the first to third embodiments and the bit line driving circuit and the plate line driving circuit shown in the fourth embodiment. An example is shown. In FIG. 12, only the configuration necessary for writing data to the variable resistance element is shown, and the other configurations are omitted. A semiconductor device includes a circuit for reading data, an input / output circuit for inputting / outputting data, a control unit for generating a control signal for operating the semiconductor device in a predetermined mode from a plurality of commands received from the outside, a semiconductor Various circuits according to the specifications of the semiconductor device are provided, such as an internal power supply voltage generation circuit for generating an internal power supply voltage used inside the device. Note that a control signal for turning on / off the switching transistor 908 shown in FIG. 8 is supplied from, for example, the control unit.

  As shown in FIG. 12, the semiconductor device has a memory cell array 1100 in which a large number of memory cells (MC) are arranged in a matrix. The memory cell (MC) has a configuration including the resistance change element, the access transistor, and the load capacitor described in the second embodiment and the third embodiment.

  A bit line (BL) and a plate line (PL) are arranged in each column of the memory cells MC, and a word line WL is arranged in each row of the memory cells MC.

  A bit line driving circuit 12A shown in FIG. 10 is connected to the bit line BL, and a plate line driving circuit 12B shown in FIG. 10 is connected to the plate line PL.

  A column decoder 1200 that generates a column selection signal that specifies a column of the memory cell array 1100 to be written or read is connected to the bit line driving circuit 12A and the plate line driving circuit 12B. The column decoder 1200 decodes the column address signal YA received from the outside via a buffer circuit (not shown) to generate a column selection signal.

  The bit line driving circuit 12A drives the bit line BL corresponding to the column selected according to the column selection signal supplied from the column decoder 1200 when data is written to the memory cell array 1100. The plate line driving circuit 12B drives the plate line PL corresponding to the column selected according to the column selection signal supplied from the column decoder 1200 when writing data to the memory cell array 1100. Driving the bit line BL and the plate line PL means setting the bit line BL or the plate line PL to the ground potential or applying a predetermined programming voltage.

  The word line WL corresponds to a row selected according to a row selection signal for designating a row of the memory cell array 1100 to be written or read when data is written to the memory cell array 1100 and when data is read from the memory cell array 1100. A word line drive circuit 1300 for supplying a word voltage to the word line WL to be connected is connected.

  A row decoder 1400 that generates a row selection signal is connected to the word line drive circuit 1300. The row decoder 1400 decodes the row address signal XA received from outside via a buffer circuit (not shown) to generate a row selection signal.

  According to this embodiment, by having the memory cell MC including the resistance change element, the access transistor, and the load capacitance, a programming current having an overshoot is caused to flow through the resistance change element due to the inrush current for charging the load capacitance. Can do. Therefore, a low resistance value can be obtained in the resistance change element after programming without depending on the current drive capability of the access transistor. Accordingly, since it is not necessary to provide an access transistor having a large area in each memory cell, it is possible to realize high integration of a semiconductor device including a resistance change element and an increase in storage capacity.

  In each of the above-described embodiments, the example in which the solid electrolyte switch is used as the variable resistance element has been described. However, the present invention is also applicable to the case of programming another variable resistance element in which the electric resistance is changed by passing a current. Is possible.

  In each of the above-described embodiments, the variable resistance element has been described as an example of using as a memory cell that stores data. However, the variable resistance element can also be used as a switching element for other purposes such as a crossbar switch. It is.

  The switching circuit of the present invention can be confirmed from the structure of the semiconductor device after manufacture. Specifically, the position of the variable resistance element connected to the multilayer wiring is specified by observing a cross section of the semiconductor chip to be observed using a TEM (Transmission Electron Microscope). Then, the semiconductor chip to be observed is polished from the upper surface, and the wiring layout connected to the resistance change element is detected using an optical microscope or SEM (scanning electron microscope). Furthermore, by measuring the width of the wiring, it is possible to estimate the load capacitance connected to the variable resistance element.

  Although related to the technology node of the semiconductor device, since the parasitic capacitance of the wiring is about 0.2 fF / μm, when the wiring having a width of 15 μm or more is used, the programming method of the present invention may be used. Can be judged to be high.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of Japanese Patent Application No. 2012-143037 for which it applied on June 26, 2012, and takes in those the indications of all here.

Claims (8)

A resistance change element that changes its state and changes its electrical resistance when a predetermined voltage is applied and a current flows;
A first load capacitor connected between a ground side terminal of the variable resistance element and a ground potential;
A switching transistor and a second load capacitor connected in series connected between a ground-side terminal of the variable resistance element and a ground potential;
A programming circuit.   An access transistor connected in series between the variable resistance element and a voltage source that applies a predetermined voltage to the variable resistance element and supplies a current necessary for the change of the electrical resistance to the variable resistance element. The programming circuit of claim 1 further comprising: When the state of the resistance change element changes, the switching transistor is turned on to connect the second load capacitor to the ground side terminal of the resistance change element, and when the resistance value of the resistance change element is read, the switching transistor is turned off. 3. The programming circuit according to claim 1, further comprising a control unit that disconnects the second load capacitance from a ground-side terminal of the resistance change element. The first load capacity is
Programming circuit according to any one of claims 1-3 ground side terminal is parasitic capacitance of the line connected to the variable resistance element. Wherein the first load capacitance, the programming circuit according to any one of claims 1 4 at least 3 fF. A programming circuit according to any one of claims 1 to 5 ;
A drive circuit that applies a predetermined voltage to the variable resistance element and supplies a current necessary for the change in the electrical resistance to the variable resistance element;
A semiconductor device. A method of programming a resistance change element that is supplied from the outside and changes its electrical resistance when a predetermined current flows,
A first load capacitor is connected between the ground side terminal of the variable resistance element and the ground potential;
A switching transistor and a second load capacitor connected in series are further connected between the ground side terminal of the variable resistance element and the ground potential,
Supplying a current having a waveform having an overshoot, including an inrush current generated to charge the first load capacity when supplying a current necessary for the change in the electrical resistance ;
When the state of the resistance change element changes, the switching transistor is turned on to connect the second load capacitor to the ground side terminal of the resistance change element,
A resistance change element programming method in which when the resistance value of the resistance change element is read, the switching transistor is turned off to separate the second load capacitor from the ground-side terminal of the resistance change element. The first load capacity is
8. The resistance change element programming method according to claim 7, wherein the resistance change element is a parasitic capacitance of a line to which the resistance change element is connected.

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