KR20120120926A - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device. In an embodiment, a liquid crystal display device includes a substrate, a plurality of pixels formed on the substrate, each pixel including a plurality of switching elements, a plurality of gate lines connected to the switching elements, and extending in a row direction; A gate driver including a circuit portion connected to the gate line and a wiring portion connected to the circuit portion, wherein the circuit portion includes a transistor, the wiring portion includes a signal line, and the transistor and the signal line comprise a connection member. It is connected through.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

The liquid crystal display device is one of the most widely used flat panel display devices, and includes two display panels having an electric field generating electrode such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween. The liquid crystal display displays an image by applying a voltage to the electric field generating electrode to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light.

The liquid crystal display device further includes a switching element connected to each pixel electrode, and a plurality of signal lines such as a gate line and a data line for controlling the switching element to apply a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode in accordance with the gate signal.

The gate driver and the data driver are formed in a chip form and mounted on the display panel. However, in recent years, in order to increase productivity while reducing the overall size of the display device, a structure for integrating the gate driver into the display panel has been developed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display that prevents static electricity from flowing into a gate driver integrated in a display panel during a manufacturing process of a liquid crystal display.

According to an aspect of the present invention, a liquid crystal display device includes a substrate, a plurality of pixels formed on the substrate, each pixel including a plurality of switching elements, and a plurality of gate lines connected to the switching elements and extending in a row direction. And a gate driver including a circuit part connected to the gate line and a wiring part connected to the circuit part, wherein the circuit part includes a transistor, the wiring part includes a signal line, and the transistor and the signal line are connecting members. Connected via

The signal line may transmit a scan start signal to the transistor.

The transistor and the signal line are made of the same material as the gate line.

The connection member may include indium tin oxide (ITO) or indium zinc oxide (IZO).

The display device may further include a passivation layer formed between the connection member, the signal line, and the transistor.

The passivation layer may have a first contact hole connecting the signal line and the connection member and a second contact hole connecting the transistor and the connection member.

The transistor may include at least one lead wire connected to the signal line through the connection member.

A liquid crystal display according to another exemplary embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, each pixel including a plurality of switching elements, a plurality of gate lines connected to the switching elements, and extending in a row direction, A gate driver including a plurality of circuit parts connected to the gate line and a wiring part connected to the circuit part, the wiring part including a signal line, the circuit part including a transistor connected to the signal line, and the transistor Includes at least two lead wires directly connected to the signal line.

The signal line may transmit a scan start signal to the transistor.

The transistor and the signal line may be made of the same material as the gate line.

According to the present invention, damage to the gate driver is minimized by preventing static electricity from flowing into the gate driver integrated in the display panel during the manufacturing process of the liquid crystal display.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a plan view of a liquid crystal panel assembly according to an embodiment of the present invention.
4 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.
5 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 4;
6 is a schematic layout view of the first and second stages of a gate driver according to an embodiment of the present invention.
FIG. 7 is an enlarged layout view of a portion of the gate driver illustrated in FIG. 6. FIG.
FIG. 8 is a cross-sectional view of the gate driver of FIG. 7 taken along the line VIII-VIII. FIG.
9A and 10A are layout views illustrating a manufacturing process of the gate driver shown in FIGS. 7 and 8, and FIGS. 9B and 10B are cut along the lines VII-b and VII-b, respectively. Shown cross section.
11 is a layout view showing a portion of a gate driver according to another embodiment of the present invention.
12 is a layout view showing a portion of a gate driver according to another embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver connected thereto. The gray voltage generator 800 connected to the 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _{n and} D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _{n and} D ₁ -D _m , which are arranged in a substantially matrix form. Include. 2, the liquid crystal display panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G _{1 to} G _n extend in a substantially row direction and are substantially parallel to each other, and the data lines D _{1 to} D _m extend in a substantially column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to a signal line and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto. The storage capacitor Cst can be omitted if necessary.

The switching element Q is a three terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line G _i and the input terminal is connected to the data line D _j And the output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200 as two terminals and the liquid crystal layer 3 between the two electrodes 191 and 270, . The pixel electrode 191 is connected to the switching element Q and the common electrode 270 is formed on the entire surface of the upper panel 200 to receive the common voltage Vcom. 2, the common electrode 270 may be provided on the lower panel 100. At this time, at least one of the two electrodes 191 and 270 may be linear or bar-shaped.

The storage capacitor Cst serving as an auxiliary capacitor of the liquid crystal capacitor Clc is formed by superimposing a separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween, A predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed by overlapping the pixel electrode 191 with the previous gate line immediately above via an insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of primary colors (space division), or each pixel PX alternately displays a basic color (time division) So that the desired color is recognized by the spatial and temporal sum of these basic colors. Examples of basic colors include red, green, and blue. 2 shows that each pixel PX has a color filter 230 indicating one of the basic colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of space division. 2, the color filter 230 may be formed on or below the pixel electrode 191 of the lower panel 100. [

At least one polarizer (not shown) for polarizing light is attached to the outer surface of the liquid crystal panel assembly 300.

Referring again to FIG. 1, the gradation voltage generator 800 generates two sets of gradation voltages (or a set of reference gradation voltages) related to the transmittance of the pixel PX. One of the two has a positive value for the common voltage (Vcom) and the other has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 and supplies a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate line G ₁ -G _n . The gate driver 400 includes a plurality of stages substantially arranged in a row as a shift register, and together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. In the same process, the liquid crystal panel assembly 300 is formed and integrated.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects the gradation voltage from the gradation voltage generator 800 and supplies it as a data signal to the data line D ₁ -D _m . However, when the gradation voltage generator 800 provides only a predetermined number of reference gradation voltages instead of providing all the voltages for all gradations, the data driver 500 divides the reference gradation voltage and supplies the gradation voltage And selects a data signal among them.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. . In addition, the driving apparatuses 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

The operation of the liquid crystal display device will now be described in detail.

The signal controller 600 receives an input control signal for controlling the display of the input image signals R, G, and B from an external graphic controller (not shown). Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes at least one clock signal for controlling the output period of the scan start signal STV indicating the start of scanning and the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines the duration of the gate on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH for notifying the start of transmission of video data to the pixel PX of one row and a load for applying a data signal to the data lines D _{1 to} D _m Signal LOAD and a data clock signal HCLK. The data control signal CONT2 is also an inverted signal which inverts the voltage polarity of the data signal with respect to the common voltage Vcom (hereinafter referred to as "the polarity of the data signal by reducing the voltage polarity of the data signal with respect to the common voltage" RVS).

The data driver 500 receives the digital video signal DAT for the pixel PX of one row and outputs the digital video signal DAT for the pixel PX in accordance with the data control signal CONT2 from the signal controller 600. [ ) To convert the digital video signal DAT into an analog data signal, and then applies the analog data signal to the corresponding data lines D ₁ -D _m .

Gate driver 400 is a signal control gate lines (G ₁ -G _n) is applied to the gate line of the gate-on voltage (Von), (G ₁ -G _n) in accordance with the gate control signal (CONT1) of from 600 The switching element Q is turned on. Then, the data signal applied to the data lines D ₁ -D _m is applied to the corresponding pixel PX through the turned-on switching element Q.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom appears as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. Such a change in polarization is caused by a change in the transmittance of light by the polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H ", which is the same as one cycle of the horizontal synchronization signal Hsync and the data enable signal DE), so that all the gate lines G ₁ -G _n On voltage Von is sequentially applied to all the pixels PX to display an image of one frame by applying a data signal to all the pixels PX.

At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled such that the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame ( "Frame inversion"). At this time, the polarity of the data signal flowing through one data line changes (for example, row inversion and dot inversion) depending on the characteristics of the inversion signal RVS in one frame, or the polarity of the data signal applied to one pixel row is different (For example, thermal inversion, dot inversion).

Next, the liquid crystal panel assembly and the gate driver formed in the liquid crystal panel assembly according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6.

3 is a plan view illustrating a liquid crystal panel assembly according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal panel assembly 300 according to an exemplary embodiment of the present invention may include a thin film transistor array panel 100, a common electrode display panel (not shown), and a liquid crystal layer (not shown) between the two display panels. ).

The liquid crystal panel assembly 300 is divided into a display area DA displaying an image and a peripheral area PA.

The substrate 110 of the display area DA has a gate line G ₁ -G _n , a data line D ₁ -D _m intersecting with the gate lines G ₁ -G _n , and a gate line G ₁ -G. _n ), a thin film transistor (not shown) connected to the data lines D ₁ -D _m , a pixel electrode 191 connected to the thin film transistor, and the like are formed.

A data driver (not shown) connected to the data lines D ₁ -D _m is mounted in the upper peripheral area PA of the display area DA.

A gate driver 400 is integrated and formed in a side peripheral area PA of the display area DA.

In the upper peripheral area PA of the display area DA, an OLB pad for inputting a control signal from the signal controller 600 or the like to the gate driver 400 is formed. The gate driver 400 and the OELB pad 50 are connected by a plurality of first connection wires 81.

The test pad part 60 adjacent to the gate driver 400 is formed in the side peripheral area PA of the display area DA. The test pad unit 60 includes a plurality of pads, and a clock signal CK or a scan start signal STV for testing the liquid crystal panel assembly or the like is input to each pad. The test pad unit 60 is connected to the OELB pad 50 through the plurality of second connection wires 82, and the test signal is input to the gate driver 400 through the OELB pad 50.

Now, the gate driver 400 of the liquid crystal panel assembly according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a block diagram of a gate driver according to an embodiment of the present invention, FIG. 5 is a circuit diagram of the j-th stage of a shift register for a gate driver according to an embodiment of the present invention, and FIG. 6 is an embodiment of the present invention. The layout of the first and second stages of the gate driver according to the example.

4 to 6, the scan start signal STV and the first and second clock signals CLK1 and CLK2 are input to the shift register 400 which is the gate driver 400. Each shift register 400 includes a plurality of stages ST1, STj-1, STj, STj + 1, and STn + 1 connected to gate lines, respectively. The plurality of stages ST1, STj-1, STj, STj + 1, and STn + 1 are connected to each other independently, and the scan start signal STV and the first and second clock signals CLK1 and CLK2 are input. .

Each of the clock signals CLK1 and CLK2 may be a gate on voltage V _on capable of driving the switching element Q of the pixel when it is high, and a gate off voltage V _off when it is low.

Each stage ST1, STj-1, STj, STj + 1, STn + 1 has a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1, CK2, and a reset terminal R. And a frame reset terminal FR, and a gate output terminal OUT1 and a carry output terminal OUT2.

In each stage, for example, the set terminal S of the j-th stage STj, the carry output of the front stage ST (j-1), that is, the front carry output Cout (j-1), is a reset terminal. The gate output of the rear stage [ST (j + 2)], that is, the rear gate output Gout (j + 1), is input to R, and the clock signals CLK1 and CLK2 are supplied to the clock terminals CK1 and CK2. The gate off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signal STV is input to the first stage of each shift register 400 instead of the front carry output. In addition, when the first clock signal CLK1 is input to the first clock terminal CK1 of the j-th stage STj and the second clock signal CLK2 is input to the second clock terminal CK2, it is adjacent to (j). The second clock signal CLK2 is provided to the first clock terminal CK1 of the -1) th and (j + 1) th stages (ST (j-1) and ST (j + 1)), and the second clock terminal ( The first clock signal CLK1 is input to CK2.

Referring to FIG. 5, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and an output unit ( 450). These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and output 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. Also, the capacitors C1-C3 may actually be the parasitic capacitance between the gate and the drain / source formed in the process.

The input section 420 includes three transistors T11, T10 and T5 connected in series to the set terminal S and the gate voltage terminal GV in order. Gates of the transistors T11 and T5 are connected to the clock terminal CK2, and gates of the transistor T10 are connected to the clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T5 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a clock terminal ( And transistor T7 connected between CK1 and contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the clock terminal CK1. And the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and at the same time connected to the clock terminal CK1 through the capacitor C1, the drain is connected to the clock terminal CK1, the source is connected to the contact J4. , Capacitor C2 is connected between contact J3 and contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs a plurality of transistors T6, T9, T13, T8, T3, and T2 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4 and the gate of the transistor T2 is connected to the reset terminal R while the drains of the two transistors T3 and T2 are connected to the contact J2.

The output unit 450 includes a pair of transistors T1 and T14 having a drain and a source connected between the clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals CLK1 and CLK2 is referred to as a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals CLK1 and CLK2 is equal to the gate off voltage V _off . This is called low voltage.

First, when the clock signal CLK2 and the front carry output Cout (j-1) (or the scan start signal STV) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T14 are turned on so that the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the clock signal CLK1 are both low voltages, the output voltage [ Gout (j) and Cout (j)] become low voltage. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal CLK1 and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2 connected to the gate are connected. ) Are all off.

When the clock signal CLK2 goes low, the transistors T11 and T5 are turned off, and at the same time, when the clock signal CLK1 goes high, the output voltage of the transistor T1 and the voltage of the contact J2 become high voltage. Becomes At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the clock signal CLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. If the resistance value of the resistance state at the time of turn-on of the two transistors T13 is set to be about 10,000 times as large as the resistance value of the resistance state when the transistor T12 is turned on, the voltage of the contact J3 becomes high . Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, whereby the transistor T3 is turned off. Keep it. At this time, the transistors T9 and T2 also maintain the turn-off state since the rear-stage gate output Gout (j + 1) is still low. Therefore, the output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistors T9 and T2 are turned on to low voltage to the contacts J1 and J2. To pass. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Therefore, the two transistors T1 and T14 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, so that the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T14 is turned off and the output terminal OUT2 is cut off from the clock signal CLK1, so that the carry output Cout (j) is performed. Becomes floating and maintains low voltage. At the same time, the output terminal OUT1 continues to output a low voltage because the transistor T1 is connected to the low voltage through the transistor T2 even when the transistor T1 is turned off.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the clock signal CLK1 and the voltage of the contact J2 is low.

Next, when the clock signal CLK1 becomes high, the transistors T12 and T7 turn on, the voltage of the contact J4 rises, turns on the transistor T3, and transfers a low voltage to the contact J2. ) Continues to emit low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the clock signal CLK1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the clock terminal CK1 is connected to the drains of the two transistors T1 and T14, and the clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the clock signal CLK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain gates, thereby turning on the transistor T1. Therefore, by transmitting the low voltage of the contact J2 to the contact J1, the gate voltage of the transistor T1 is kept at the low voltage to prevent the transistor T1 from being turned on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 has the clock signal CLK1 high and the clock signal CLK2. Is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated in the last dummy stage (not shown) and transfers the gate-off voltage V _off to the contact J1 to transfer the voltage of the contact J1 once more. Set to low voltage.

In this manner, the stage 400 is based on the front carry signal Cout (j-1) and the back gate signal Gout (j + 1) and is synchronized with the clock signals CLK1 and CLK2 to carry the carry signal Cout ( j)] and the gate signal Gout (j).

Next, the connection relationship between the gate driver and the scan start signal line according to an embodiment of the present invention will be described in detail with reference to FIGS. 7, 8, and 6 described above.

FIG. 7 is a layout view illustrating a connection relationship between the transistor T4 and the scan start signal line among the gate drivers illustrated in FIG. 6, and FIG. 8 is a cross-sectional view of FIG. 7 taken along the line VIII-VIII.

Referring to FIG. 6, the scan start signal STV is input to the first stage ST1 of the shift register 400 instead of the front carry signal. That is, the scan start signal line that transmits the scan start signal STV is connected to the gate line of the transistor T4 of the first stage ST1. Hereinafter, the scanning start signal line will be described in detail with respect to the connection relationship of the transistor T4 of the first stage ST1.

7 and 8, a lead line 126 and a scan start signal line 127 of the transistor T4 are formed on the substrate 110. The lead line 126 and the scan start signal line 127 of the transistor T4 are made of the same material as the gate lines G _i and G _i-1 formed in the display area of the substrate 110. ) And aluminum-based metals such as aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, and chromium (Cr), titanium (Ti), tantalum (Ta) and the like. However, the lead line 126 and the scan start signal line 127 of the transistor T4 may have a multilayer structure including two conductive films (not shown) having different physical properties.

In addition, the side of the lead line 126 and the scan start signal line 127 of the transistor T4 is inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the lead line 126, the scan start signal line 127, and the substrate 110 of the transistor T4.

A passivation layer 180 is formed on the gate insulating layer 140. The protective film 180 is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, or a low dielectric constant insulating material. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulators, and the surface of the passivation layer may be flat. However, the passivation layer 180 may have a double layer structure of a lower inorganic layer and an upper organic layer.

The passivation layer 180 is provided with a plurality of contact holes 186 and 187 exposing the lead line 126 and the scan start signal line 127 of the transistor T4, respectively.

The connection member 86 is formed on the passivation layer 180. The connecting member 86 is made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, or an alloy thereof.

The lead line 126 of the transistor T4 is physically and electrically connected to the scan start signal line 127 through the contact holes 186 and 187 to receive the gaze start signal STV from the scan start signal line 127.

A part of a method of manufacturing a gate driver according to an exemplary embodiment of the present invention will now be described with reference to FIGS. 9A, 9B, 10A, 10B, and FIGS. 7 and 8.

9A and 10A are layout views showing a part of a method of manufacturing a gate driver according to an exemplary embodiment of the present invention, and FIGS. 9B and 10B illustrate the V-V and V-V lines of FIGS. 9A and 10A, respectively. It is a cross-sectional view cut along.

Hereinafter, for convenience of description, portions of the gate driver 400 according to an embodiment of the present invention shown in FIGS. 7 and 8 will be described.

Referring to FIGS. 9A and 9B, after forming a metal layer on an insulating substrate 110 made of transparent glass or plastic, the metal layer is etched to scan the signal line 127, the lead lines 126 of the plurality of transistors and the transistor T4. To form.

Subsequently, as shown in FIGS. 10A and 10B, the gate insulating layer 140 made of silicon nitride (SiNx) is deposited on the lead line 126 and the start signal start signal line 127 of the transistor T4. vapor deposition, PECVD).

Thereafter, the passivation layer 180 is deposited on the gate insulating layer 140 by a plasma enhanced chemical vapor deposition (PECVD) method. Thereafter, the passivation layer 180 and the gate insulating layer 140 are etched to expose a portion of the lead line 126 and the scan start signal line 127 of the transistor T4.

Subsequently, as shown in FIGS. 7 and 8, the IZO or ITO layer is deposited on the protective film 180 by sputtering and patterned by a photo process using a photosensitive film to form a connecting member 86.

Static electricity is apt to occur during such a process. In particular, static electricity is likely to be generated during the lamination process and the etching process of the gate insulating layer 140 and the passivation layer 180, which are performed after the lead line 126 and the scan start signal line 127 of the transistor T4 are formed. When static electricity is generated, the static electricity is easily drawn into the gate driver 400 through the test pad unit 60. The transistor T4 directly connected to the scan start signal line 127 among the test pad portions 60 is liable to be damaged by the generation of static electricity. Therefore, after forming the lead line 126 and the scan start signal line 127 of the transistor T4 without being directly connected as in the present invention, a process of forming the gate insulating layer 140 and the passivation layer 180 where static electricity is mainly generated. Thereafter, when the lead line 126 and the scan start signal line 127 of the transistor T4 are connected through the connection member 86, damage of the transistor T4 due to static electricity may be prevented.

A gate driver according to another exemplary embodiment of the present invention will now be described in detail with reference to FIG. 11.

11 is a layout view illustrating a part of a gate driver according to another exemplary embodiment of the present invention.

Referring to FIG. 11, a lead line 128 and a scan start signal line 127 of the transistor T4 are formed on a substrate (not shown). A gate insulating film (not shown) is formed on the lead line 128, the scan start signal line 127, and the substrate of the transistor T4. A protective film (not shown) is formed on the gate insulating film.

Unlike the gate driver shown in FIGS. 7 and 8, the gate driver of FIG. 11 is directly connected to the scan start signal line 127 and the lead line 128 of the transistor T4. Lead wire 128 of transistor T4 includes a plurality of branches 128a, 128b, and 128c, and each branch 128a, 128b, and 128c is connected to each other through a plurality of connection portions 128d and 128e. When static electricity is generated and introduced into the transistor T4 through the scan start signal line 127, the static electricity is dispersed and introduced through the plurality of branches 128a, 128b, and 128c. Therefore, even when the scan start signal line 127 and the lead wire 128 of the transistor T4 are directly connected, damage to the transistor T4 due to static electricity generation is reduced.

A gate driver according to another exemplary embodiment of the present invention will now be described in detail with reference to FIG. 12.

12 is a layout view illustrating a gate driver according to another exemplary embodiment of the present invention.

Referring to FIG. 12, a lead line 126 and a scan start signal line 127 of the transistor T4 are formed on a substrate (not shown). A gate insulating film (not shown) is formed on the lead line 128, the scan start signal line 127, and the substrate of the transistor T4. A protective film (not shown) is formed on the gate insulating film.

Similar to the gate driver shown in FIG. 11, the gate driver shown in FIG. 12 also includes a plurality of branches 126a, 126b, and 126c of the lead line 126 of the transistor T4. However, unlike the gate driver of FIG. 11, the plurality of branches 126a, 126b, and 126c are not directly connected to the scan start signal line 127. Similar to the gate driver shown in FIGS. 7 and 8, the gate driver of FIG. 12 includes a plurality of contact holes 186a, 186b, and 186c and respective branches 126a, 126b, and 126c and a gaze start signal line 127. It is connected to each other via the some connection member 187a, 187b, 187c. Each branch 126a, 126b, 126c is connected to each other by a plurality of connecting portions 126d, 126e. Therefore, the static electricity can be prevented from entering the transistor T4, and even if the static electricity is dispersed, the damage can be minimized.

3: liquid crystal layer 50: test pad
60: OLB pad 70: cutting line
86, 86a, 86b, 86c: connecting member
100: lower display panel 110: substrate
127: scan start signal line
126a, 126b, 126c, 128a, 128b, 128c: incoming line
126d, 126e, 128d, 128e: connecting line
186, 186a, 186b, 186c, 187, 187a, 187b, 187c: contact hole
191: pixel electrode
200: upper display panel 230: color filter
270: common electrode 300: liquid crystal panel assembly
400: gate driver 500: data driver
600: signal controller 800: gray voltage generator

Claims (3)

Board,
A plurality of pixels formed on the substrate and each comprising a plurality of switching elements,
A plurality of gate lines connected to the switching element and extending in a row direction,
A gate driver including a plurality of circuit parts connected to the gate lines, and a wiring part connected to the circuit parts, respectively
Including,
The wiring portion includes a signal line, the circuit portion includes a transistor connected to the signal line,
The transistor includes at least two lead wires directly connected to the signal line.
Liquid crystal display. In claim 1,
And the signal line transmits a scan start signal to the transistor. In claim 1,
And the transistor and the signal line are made of the same material as the gate line.

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