KR101090251B1 - Thin film transistor array panel and display device including same - Google Patents

Abstract

The present invention relates to a thin film transistor array panel and a display device including the same.

A substrate on which a gate line, a data line, a pixel electrode and a thin film transistor are formed,

A gate driver formed on the substrate, the gate driver including a first to third signal line receiving a signal from the outside, a circuit unit configured to output a gate signal to the gate line in response to a signal from the first to third signal line; Intersecting at least one of the first to third signal lines, and including first to third connection lines for transmitting a signal from the first to third signal lines to the gate driver, wherein the first to third signal lines A plurality of sub-signal lines connected to each other, at least one of the sub-signal lines is short-circuited with one of the first to third connecting lines, and the at least one sub-signal line is disconnected at both sides of the short-circuit point.

In this manner, a thin film transistor array panel and a display device which can be easily repaired by disconnecting both of the signal lines when the signal lines and the connection lines are shorted due to the inflow of static electricity from the outside can be provided.

Display, Static electricity, Short circuit, Gate driver, Integrated, Signal line, Connection line

Description

Thin film transistor array panel and display device including the same {THIN FILM TRANSISTOR ARRAY PANEL AND DISPLAY APPARATUS INCLUDING THE SAME}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is an example of a block diagram of a shift register used as the gate driver shown in FIG.

4 is an example of a circuit diagram of one stage of the shift register shown in FIG.

5 is a schematic layout view of a gate driver according to an exemplary embodiment of the present invention.

FIG. 6 is an example of the layout of the wiring portion of the gate driver shown in FIG. 5.

FIG. 7 is a view showing an example of a repaired state in the layout shown in FIG. 6.

FIG. 8 is a cross-sectional view of the wiring unit illustrated in FIG. 6 taken along the line VIII-VIII ′.

FIG. 9 is an example of a layout view of a part of a circuit portion of the gate driver shown in FIG. 5.

10 is a cross-sectional view of the wiring unit illustrated in FIG. 9 taken along the line X-X '.                 

11 is a layout view of pixels of the display area DA.

12 is a cross-sectional view of the pixel illustrated in FIG. 11 taken along the line XII-XII ′.

The present invention relates to a thin film transistor array panel and a display device including the same.

In general, a display device includes a display panel unit including a thin film transistor array panel including a gate line, a data line, a pixel electrode, and a thin film transistor and a common electrode display panel, a gate driver for outputting a gate signal to the gate line, and a data signal to the data line. It consists of a data driver for outputting.

The gate driver and the data driver have a chip shape and are mounted on the display panel. However, in recent years, in order to increase productivity while reducing the overall size of the display device, a structure in which the gate driver is incorporated in the display panel has been developed.

In a structure in which the gate driver is incorporated in the display panel, wirings for transmitting signals necessary for the operation of the gate driver, for example, a gate-off voltage, a clock signal, and an initialization signal, are formed on one side together with the gate driver. . In addition, a connection line for transmitting these signals to the gate driver is formed to cross these signal lines.

 In this case, when the gate driver and the signal line are integrated on one side, when the phenomenon that the signal line and the connection line are shorted due to the inflow of static electricity flowing from the outside occurs, the gate driver is seriously damaged. However, in the structure in which the gate driver is integrated, repair to recover such damage is impossible, resulting in a very fatal defect as a whole product.

Accordingly, it is an object of the present invention to provide a thin film transistor array panel that is easy to repair. In addition, to provide a display device including the thin film transistor array panel.

A thin film transistor array panel according to an aspect of the present invention may include a substrate on which a gate line, a data line, a pixel electrode, and a thin film transistor are formed, and first to third signal lines formed on the substrate and receiving signals from the outside. A gate driver including a circuit unit configured to output a gate signal to the gate line in response to a signal from the first to third signal lines, and at least one of the first to third signal lines, the first to third signal lines A first to third connection lines for transmitting a signal from the gate driver to the gate driver, wherein the first to third signal lines each include a plurality of sub signal lines connected to each other, and at least one of the sub signal lines Short-circuit with one of the first to third connecting lines, and the at least one sub-signal line is disconnected at both sides of the short-circuit point. There.

In this case, the first to third signal lines may be formed of the same layer as the gate line, or the first to third connection lines may be formed of the same layer as the data line.

On the other hand, the circuit portion includes a shift register consisting of a plurality of stages are cascaded and in turn generates an output signal, wherein the first to third signal lines are first and second clocks of a phase different from a power supply voltage to the shift register; Can carry a signal. Here, it is preferable that all of the first to third signal lines have openings.

The electronic device may further include a fourth signal line that transmits an initialization signal to the shift register, and the first to fourth signal lines may be sequentially disposed far from and close to the shift register.

The first to third connection lines and the first to third signal lines may be connected through a connection auxiliary member, and the connection auxiliary member may be transparent and may be connected to the first to third connection lines and the first to third signal lines. It may be connected through a plurality of contact holes.

The circuit unit may include a plurality of transistors, and at least one of the transistors may include a plurality of sub transistors spaced apart from each other.

On the other hand, the thin film transistor array panel according to another aspect of the present invention, the gate line, the data line, the pixel electrode and the substrate on which the thin film transistor is formed, the first to third signal lines formed on the substrate, and receives a signal from the outside And a gate driver including a circuit unit configured to output a gate signal to the gate line in response to a signal from the first to third signal lines, and to cross at least one of the first to third signal lines. First to third connection lines for transmitting signals from three signal lines to the gate driver, wherein the first to third connection lines respectively include a plurality of sub connection lines connected to each other, and at least one of the sub connection lines Shorted to one of the first to third signal lines, and the at least one sub connection line It is disconnected.

In this case, the first to third connection lines may be formed of the same layer as the data line, or the first to third signal lines may be formed of the same layer as the gate line.

On the other hand, the circuit portion includes a shift register consisting of a plurality of stages are cascaded and in turn generates an output signal, wherein the first to third signal lines are first and second clocks of a phase different from a power supply voltage to the shift register; Can carry signal KF.

In addition, it is preferable that all of the first to third connection lines have openings.

The thin film transistor array panel may further include a fourth signal line that transmits an initialization signal to the shift register, and the first to fourth signal lines may be sequentially disposed from a far position to a close position to the shift register.

The first to third connection lines and the first to third signal lines may be connected through a connection auxiliary member, and the connection auxiliary member may be transparent and may be connected to the first to third connection lines and the first to third signal lines. It may be connected through a plurality of contact holes.

The circuit unit may include a plurality of transistors, and at least one of the transistors may include a plurality of sub transistors spaced apart from each other.

A display device according to an aspect of the present invention comprises a first substrate having a plurality of gate lines and a plurality of data lines, a second substrate facing the first substrate, and displaying an image in response to a data signal and a gate signal. A display panel unit; a data driver for outputting the data signal to the plurality of data lines; first to third signal lines provided on the first substrate and receiving a plurality of signals from the outside; A gate driver configured to include a circuit unit configured to output a gate signal to the plurality of gate lines, and an intersecting at least one of the first to third signal lines, and transmitting a signal from the first to third signal lines to the gate driver. Including a first to third connecting line, each of the first to third connecting line includes a plurality of secondary connecting line connected to each other , And at least one of said connecting line section is short-circuited with one of the first to third signal line, it said at least one connector portion is disconnected from both of the short-circuit point.

According to another aspect of the present invention, a display device includes a first substrate having a plurality of gate lines and a plurality of data lines, a second substrate facing the first substrate, and displays an image in response to a data signal and a gate signal. A display panel unit; a data driver for outputting the data signals to the plurality of data lines; and first to third signal lines provided on the first substrate and receiving a plurality of signals from outside; A gate driver including a circuit unit configured to output the gate signal to the plurality of gate lines, and at least one of the first to third signal lines, and transferring a signal from the first to third signal lines to the gate driver. First to third connection lines, and each of the first to third signal lines includes a plurality of sub signal lines connected to each other. It said, and at least one of the sub-signal line is short-circuited with one of the first to third connection line, wherein the at least one sub signal line is disconnected from both of the short-circuit point.

In addition, a repairing method of a display device according to an aspect of the present invention may include a wiring part including a plurality of signal lines on a first substrate, a plurality of connection parts for transmitting a signal from the wiring part, and a signal transmitted from the connection part. Forming a gate driving circuit including a circuit portion for generating a gate signal, and disconnecting both of the wiring portions about the short circuit point when one of the wiring portions and any one of the connection portions is shorted; Steps.

According to another aspect of the present invention, a repairing method of a display device includes a wiring part including a plurality of signal lines on a first substrate, a plurality of connection parts for transmitting a signal from the wiring part, and a gate signal according to a signal transmitted from the connection part. Forming a gate driving circuit including a circuit unit for generating a circuit, and disconnecting both ends of the connection unit based on the shorting point when one of the wiring units and any one of the connection units is short-circuited. Include.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display device according to an embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the display device according to an exemplary embodiment of the present invention includes a display panel 300, a gate driver 400 connected thereto, a data driver 500, and a gray voltage generator connected to the data driver 500. 800, and a signal controller 600 for controlling them.

The display panel unit 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and a plurality of pixels arranged in a substantially matrix form when viewed in an equivalent circuit.

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data line D for transmitting a data signal. ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to the display signal lines G ₁ -G _n , D ₁ -D _m , and a pixel circuit PX connected thereto.

The switching element Q is a three-terminal element whose control terminal and input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively, and the output terminal is the pixel circuit PX. Is connected to. In addition, the switching element Q is preferably a thin film transistor, and particularly preferably comprises amorphous silicon.

In the case of a liquid crystal display device which is a representative example of a flat panel display device, as shown in FIG. 2, the display panel unit 300 includes a lower panel 100, an upper panel 200, and a liquid crystal layer 3 therebetween, The signal lines G ₁ -G _n , D ₁ -D _m and the switching element Q are provided on the lower panel 100. The pixel circuit PX of the liquid crystal display includes a liquid crystal capacitor C _LC and a storage capacitor C _ST connected in parallel to the switching element Q. The holding capacitor C _ST can be omitted as necessary.

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel should be able to display color, which is provided with a color filter 230 of three primary colors, for example, red, green, or blue, in a region corresponding to the pixel electrode 190. It is possible by doing. In FIG. 2, the color filter 230 is formed on the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

Polarizers (not shown) for polarizing light are attached to outer surfaces of at least one of the two display panels 100 and 200 of the display panel unit 300 of the liquid crystal display device.

Referring back to FIG. 1, the gray voltage generator 800 generates one or two gray voltages related to the luminance of the pixel. If there are two sets, one of the sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to turn off the gate-on voltage V _on and the switching element Q, which can turn _{on the} switching element Q. A gate signal composed of a combination of gate off voltages V _off may be applied to the gate lines G ₁ -G _n . The gate driver 400 is formed in the same process as the switching element Q of the pixel and is integrated in the display panel 300.

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a display device will now be described in more detail.

The signal controller 600 may control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal and the input image signals R, G, and B, and generates the image signals R, G, and B. After proper processing according to the operating conditions of the display panel 300, the gate control signal CONT1 is sent to the gate driver 400, and the image signal DAT processed with the data control signal CONT2 is transferred to the data driver 500. Export.

The gate control signal (CONT1) is the gate-on scanning start instructing the start of output of a voltage (V _on) signal (STV), a gate-on voltage (V _on) on-voltage gate clock signal (CPV), and a gate for controlling the output timing of the An output enable signal OE or the like that defines the duration of V _on .

The data control signal CONT2 is a load signal LOAD and a data clock signal for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data DAT and the data lines D ₁ -D _m . (HCLK). In the case of the liquid crystal display or the like shown in FIG. 2, the polarity of the data voltage with respect to the common voltage V _com (hereinafter referred to as "polarization of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage") is inverted. The inversion signal RVS may also be included.

The data driver 500 sequentially receives the image data DAT corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and among the gray voltages from the gray voltage generator 800. By selecting the gray scale voltage corresponding to each image data DAT, the image data DAT is converted into a corresponding data voltage and applied to the data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to. The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In the case of the liquid crystal display shown in FIG. 2, the difference between the data voltage applied to the pixel and the common voltage V _com is represented as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is represented by a change in transmittance of light by polarizers attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. In the case of the liquid crystal display shown in FIG. 2, inverting is applied to the data driver 500 such that the next frame starts after one frame ends, and the polarity of the data voltage applied to each pixel is opposite to that of the previous frame. The state of the signal RVS is controlled ("frame inversion"). In this case, the polarity of the data voltage flowing through one data line may be changed (“column inversion”) or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( "Dot reversal")

Next, the thin film transistor array panel and the display device according to the exemplary embodiment will be described in more detail with reference to FIGS. 3 to 12.

FIG. 3 is an example of a block diagram showing the gate driver shown in FIG. 1, and FIG. 4 is an example of a circuit diagram of one stage of the gate driver shown in FIG.

Referring to FIGS. 3 and 4, the gate driver 400 is connected to each other and includes a plurality of stages ST ₁ to ST _{n + 1} that sequentially output gate signals, and includes a gate off voltage V _off . The first and second clock signals CKV and CKVB and the initialization signal INT are input. All stages ST ₁ to ST _{n + 1} except for the last stage ST _{n + 1 are} connected to the gate lines GL1 to GLn one-to-one.

Each stage ST ₁ to ST _{n + 1} includes a first clock terminal CK1, a second clock terminal CK2, a set terminal S, a reset terminal R, a power supply voltage terminal GV, and a frame rear. It has a set terminal FR, and a gate output terminal OUT1 and a carry output terminal OUT2.

Each stage, for example, the j-th stage (ST _j) the set terminal (S), the carry output of the front end stage (ST _j-1), i.e. shear carry output [Cout (j-1)] is a reset terminal ( The gate output of the rear stage ST _{j + 1} , that is, the rear gate output Gout (j + 1), is input to R, and the clock signals CKV and CKVB are provided to the first and second clock terminals CK1 and CK2. ) Is input, the gate off voltage V _off is input to the gate voltage terminal GV, and the initialization signal INT is input to the frame reset terminal FR. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j). Finally stay not carry output [Cout (n + 1)] of the _{(n + 1} ST) is provided at the respective stages (ST1 ~ ST _n) as a reset signal (INT).

However, the scan start signal STV is input to the first stage ST ₁ of the shift register 400 instead of the front carry output, and the scan start signal STV is output to the last stage ST _{n + 1} instead of the rear gate output. Is entered. In addition, when the first clock signal CKV is input to the first clock terminal CK1 of the j th stage ST _j and the second clock signal CKVB is input to the second clock terminal CK2, The second clock signal CKVB is provided to the first clock terminal CK1 of the j-1) th and (j + 1) th stages ST _j-1 and ST _{j + 1} , and is provided to the second clock terminal CK2. The first clock signal CKV is input.

The first and second clock signals CKV and CKVB are equal to the gate-on voltage V _on when the voltage level is high so as to drive the transistor Tr of the pixel, and gate-off voltage V _{off when the} voltage is low. Is preferred. The first and second clock signals CKV and CKVB may have a duty ratio of 50% and a phase difference of 180 °.

Referring to FIG. 4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j th stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and an output unit ( 450). These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the second clock terminal CK2, and gates of the transistor T5 are connected to the first clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T11 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the first clock terminal CK1 and the contact J3, and a first transistor T12. And a transistor T7 connected between the one clock terminal CK1 and the contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the first clock terminal CK1. Connected and the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and is connected to the first clock terminal CK1 through the capacitor C1, the drain is connected to the first clock terminal CK1, and the source is the contact J4. The capacitor C2 is connected between the contact J3 and the contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs the transistors T9, T13, T8, T3, T2, and the like through the drain to the contacts J1, J2, J3, and J4. T6). The gate of the transistor T9 is connected to the reset terminal R, the drain is connected to the contact J1, the gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drain is respectively a contact. It is connected to (J3, J4). The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2. The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, and the source is connected to the gate off voltage terminal GV.

The output unit 450 includes a pair of transistors T1 and T15 having a drain and a source connected between the first clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of the transistor T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of description, a voltage corresponding to a high level of the first and second clock signals CKV and CKVB is called a high voltage, and a magnitude of a voltage corresponding to a low level of the first and second clock signals CKV and CKVB. Is equal to the gate off voltage (V _off ) and is referred to as low voltage.

First, when the second clock signal CKVB and the front carry output Cout (j-1) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T15 are turned on so that the first clock signal CKV is output to the output terminals OUT1 and OUT2. At this time, the voltage of the contact J2 and the first clock signal CKV are low voltage. , The output voltages Gout (j) and Cout (j) become low voltages. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the first clock signal CKV and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, and T8 connected to the gate are connected. , T2) are all off.

Subsequently, when the second clock signal CKVB becomes low, the transistors T11 and T5 are turned off. At the same time, when the first clock signal CKV becomes high, the output voltage of the transistor T1 and the contact point J2 of the transistor T1 are turned off. The voltage becomes a high voltage. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the first clock signal CKV and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the two transistors T13 in the resistance state at the turn-on is set very large compared to the resistance value of the resistance state in the turn-on state of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be substantially the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, and thus the transistor T3 turns off. Keep it. At this time, since the rear gate output Gout (j + 1) is still low, the transistors T9 and T2 also remain turned off. Accordingly, the output terminals OUT1 and OUT2 are connected only to the first clock signal CKV and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the second clock signal CKVB go high and the first clock signal CKV goes low, the transistors T9 and T2 are turned on so that the contact J1, It transmits low voltage to J2). At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Accordingly, the two transistors T1 and T15 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, whereby the output terminals OUT1 and OUT2 become the first clock signal CKV. It is connected to and emits low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T15 is turned off and the output terminal OUT2 is cut off from the first clock signal CKV. (j)] becomes floating and maintains low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the first clock signal CKV and the voltage of the contact J2 is low.

Next, when the first clock signal CKV becomes high, the transistors T12 and T7 are turned on, the voltage of the contact J4 is increased, the transistor T3 is turned on, and a low voltage is transmitted to the contact J2. OUT1 continues to emit a low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the first clock signal CKV and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the first clock terminal CK1 is connected to the drains of the two transistors T1 and T15 so that the first clock signal CKV is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors. As a result, the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the first clock signal CKV becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain regions, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 is the first clock signal CKV and the second voltage is high. When the clock signal CKVB is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

Meanwhile, the transistor T6 receives the initialization signal INT, which is the carry output Cout (n + 1) of the last dummy stage ST _{n + 1} , and transfers the gate off voltage V _off to the contact J1. To set the voltage at the contact J1 again to a lower voltage.

In this manner, the stage ST _j is based on the front carry signal Cout (j-1) and the rear gate signal Gout (j + 1) and synchronized with the first and second clock signals CKV and CKVB. To generate a carry signal Cout (j) and a gate signal Gout (j).

Next, an arrangement on the thin film transistor array panel 100 of the gate driver 400 illustrated in FIG. 4 will be described in detail with reference to FIGS. 5 to 7 and 9.

FIG. 5 is a schematic layout view of a gate driver according to an exemplary embodiment of the present invention, FIG. 6 is a layout view of a wiring part of the gate driver shown in FIG. 5, and FIG. 7 is a case in which a signal line is shorted in the layout view shown in FIG. 6. It is a figure which shows the repaired example, and FIG. 9 is a layout view of a part of circuit part of the gate drive part shown in FIG.

Referring to FIG. 5, the gate driver 400 according to this embodiment described earlier stage various input to the _{(ST 1 ~ ST n + 1} ) circuit (CS), and these stages _{(ST 1 ~ ST n + 1} ) consisting of The wiring unit SL may be configured to transmit the signals V _off , CKV, CKVB, and INT.

The wiring part SL may include the gate-off voltage line SL1 for transmitting the gate-off voltage V _off , and the first and second clock signal lines SL2 and SL3 for transmitting the first and second clock signals CKV and CKVB, respectively. ) And an initialization signal line SL4 for transmitting the initialization signal INT. Each signal line SL1 to SL4 extends mainly in the vertical direction, and is arranged in order from the left in the order of the gate-off voltage line SL1, the clock signal lines SL2 and SL3, and the initialization signal line SL4 to the shift register 400. Getting closer. In addition, these signal lines SL1 to SL4 have connecting lines extending horizontally toward the stages ST ₁ to ST _{n + 1} , and the gate-off voltage line SL1 and the initialization signal line SL4 are connected to one stage ST ₁ to ST. _{Although n + 1 is} connected one by one, the first and second clock signal lines SL2 and SL3 are positioned near the boundary of the stages ST ₁ to ST _{n + 1} and alternately are connected one by one.

In the circuit section CS, the arrangement of the transistors T1 to T13 and T15 in each of the stages ST ₁ to ST _{n + 1} , for example, the (j-1) th stage, shows that the front carry is located in the upper left side near the front stage. A transistor T4 to which the signal Cout (j-1) is input is disposed, and a transistor which receives the first clock signal CKV along a connection line of the first clock signal line SL2 extending in the horizontal direction at the top ( T1 and T15 are disposed, and transistors T7, T10, and T12 that receive the first clock signal CKV are also disposed below the transistor T15. In addition, the transistors T11 and T5 connected to the connection line of the second clock signal line SL3 rising from the bottom to receive the second clock signal CKVB are disposed on the lower left side, and the initialization signal line SL4 coming from the left side. The transistor T6 connected to the connection line of the signal receiving the initialization signal INT is disposed on the leftmost side. In addition, the transistors T2, T3, T8, T9, and T13 that receive the gate-off voltage V _off are disposed along the connection line of the gate-off voltage line SL1 extending in the horizontal direction.

In the j-th stage ST _j adjacent thereto, the first clock signal line SL2 and the first clock signal CKV are converted into the second clock signal line SL3 and the second clock signal CKVB, and vice versa. Except that the signal line SL3 and the second clock signal CKVB are replaced with the first clock signal line SL2 and the first clock signal CKV, the arrangement of each transistor is the (j-1) th stage (ST _{j). -1} )

In this case, the wiring part SL is located in the seal line area SA, a part of the circuit part CS is also located in the seal line area SA, and another part of the circuit part CS is a process margin area of the seal line area SA. It is located at (SA '). The width of the process margin area SA ′ is about 0.3 mm, which is the maximum error range that can occur when applying the sealant used to bond the thin film transistor array panel 100 and the upper substrate 200 to the seal line area SA. It means.

In this case, when light is irradiated from the rear surface of the thin film transistor array panel 100 when curing the sealant, signal lines and transistors positioned in the seal line area SA and the seal line process margin area SA ′ may pass the light well. Can be.

Referring to FIG. 6, each of the signal lines SL1 to SL4 includes signal lines 122a to 122d in the form of a ladder or a net, and each of the signal lines 122a to 122b each has a pair of one or more lengths extending vertically. It consists of a part and a plurality of horizontal parts connecting them and has an opening surrounded by them. In terms of circuits, the signal lines 122a to 122d are connected in parallel. In this case, when static electricity flows from the outside and one of the signal lines and the connection line is shorted, it can be easily repaired as shown in FIG. 7.

Referring to FIG. 7, for example, when one of the vertical lines of the first clock line 122b and the horizontal line of the gate-off voltage line 122a are short-circuited, the points indicated by the X marks on the top and the bottom of the short-circuit point represented by triangles are cut off, respectively. do. Then, the horizontal line of the gate-off voltage line 122a is connected only to the stage STj to transfer the gate-off voltage V _off .

On the other hand, such a structure is not only a structure that can facilitate repair when a short circuit due to static electricity, but also has a structure suitable for curing the sealant by the back exposure.                     

Referring to FIG. 9, a large thin film transistor positioned in the seal line area SA and the seal line process margin area SA ′, for example, the transistors T4 and T15 in FIG. It is divided into (T41 ~ T45) and there is a sufficient gap between them to allow light to pass between the small transistors (T41 ~ T45). The width and spacing of the small thin film transistors T41 to T45 are also determined to allow light to diffract and transmit, and are preferably about 100 μm or less.

Next, the structure of the thin film transistor array panel including the gate driver 400 will be described in detail with reference to FIGS. 8 and 10 to 12, and FIGS. 6 and 9.

FIG. 8 is a cross-sectional view of the wiring unit illustrated in FIG. 6 taken along the line VIII-VIII ', FIG. 10 is a cross-sectional view of the wiring unit illustrated in FIG. 9 taken along the line X-X ′, and FIG. It is a layout view of the pixel of area | region DA, and FIG. 12 is sectional drawing which cut | disconnected and showed the pixel shown in FIG. 11 along line XII-XII '.

A plurality of gate lines 121 and a plurality of driving signal lines 122, 122a through 122d are formed on the insulating substrate 110.

Referring to FIG. 11, the gate line 121 transmits a gate signal, mainly extends in a horizontal direction, and extends to be connected to the gate driver 400. A portion of each gate line 121 forms a plurality of gate electrodes 124, and the other portion protrudes downward to form a plurality of projections 127.

Referring to FIG. 6, the driving signal lines 122a to 122d transmit the gate-off voltage V _off , the first and second clock signals CKV and CKVB, and the initialization signal INT, respectively, and mainly extend in the vertical direction. . The driving signal lines 122a to 122d have a ladder shape, and include a pair of one or more vertical portions extending vertically, and a plurality of horizontal portions connecting them, and openings surrounded by them. The width and spacing of the longitudinal sections are determined to the extent that light can be diffracted and transmitted and preferably about 20 to 30 μm, preferably about 25 μm. The total line width of each signal line 122a to 122d is appropriately determined in consideration of the increase in resistance caused by the opening. It is preferable to have such a structure in the case where the light is not diffracted because the line width when no opening is formed is about 100 µm or more. On the other hand, the initialization signal line 122d has a plurality of branches extending in the horizontal direction toward each stage.

Referring to FIG. 9, the driving signal line 122 transmits a signal in the gate driver and is expanded to serve as a control electrode of the thin film transistor of the gate driver.

The gate line 121 and the driving signal lines 122 and 122a to 122d may be formed of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper (Cu), copper alloys, and the like. It consists of copper-based metals, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), tantalum (Ta) and titanium (Ti). However, the gate line 121 may include two layers having different physical properties, that is, a lower layer (not shown) and an upper layer (not shown) thereon. The upper layer may have a low resistivity metal such as aluminum (Al) or an aluminum alloy, such as aluminum (Ag) or silver alloy, so as to reduce signal delay or voltage drop of the gate line 121. It may be made of a copper-based metal such as a metal of the series, copper (Cu) or a copper alloy. In contrast, the underlayer is a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti) Or the like. The chromium lower film, the aluminum-neodymium (Nd) alloy upper film, the molybdenum upper film and the aluminum-neodymium (Nd) alloy lower film are good examples.

Side surfaces of the gate line 121 and the driving signal lines 122, 122a through 122d are inclined with respect to the surface of the substrate 110, and the inclination angle is in the range of about 30 to 80 degrees.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate line 121 and the driving signal lines 122 and 122a to 122d.

A plurality of linear semiconductors 151 and island semiconductors 152 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of protrusions 154 extend toward the gate electrode 124, and the width of the linear semiconductor 151 is increased near the point where the linear semiconductor 151 meets the gate line 121. The large area of 121 is covered. The island type semiconductor 152 is positioned on the control electrode of the gate driver as shown in FIG. 9, or is positioned on a part of the driving signal lines 122, 122a to 122d as shown in FIGS. 6 and 9, and the driving signal line 122. , 122a through 122d).

On top of the semiconductors 151, 152 a plurality of linear and island ohmic contacts 161, 162, 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities. ) Is formed. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151. The island resistive contact member 162 is positioned over the island semiconductor 152.

Side surfaces of the semiconductors 151 and 152 and the ohmic contacts 161, 162 and 165 are also inclined and have an inclination angle of 30 to 80 degrees.

A plurality of data lines 171, a plurality of output electrodes 175, and a plurality of storage capacitor conductors are formed on the ohmic contacts 161, 162, and 165 and the gate insulating layer 140. 177 and a plurality of connection signal lines 172, 172a to 172c.

Referring to FIG. 11, the data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the output electrode 175 form the input electrode 173. The pair of input electrode 173 and the output electrode 175 are separated from each other and positioned opposite to the control electrode 124.

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.                     

Referring to FIG. 6, the connection signal line 172a is positioned between the gate-off voltage line 122a and the first clock signal line 122b and mainly extends in a horizontal direction toward each stage from a stem and a stem extending in a vertical direction. Have Each of the connection signal lines 172b and 172c is disposed between the first clock signal line 122b and the second clock signal line 122c and is connected to a vertical portion extending mainly in the vertical direction and at its ends and extending in the horizontal direction toward each stage. It includes the horizontal portion of.

Referring to FIG. 9, the connection signal line 172 transmits a signal in the gate driver, and portions disposed on the island semiconductor 152 and the island resistive contact member 162 serve as input and output electrodes of the thin film transistor. Portions on the thin film transistor have a pod shape to increase the driving current of the transistor.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are made of a refractory metal such as molybdenum-based metal, chromium, tantalum, or titanium. It may have a multilayer film structure including a lower film having good contact characteristics. The end portion 179 of each data line 171 is extended in width for connection with another layer or an external device.

The side of the data line 171, the output electrode 175, the connection signal lines 172, 172a to 172c, and the conductor 177 for the storage capacitor are also inclined with respect to the surface of the substrate 110, and the inclination angle thereof is about 30 degrees. -80 ° range.

The ohmic contacts 161, 162, and 165 exist only between the semiconductors 151 and 152 below and the data line 171, the connection signal line 172, and the output electrode 175 thereon, and lower the contact resistance. Play a role. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Although the width of is smaller than the width of the data line 171, as described above, the width becomes larger at the portion where the gate line 121 meets, thereby preventing disconnection of the data line 171. The island type semiconductor 152 is also positioned at a portion that intersects the driving signal lines 122, 122a through 122d and the connection signal lines 172, 172a through 172c to prevent disconnection of the connection signal lines 172, 172a through 172c.

The planarization characteristics are excellent and photosensitivity is formed on the data line 171, the output electrode 175, the connection signal lines 172, 172a to 172c, and the conductive capacitor 177 for the storage capacitor and the exposed semiconductor 151. Organic material having a low dielectric constant insulating material having a dielectric constant of 4.0 or less, such as a-Si: C: O, a-Si: O: F, which is formed by plasma enhanced chemical vapor deposition (PECVD), or an inorganic material. A passivation layer 180 made of silicon nitride is formed. Alternatively, the passivation layer 180 may be formed of a double layer of organic material and silicon nitride.

The passivation layer 180 has a plurality of contacts exposing the end portion 179 of the data line 171, the output electrode 175, the conductor 177 for the storage capacitor, and the end portions of the connection signal lines 172, 172a ˜ 172c, respectively. Contact holes 182, 185, 187, and 188 are formed, and a plurality of contact holes 189 are formed to expose the driving signal lines 122, 122a through 122d together with the gate insulating layer 140.

A plurality of pixel electrodes 190, a plurality of contact assistants 82, and a connection assistant 88 formed of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the output electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive a data voltage from the output electrode 175 and to receive the conductor. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage is applied, thereby creating a liquid crystal layer 3 between the two electrodes 190 and 270. Rearrange the liquid crystal molecules.

In addition, as described above, the pixel electrode 190 and the common electrode 270 form a liquid crystal capacitor to maintain an applied voltage even after the thin film transistor is turned off, and another capacitor connected in parallel with the liquid crystal capacitor to enhance the voltage holding capability. This is called the "storage electrode". The storage capacitor is formed by the superposition of the pixel electrode 190 and the neighboring gate line 121 (which is called a “previous gate line”), and the like. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer. Alternatively, the storage capacitor can be made by overlapping the storage electrode and the pixel electrode 190 provided separately.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.                     

The contact auxiliary member 82 is connected to the end portion 179 of the data line through the contact hole 182. The contact assisting member 82 is not essential to serve to protect adhesiveness between the end portion 179 of the data line 171 and an external device and to protect them, and application thereof is optional.

The connection auxiliary member 88 is connected to the driving signal lines 122a to 122c and the connection signal lines 172a to 172c through the contact holes 188 and 189 to receive various signals from the driving signal lines 122a to 122c to receive the connection signal lines ( 172a through 172c). The connection auxiliary member 88 has a large area and is connected to one signal line through several contact holes. The reason why the connecting auxiliary member 88 is left large without dividing is because the connecting auxiliary member 88 is transparent and allows light to pass. This is because, if a plurality of contact holes are made and connected, the possibility of disconnection of the connection auxiliary member 88 is reduced by that much.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistant 82 may be made of a material different from the pixel electrode 190, in particular, ITO or IZO.

Unlike the above-described example, the driving signal lines 122 and 122a to 122d may be the same layer as the data line 171, and the connection signal lines 172 and 172a to 172c may be the same layer as the gate line 121. You can make them in several ways.

In addition, in the display device according to the exemplary embodiment, a plurality of driving signal lines SL1 to SL4 are formed and one connecting line connected to the stage is formed. However, one driving signal line SL1 to SL4 is formed. It is possible to have a plurality of connecting lines. Furthermore, the laser irradiation operation at the time of short circuiting may be facilitated by making the signal lines constituting the driving signal lines SL1 to SL4 different from each other.

On the other hand, an opening is provided in each of the driving signal lines SL1 to SL4 so that the light provided from the rear surface of the thin film transistor array panel 100 penetrates the opening to easily reach the photocurable sealant so that the sealant can be stably cured. do.

According to such a display device, by forming a plurality of driving signal lines or connecting lines, it can be easily repaired when shorted due to the inflow of static electricity. Therefore, the yield can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (26)

A substrate on which a gate line, a data line, a pixel electrode and a thin film transistor are formed, First to third signal lines formed on the substrate and receiving signals from the outside; A gate driver including a circuit unit configured to output a gate signal to the gate line in response to a signal from the first to third signal lines; First to third connection lines that cross at least one of the first to third signal lines, and transfer signals from the first to third signal lines to the gate driver; Including, The first to third signal lines each include a plurality of sub signal lines connected to each other. At least one of the sub-signal lines is short-circuited with one of the first to third connecting lines, and the at least one sub-signal line is disconnected at both sides of the short-circuit point. Thin film transistor display panel. In claim 1, The first to third signal lines may be formed on the same layer as the gate line. 3. The method of claim 2, The thin film transistor array panel of which the first to third connection lines are formed of the same layer as the data line. In claim 1, The circuit portion includes a shift register consisting of a plurality of stages cascaded and in turn generating an output signal, The first to third signal lines transmit first and second clock signals having a phase different from a power supply voltage to the shift register. Thin film transistor display panel. In claim 4, The first to third signal lines all have openings. The method of claim 5, And a fourth signal line configured to transfer an initialization signal to the shift register. In claim 6, And the first to fourth signal lines are arranged in sequence from a position far to a position close to the shift register. 8. The method of claim 7, The first to third connection lines and the first to third signal lines are connected through a connection auxiliary member. In claim 8, The connection auxiliary member is transparent and is connected to the first to third connection lines and the first to third signal lines through a plurality of contact holes. In claim 1, The circuit portion includes a plurality of transistors, wherein at least one of the transistors comprises a plurality of sub-transistors spaced apart from each other. In claim 1, The thin film transistor array panel of which the line widths of the sub signal lines are different from each other. A substrate on which a gate line, a data line, a pixel electrode and a thin film transistor are formed, First to third signal lines formed on the substrate and receiving signals from the outside; A gate driver including a circuit unit configured to output a gate signal to the gate line in response to a signal from the first to third signal lines; First to third connection lines that cross at least one of the first to third signal lines, and transfer signals from the first to third signal lines to the gate driver; Including, The first to third connection lines each include a plurality of secondary connection lines connected to each other, At least one of the secondary connection lines is shorted to one of the first to third signal lines, and the at least one secondary connection line is disconnected at both sides of the shorting point. Thin film transistor display panel. The method of claim 12, The thin film transistor array panel of which the first to third connection lines are formed of the same layer as the data line. The method of claim 13, The first to third signal lines may be formed on the same layer as the gate line. The method of claim 12, The circuit portion includes a shift register consisting of a plurality of stages cascaded and in turn generating an output signal, The first to third signal lines transmit first and second clock signals having a phase different from a power supply voltage to the shift register. Thin film transistor display panel. The method of claim 12, The first to third connection lines all have openings. The method of claim 16, The circuit portion includes a shift register consisting of a plurality of stages cascaded and in turn generating an output signal, And a fourth signal line configured to transfer an initialization signal to the shift register. The method of claim 17, And the first to fourth signal lines are arranged in sequence from a position far to a position close to the shift register. The method of claim 18, The first to third connection lines and the first to third signal lines are connected through a connection auxiliary member. The method of claim 19, The connection auxiliary member is transparent and is connected to the first to third connection lines and the first to third signal lines through a plurality of contact holes. The method of claim 12, The circuit portion includes a plurality of transistors, wherein at least one of the transistors comprises a plurality of sub-transistors spaced apart from each other. The method of claim 12, The thin film transistor array panel of which the line widths of the plurality of sub connection lines are different from each other. A display panel unit including a first substrate having a plurality of gate lines and a plurality of data lines, a second substrate facing the first substrate, and displaying an image in response to a data signal and a gate signal; A data driver which outputs the data signal to the plurality of data lines; A gate driver provided on the first substrate, the gate driver including first to third signal lines receiving a plurality of signals from outside and a circuit unit configured to output the gate signals to the plurality of gate lines in response to the external signals; First to third connection lines that cross at least one of the first to third signal lines, and transfer signals from the first to third signal lines to the gate driver; Including, The first to third connection lines each include a plurality of secondary connection lines connected to each other, At least one of the secondary connection lines is shorted to one of the first to third signal lines, and the at least one secondary connection line is disconnected at both sides of the shorting point. Display device. A display panel unit including a first substrate having a plurality of gate lines and a plurality of data lines, a second substrate facing the first substrate, and configured to display an image in response to a data signal and a gate signal; A data driver which outputs the data signal to the plurality of data lines; A gate driver provided on the first substrate, the gate driver including first to third signal lines receiving a plurality of signals from outside and a circuit unit configured to output the gate signals to the plurality of gate lines in response to the external signals; First to third connection lines that cross at least one of the first to third signal lines, and transfer signals from the first to third signal lines to the gate driver; Including, The first to third signal lines each include a plurality of sub signal lines connected to each other. At least one of the sub-signal lines is short-circuited with one of the first to third connecting lines, and the at least one sub-signal line is disconnected at both sides of the short-circuit point. Display device. Forming a gate driving circuit including a wiring part including a plurality of signal lines on the first substrate, a plurality of connection parts for transmitting a signal from the wiring part, and a circuit part for generating a gate signal according to a signal transmitted from the connection part; , And Disconnecting both of the wiring units with respect to the shorting point when one of the wiring units and one of the connection units are short-circuited; Repair method of the display device comprising a. Forming a gate driving circuit including a wiring part including a plurality of signal lines on the first substrate, a plurality of connection parts for transmitting a signal from the wiring part, and a circuit part for generating a gate signal according to a signal transmitted from the connection part; , And Disconnecting both ends of the connection part with respect to the short-circuit point when one of the wiring parts and one of the connection parts are short-circuited; Repair method of the display device comprising a.

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