KR20120089937A - Thin film transistor array substrate and method thereof - Google Patents

Abstract

In an embodiment, a thin film transistor array substrate may include a plurality of gate lines including a first conductive layer and a metal layer; A plurality of data lines defining a pixel region by crossing with each gate line; A plurality of thin film transistors connected to each gate line and each data line; A plurality of pixel electrodes connected to each thin film transistor and including a second conductive film; A protective film on the data line and the thin film transistor; And a plurality of common electrodes on the passivation layer of each pixel region.

Description

Thin film transistor array substrate and method for manufacturing same

Embodiments relate to a thin film transistor array substrate and a method of manufacturing the same.

Display devices for displaying information have been actively developed. For example, the display device may include a liquid crystal display device, a plasma display device, an electroluminescence display device, or a field emission display device. Such a display device has advantages of being lighter, having a larger screen, and having a smaller thickness than the CRT.

Among these, liquid crystal display devices are excellent in moving image display and have a high contrast ratio, and thus are widely used in notebook computers, monitors, televisions, and navigation devices.

The liquid crystal display device includes a thin film transistor array substrate on which thin film transistors are arranged, a color filter array substrate on which color filters are arranged, and a liquid crystal layer interposed therebetween.

1 is a plan view illustrating a conventional thin film transistor array substrate, and FIG. 2 is a cross-sectional view taken along the line II ′ of the thin film transistor array substrate of FIG. 1.

1 and 2, the gate line 3 and the data line 19 intersect to define a pixel region, and the thin film transistor 25 is electrically connected to the gate line 3 and the data line 19. Is connected.

The thin film transistor 25 is formed by the gate electrode 5, the semiconductor layer 17, the source electrode 21, and the drain electrode 23.

The semiconductor layer 17 includes an active layer 13 and an ohmic contact layer 15.

The gate insulating film 11 is formed on the gate electrode 5.

The pixel electrode 35 electrically connected to the thin film transistor 25 is formed in the pixel region.

In each pixel area, common electrodes 7 and 9 are formed to overlap the edge area of the pixel electrode 35 to form a storage capacitor.

The pixel electrode 35 may be electrically connected to the drain electrode 23 of the thin film transistor 25 through the drain contact hole 31 of the passivation layer 27.

The common electrodes 7 and 9 of each pixel area in the horizontal direction are electrically connected by the common connection electrode 6, and the jumping electrode 37 is connected between the common electrodes 7 and 9 of each pixel area in the vertical direction. Is electrically connected by.

The common connection electrode 6 is formed in the same layer with the same material as the common electrodes 7 and 9, but the jumping electrode 37 is formed in a different layer with a different material from the common electrodes 7 and 9.

The common electrodes 7 and 9 and the common connection electrode 6 may be formed of the same material, for example, chromium (Cr), on the same layer as the gate electrode 5.

The jumping electrode 37 may be formed of the same material, for example, ITO, on the same layer as the pixel electrode 35. ITO is significantly more resistant than chromium.

The jumping electrode 37 is electrically connected to the common electrodes 7 and 9 formed in the adjacent pixel regions through the first and second contact holes 33a and 33b of the passivation layer 27.

The jumping electrode 37 is formed to cross the gate line 3.

The parasitic capacitor is formed between the jumping electrode 37 and the gate line 3 due to the intersection of the jumping electrode 37 and the gate line 3. In addition, the jumping electrode 37 has a large resistance. Therefore, due to the capacitance of the parasitic capacitance and the resistance of the jumping electrode 37, there is a problem that coupling occurs to the common voltage signal by the gate signal supplied to the gate line 3.

As the common voltage signal is not constant and the common voltage signal is varied according to the gate signal, the gray level is lowered to a certain level, for example, 20 to 30 gray levels.

In addition, vertical and horizontal crosstalk failures occur due to the coupling of common voltage signals.

The embodiment provides a thin film transistor array substrate having a novel structure and a method of manufacturing the same.

The embodiment provides a thin film transistor array substrate and a method of manufacturing the same, which prevents coupling of a common voltage signal.

The embodiment provides a thin film transistor array substrate and a method of manufacturing the same that prevent vertical and horizontal crosstalk.

In an embodiment, a thin film transistor array substrate may include a plurality of gate lines including a first conductive layer and a metal layer; A plurality of data lines defining a pixel region by crossing each of the gate lines; A plurality of thin film transistors connected to the gate lines and the data lines; A plurality of pixel electrodes connected to each of the thin film transistors and including a second conductive layer; A passivation layer on the data line and the thin film transistor; And a plurality of common electrodes on the passivation layer of each pixel area.

According to an embodiment, a method of manufacturing a thin film transistor array substrate may include forming a first pattern group including a gate line, a gate electrode, and a pixel electrode including at least one of a conductive film and a metal film on the substrate; Forming a gate insulating film on the substrate including the first pattern group;

Forming a second pattern group including a semiconductor layer, a data line, a source electrode, and a drain electrode on the gate insulating layer; Forming a passivation layer on the substrate including the second pattern group, the protective layer including a contact hole exposing the drain electrode and a groove exposing the pixel electrode; And forming a third pattern group including a contact electrode and a common electrode on the passivation layer.

Embodiments can prevent coupling of common voltage signals.

Embodiments can prevent vertical and horizontal crosstalk.

1 is a plan view illustrating a conventional thin film transistor array substrate.
FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along line II ′.
3 is a plan view illustrating a thin film transistor array substrate according to an embodiment.
4 is a cross-sectional view of the thin film transistor array substrate of FIG. 3 taken along the line KK ′.
5A to 5D are cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to an embodiment.
6A through 6E are cross-sectional views illustrating a process of forming the first common voltage signal group of FIG. 5A.
7 is a graph showing a waveform change of a conventional common voltage signal and a common voltage signal of the embodiment.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a thin film transistor array substrate according to an exemplary embodiment, and FIG. 4 is a cross-sectional view taken along the line K-K ′ of the thin film transistor array substrate of FIG. 3.

Referring to FIG. 3, a gate line 57 is formed along a first direction, and a data line 71 is formed along a second direction, that is, a direction crossing the gate line 57.

The pixel region is defined by the intersection of the gate line 57 and the data line 71.

The thin film transistor 77 is electrically connected to the gate line 57 and the data line 71 of the pixel region.

The thin film transistor 77 is formed by the gate electrode 55, the semiconductor layer 67, the source electrode 73, and the drain electrode 75.

The gate line 57 may be electrically connected to the gate electrode 55 of the thin film transistor 77, and the data line 71 may be electrically connected to the source electrode 73 of the thin film transistor 77. .

The gate electrode 55 may protrude from the gate line 57, and the source electrode 73 may protrude from the data line 71.

The gate line 57 and the gate electrode 55 may include a conductive pattern 53a made of a transparent conductive material and a metal pattern 53b made of a metal material.

The conductive material may be one of ITO, IZO, and ITZO. The metal material is made of titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), copper (Cu) and molybdenum (Mo). It may be at least one selected from the group.

A pixel electrode 59 electrically connected to the drain electrode 75 of the thin film transistor 77 may be formed in the pixel region. The pixel electrode 59 may be formed of a transparent conductive material. The conductive material may be one of ITO, IZO, and ITZO.

The pixel electrode 59 may be formed on the same layer as the conductive pattern 53a of the gate line 57.

In other words, the conductive pattern 53a of the gate line 57 and the pixel electrode 59 may be formed of the same material on the same layer.

The contact electrode 83 may be formed to connect the pixel electrode 59 and the drain electrode 75 through the contact hole 81 and the pixel region groove 82. The contact hole 81 may be formed to expose the drain electrode 75, and the pixel region groove 82 may be formed to expose the pixel electrode 59.

The pixel region groove 82 may be formed to expose the entire region of the pixel electrode 59. Alternatively, the pixel region groove 82 may be formed to expose only a portion of the pixel region. In this case, the pixel region groove 82 may have a diameter similar to that of the contact hole 81.

The contact electrode 83 electrically connects the drain electrode 75 and the pixel electrode 59. That is, the contact electrode 83 may extend from the pixel electrode 59 of the pixel region groove 82 to the drain electrode 75 via the contact hole 81. One region of the contact electrode 83 may be electrically connected to the pixel electrode 59, and the other region of the contact electrode 83 may be electrically connected to the drain electrode 75 through the contact hole 81. have.

In each pixel area, common electrodes 85 and 87 may be formed to overlap the pixel electrode 59 to form a storage capacitor.

The first common connection electrode 89a is electrically connected between the common electrodes 85 of the pixel regions in the first direction, and the second common connection is connected between the common electrodes 85 and 87 of the pixel regions of the second direction. It may be electrically connected to the electrode 89b.

The common electrodes 85 and 87 and the first and second common connection electrodes 89a and 89b may be formed on the same layer as the contact electrode 83. The common electrodes 85 and 87, the first and second common connection electrodes 89a and 89b, and the contact electrode 83 may be formed of a metal material having almost no resistance. Metal material is a group consisting of titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), copper (Cu) and molybdenum (Mo) It may be at least one selected from.

The second common connection electrode 89b may be disposed to cross the gate line 57. Even if the second common connection electrode 89b crosses the gate line 57, the second common connection electrode 89b may be disposed. Since there is almost no resistance, even when a gate signal is supplied to the gate line 57, the common voltage signal flowing through the common electrodes 85 and 87 to the second common connection electrode 89b is influenced by the gate signal. Since the signal is hardly received, the coupling rarely occurs in the common voltage signal by the gate signal.

As shown in Fig. 7, the conventional common voltage signal causes a considerably large coupling due to the high resistance of the jumping electrode. In contrast, the common voltage signal of the embodiment is formed of a metal material having almost no resistance, so that little coupling occurs.

Referring to FIG. 4, a first pattern group including a gate line 57, a gate electrode 55, and a pixel electrode 59 is formed on the substrate 51.

The gate electrode 55 may protrude from the gate line 57.

The gate line 57 and the gate electrode 55 may include a double layer of a conductive pattern 53a and a metal pattern 53b. The conductive pattern 53a may be a transparent conductive material including one of ITO, IZO, and ITZO. The metal pattern 53b includes titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), copper (Cu), and molybdenum (Mo). Metal material including at least one selected from the group consisting of

The pixel electrode 59 may include the conductive pattern 53a. The pixel electrode 59 may be formed by removing the metal pattern 53b from a double layer of the conductive pattern 53a and the metal pattern 53b.

A gate insulating layer 61 is formed on the substrate 51 including the first pattern group.

A second pattern group including a semiconductor layer 67, a data line 71, a source electrode 73, and a drain electrode 75 is formed on the gate insulating layer 61.

The semiconductor layer 67 may include an active layer 63 and an ohmic contact layer 65.

The data line 71 may be formed to cross the gate line 57. The pixel region may be defined by the intersection of the gate line 57 and the data line 71.

The source electrode 73 may protrude from the data line 71.

The data line 71, the source electrode 73, and the drain electrode 75 may include titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), and gold (Au). , Metal material including at least one selected from the group consisting of tungsten (W), copper (Cu), and molybdenum (Mo).

The thin film transistor 77 may be formed by the gate electrode 55, the semiconductor layer 67, the source electrode 73, and the drain electrode 75.

A passivation layer 79 is formed on the substrate 51 including the second pattern group, and the contact hole 81 and the pixel electrode 59 exposing the drain electrode 75 are exposed to the passivation layer 79. An exposed pixel region groove 82 may be formed.

The contact hole 81 may be formed through the passivation layer 79, and the pixel region groove 82 may be formed through the gate insulating layer 61 and the passivation layer 79.

The pixel region groove 82 may be formed on the entire region of the pixel electrode 59, or may be formed in a partial region of the pixel electrode 59. When the pixel region groove 82 is formed in a portion of the pixel electrode 59, the passivation layer 79 may be formed on another region except for the region of the pixel electrode 59.

A third pattern group including the common electrodes 85 and 87, the first and second common connection electrodes 89a and 89b, and the contact electrode 83 is formed on the passivation layer 79.

The common electrodes 85 and 87 are formed on the passivation layer 79 of each pixel region, and the first common connection electrode 89a is electrically connected between the common electrodes 85 of the pixel regions in the first direction. In addition, the second common connection electrode 89b may electrically connect the common electrodes 85 and 87 of the pixel areas in the second direction. The second common connection electrode 89b may be formed on the passivation layer 79 to cross the gate line 57.

The contact electrode 83 may be electrically connected to the drain electrode 75 through the contact hole 81, and may be electrically connected to the pixel electrode 59 through the pixel region groove 82.

The common electrodes 85 and 87, the first and second common connection electrodes 89a and 89b, and the contact electrode 83 are titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), and platinum. It may be a metal material including at least one selected from the group consisting of (Pt), gold (Au), tungsten (W), copper (Cu), and molybdenum (Mo).

The second common connection electrode 89b may be formed to cross the gate line 57.

Since the second common connection electrode 89b is formed of a metal material having almost no resistance, the second common connection electrode 89b is coupled to the common voltage signal flowing to the second common connection electrode 89b by a gate signal supplied to the gate line 57. This rarely occurs. Therefore, it is possible to prevent the gray scale value from being lowered due to the coupling of the common voltage signal and to prevent vertical and horizontal crosstalk.

Accordingly, the image quality of the liquid crystal display device can be improved.

5A to 5D are cross-sectional views illustrating a manufacturing process of a thin film transistor array substrate according to an embodiment.

As shown in FIG. 5A, a first pattern group including the gate line 57, the gate electrode 55, and the pixel electrode 59 is formed on the substrate 51 by using a first mask process.

Formation of the first pattern group will be described in more detail with reference to FIGS. 6A to 6E.

As shown in FIG. 6A, the conductive film 91, the metal film 93, and the photosensitive film 95 are formed on the substrate 51, and the halftone mask 97 is aligned thereon.

The conductive layer 91 may include one of ITO, IZO, and ITZO. The metal layer 93 may include titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), gold (Au), tungsten (W), copper (Cu), and molybdenum (Mo). It may include at least one selected from the group consisting of

The halftone mask 97 may include a transmission region 97a through which light is transmitted, a blocking region 97b through which light is blocked, and a semitransmissive region 97c through which light is partially transmitted.

The blocking region 97b may be positioned in a region forming a gate line and a gate electrode, and the transflective region 97c may be positioned in a region forming a pixel electrode.

As shown in FIG. 6B, when the light is irradiated with the halftone mask 97, the photosensitive film 95 corresponding to the transmission region 97a is removed, and the photosensitive film 95 corresponding to the blocking region 97b is removed. ) May be present as is, and the first photosensitive pattern 95a may be formed in the photosensitive layer 95 corresponding to the transflective region 97c from which an upper region is removed. Therefore, the photosensitive film 95 corresponding to the transflective area 97c may have a lower thickness than the photosensitive film 95 corresponding to the blocking area 97b.

As shown in FIG. 6C, the metal layer 93 and the conductive layer 91 are successively patterned using the first photosensitive pattern 95a as a first etching mask to form the gate line 57 and the gate electrode ( 55). The gate line 57 and the gate electrode 55 may be formed of a double layer of a conductive pattern 53a and a metal pattern 53b.

As shown in FIG. 6D, to completely remove the first photosensitive pattern 95a corresponding to the transflective region 97c so that the metal film 53b corresponding to the transflective region 97c is exposed. The first photosensitive pattern 95a is ashed.

As a result, an upper region of the first photosensitive pattern 95a corresponding to the blocking region 97b is removed, but a lower region of the first photosensitive pattern 95a corresponding to the blocking region 97b remains and the transflective portion is left. The second photosensitive pattern 95b may be completely removed from the first photosensitive pattern 95a corresponding to the region 97c.

As shown in FIG. 6E, the pixel electrode 59 is formed by removing the metal film 93 corresponding to the transflective region 97c by using the second photosensitive pattern 95b as a second etching mask. .

Referring to FIG. 5B, a gate insulating layer 61 is formed on a substrate 51 including the first pattern group, and a semiconductor layer 67 is formed on the gate insulating layer 61 by using a second mask process. A second pattern group including the data line 71, the source electrode 73, and the drain electrode 75 is formed.

The semiconductor layer 67 may include an active layer 63 formed from an amorphous film and an ohmic contact layer 65 formed from an amorphous film including impurities.

The data line 71 may cross the gate line 57 to define a pixel area.

The thin film transistor 77 may be formed by the gate electrode 55, the semiconductor layer 67, the source electrode 73, and the drain electrode 75.

The data line 71, the source electrode 73, and the drain electrode 75 may include titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), platinum (Pt), and gold (Au). , Tungsten (W), copper (Cu), and molybdenum (Mo).

Referring to FIG. 5C, the passivation layer 79 is formed on the substrate 51 including the second pattern group, and the contact hole 81 and the pixel region groove 83 are formed using a third mask process. .

The passivation layer 79 may include an inorganic insulating material such as silicon nitride (SiN _x ) or silicon oxide (SiO _x ) or an organic insulating material such as benzocyclobutene (BCB).

The contact hole 81 may be formed by removing the passivation layer 79 to expose the drain electrode 75. The pixel region groove 82 may be formed by removing the passivation layer 79 and the gate insulating layer 61 to expose the pixel electrode 59.

Referring to FIG. 5D, a contact electrode 83, a common electrode 85 and 87, and first and second common connection electrodes 89a and 89b are formed on the passivation layer 79 by using a fourth mask process. The third pattern group is formed.

The contact electrode 83, the common electrodes 85 and 87, and the first and second common connection electrodes 89a and 89b may include titanium (Ti), chromium (Cr), nickel (Ni), and aluminum (Al). It may include at least one selected from the group consisting of platinum (Pt), gold (Au), tungsten (W), copper (Cu) and molybdenum (Mo).

The third pattern group may be formed of the same metal material as the first and second pattern groups or may be formed of a different metal material.

The contact electrode 83 may be electrically connected to the drain electrode 75 through the contact hole 81, and may be electrically connected to the pixel electrode 59 through the pixel region groove 82.

The contact electrode 83 may be a partial region of an upper surface of the pixel electrode 59, a side surface of the pixel region groove 82, an upper surface of the protective layer 79 between the contact hole 81 and the pixel region. The contact hole 81 may be formed in contact with the side surface of the contact hole 81 and the drain electrode 75.

The common electrodes 85 and 87 may be formed along the edge regions of the pixel regions and overlap the edge regions of the pixel electrodes 59 to form storage capacitors.

The first common connection electrode 89a is electrically connected between the common electrodes 85 of the pixel regions in the first direction, and the second common connection electrode 89b is the common electrodes of the pixel regions in the second direction. Electrical connection can be made between (85, 87).

The first and second common connection electrodes 89a and 89b may be formed on the passivation layer 79.

The second common connection electrode 89b may be formed to cross the gate line 57.

Since the second common connection electrode 89b is formed of a metal material having no resistance, the common voltage signal supplied to the second common connection electrode 89b is affected by the coupling signal by the gate signal supplied to the gate line 57. You rarely get it. Therefore, since the common voltage signal supplied to the second common connection electrode 89b is kept stable, the common electrodes 85 and 87 of adjacent pixel regions may also maintain a stable common voltage signal.

Therefore, the gray scales can be prevented from being reduced by the coupling, and vertical and horizontal crosstalk can be prevented.

51: substrate 53a: transparent conductive pattern
53b: metal pattern 55: gate electrode
57: gate line 59: pixel electrode
61: gate insulating film 63: active layer
65: ohmic contact layer 67: semiconductor layer
71: data line; 73: source electrode
75: drain electrode 77: thin film transistor
79: Shield 81: Contact Hole
82: pixel region groove 83: contact electrode
85, 87: common electrode 89a, 89b: common connection electrode

Claims (16)

A plurality of gate lines including a first conductive layer and a metal layer;
A plurality of data lines defining a pixel region by crossing each of the gate lines;
A plurality of thin film transistors connected to the gate lines and the data lines;
A plurality of pixel electrodes connected to each of the thin film transistors and including a second conductive layer;
A passivation layer on the data line and the thin film transistor; And
A thin film transistor array substrate comprising a plurality of common electrodes on the passivation layer of each pixel area. The method of claim 1,
The thin film transistor array substrate of which the first conductive film and the second conductive film are formed of the same material on the same layer. The method of claim 1,
The common electrode includes a thin film transistor array substrate including the same material as the data line. The method of claim 1,
And a contact electrode for connecting the pixel electrode and the drain electrode of the thin film transistor. The method of claim 4, wherein
And the contact electrode is formed on the same layer as the common electrode. The method of claim 4, wherein
And the contact electrode is connected to the drain electrode and the pixel electrode through a contact hole in which the drain electrode is exposed and a pixel region groove in which the pixel electrode is exposed. The method of claim 1,
The common electrode is a thin film transistor array substrate formed on the protective film. The method of claim 1,
And a common connection electrode connecting between the common electrodes crossing the gate line. The method of claim 8,
The common connection electrode is a thin film transistor array substrate formed on the same layer as the common electrode. Forming a first pattern group including a gate line, a gate electrode, and a pixel electrode including at least one of a conductive film and a metal film on a substrate;
Forming a gate insulating film on the substrate including the first pattern group;
Forming a second pattern group including a semiconductor layer, a data line, a source electrode, and a drain electrode on the gate insulating layer;
Forming a passivation layer on the substrate including the second pattern group, the protective layer including a contact hole exposing the drain electrode and a groove exposing the pixel electrode; And
Forming a third pattern group including a contact electrode and a common electrode on the passivation layer. The method of claim 10,
And the gate line and the gate electrode include the conductive layer and the metal layer. The method of claim 10,
And the pixel electrode comprises the conductive film. The method of claim 10,
And the contact electrode is connected to the drain electrode and the pixel electrode through the contact hole and the groove.
The method of claim 10,
A pixel region is defined by the intersection of the gate line and the data line,
The common electrode is formed in each pixel area,
Forming the third pattern group,
And forming a common connection electrode crossing the gate line and connecting between the common electrodes of the pixel areas. The method of claim 14,
The first to third metal pattern groups include a metal material. The method of claim 10,
And the contact hole is formed through the passivation layer and the groove is formed through the gate insulating layer and the passivation layer.

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