KR100443538B1 - A array substrate for Liquid crystal display and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method for manufacturing an array substrate for a liquid crystal display device manufactured by simplifying a process.

In detail, the present invention is to form a gate wiring and a data wiring on the array substrate by the electrodeposition method, and at the same time to produce an array substrate by a three-mask process using a method of patterning the insulating film by the back exposure method do.

When the array substrate is manufactured in the manner as described above, the productivity of the product can be improved.

Description

A array substrate for liquid crystal display and method for fabricating the same

The present invention relates to an image display device, and more particularly, to a method of manufacturing a liquid crystal display (LCD) including a thin film transistor (TFT).

In particular, the present invention relates to a method of manufacturing by reducing the number of masks used in manufacturing a liquid crystal display, and a liquid crystal display manufactured by the method.

The driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, the active matrix liquid crystal display (AM-LCD) in which the above-described thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner is attracting the most attention due to its excellent resolution and ability to implement video.

1 is a view schematically showing a liquid crystal panel of a general liquid crystal display device.

As shown in the drawing, a general color liquid crystal display 11 includes a black matrix 6 formed between a color filter 7 and each of the color filters 7 and a common electrode 18 deposited on the color filter and the black matrix. ) Is formed of an upper substrate (5) formed thereon, a pixel region (P), a pixel electrode (17) formed on the pixel region, and a lower substrate (10) on which switching elements (T) and array wiring are formed. The liquid crystal 9 is filled between 5) and the lower substrate 22.

The lower substrate 10 may also be referred to as an array substrate, and the thin film transistor T, which is a switching element, may be positioned in a matrix type, and the gate wiring 14 may cross the plurality of thin film transistors TFT. ) And data wirings 22 are formed.

In this case, the pixel region P is an area defined by the gate wiring 14 and the data wiring 22 intersecting. A transparent pixel electrode 36 is formed on the pixel region P as described above. .

The pixel electrode 36 and the common electrode 18 use a transparent conductive metal having relatively high light transmittance, such as indium-tin-oxide (ITO).

The driving of the liquid crystal panel having the configuration as described above is due to the electro-optical effect of the liquid crystal.

In detail, the liquid crystal layer 9 is a dielectric anisotropic material having spontaneous polarization characteristics, and when a voltage is applied, bipolars are formed by spontaneous polarization to arrange the molecules according to the direction of application of the electric field. This has changing characteristics.

Therefore, the optical characteristic is changed according to this arrangement state, thereby causing electrical light modulation.

By the light modulation phenomenon of the liquid crystal, an image is realized by a method of blocking or passing light.

FIG. 2 is an enlarged plan view schematically illustrating some pixels of an array substrate in the configuration of FIG. 1.

The elements necessary for driving the liquid crystal layer (9 of FIG. 1) of the above-described configuration may include a gate wiring 14 for transmitting a scanning signal (gate voltage) and an image signal (data voltage). A thin film transistor T, which is a switching element connected to the data wiring 22, the gate wiring and the data wiring, and positioned at the intersection of the gate wiring 14 and the data wiring 22, and the thin film. It is a pixel electrode 36 connected to the transistor.

The thin film transistor T includes a gate electrode 12 connected to the gate wiring 14, and a source electrode 24 and a drain electrode formed to overlap a predetermined area with the gate electrode 12 on the gate electrode 12. And the source electrode 24 and the drain electrode 26 are spaced apart from each other with the active layer 18 therebetween.

The active layer 18 is generally formed using amorphous silicon (a-Si: H), and in some cases, may be formed of polysilicon.

Although not shown, an ohmic contact layer is positioned between the source and drain electrodes 24 and 26 and the active layer 18.

In this case, the source electrode 24 is formed to be connected to the data line 22, and the drain electrode 26 is connected to the pixel electrode 36 positioned on the pixel area P.

A portion of the pixel electrode 36 extends over a portion of the gate line 14 to form a storage capacitor C together with the gate line 14.

Hereinafter, a manufacturing process of a conventional active matrix liquid crystal display device will be described with reference to FIGS. 3A to 3E.

In general, the structure of a thin film transistor used in a liquid crystal display is an inverted staggered structure. This is because the structure is the simplest and the performance is excellent.

In addition, the reverse staggered thin film transistor is divided into a back channel etch type (EB) and an etch stopper type (ES) according to a channel forming method, and a simple back channel etch type structure is applied. The liquid crystal display device manufacturing process will be described.

First, a foreign material or an organic material is removed from the substrate 10, and the metal film is deposited by sputtering after cleaning to improve the adhesion between the metal film of the gate material to be deposited and the glass substrate. .

3A is a step of forming a gate electrode 12 and a gate wiring 14 by patterning with a first mask after the deposition of the metal film. The gate electrode 12 material, which is important for the operation of the active matrix liquid crystal display, is mainly composed of aluminum having low resistance in order to reduce the RC delay, but pure aluminum has a weak chemical corrosion resistance, and is healed in a subsequent high temperature process. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to the formation of the hi-lock.

In the above-described process, the gate electrode 12 is formed by protruding a predetermined area from the gate wiring 14.

Next, one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 10 on which the gate electrode 12 and the gate wiring 14 are formed. A gate insulating film 16 as a first insulating film is formed.

Next, referring to FIG. 3B, amorphous silicon (a-Si: H), which is a semiconductor material, and amorphous silicon (n ⁺ a-Si: H) containing impurities are successively formed on the gate insulating layer 16. Deposit.

After depositing the semiconductor material, the second layer is patterned to form an active layer 18 and an ohmic contact layer 20 planarly overlapping the active layer 18.

The ohmic contact layer 20 formed of amorphous silicon containing the impurity is to reduce contact resistance between a metal layer to be formed later and the active layer 18.

Thereafter, as shown in FIG. 3C, a metal layer is deposited and patterned with a third mask to intersect the gate line 14 perpendicularly to define the pixel area P and the data line 22. A source electrode 24 protruding from one side of the gate electrode 12 and a drain electrode 26 spaced a predetermined distance from the gate electrode 12 are formed at 22.

At the same time, an island-shaped storage metal layer 28 is formed on a portion of the gate wiring 14 passing through the pixel region P, that is, the storage region S in which the storage capacitor is formed.

Subsequently, the ohmic contact layer 20 existing between the source electrode 24 and the drain electrode 26 is removed using the source and drain electrodes 24 and 26 as masks. If the ohmic contact layer existing between the source electrode 24 and the drain electrode 26 is not removed, serious problems may occur in the electrical characteristics of the thin film transistor T, and a great problem may occur in performance.

Careful attention is required to removing the ohmic contact layer. When the ohmic contact layer is actually etched, since there is no etch selectivity with the active layer formed thereunder, the active layer is overetched by about 50 to 100 nm. The etching uniformity directly affects the characteristics of the thin film transistor T. Crazy

Thereafter, as shown in FIG. 3D, an insulating film is deposited on the entire surface of the substrate on which the source electrode and the drain electrode are formed and patterned with a fourth mask to form a protective film 30 for protecting the active layer 18. . The passivation layer 30 may adversely affect the characteristics of the thin film transistor due to the unstable energy state of the active layer 18 and the residual material generated during etching, so that the inorganic silicon nitride layer (SiN _x ) or silicon oxide layer (SiO ₂ ) It is formed from organic benzocyclobutene (BCB) or the like.

The passivation layer 30 requires high light transmittance, moisture, and durability.

A process of forming a contact hole during patterning of the passivation layer 30 is added. A drain contact hole 32 exposing a part of the drain electrode 26 and a storage contact hole exposing a part of the storage metal layer 28 are formed. 34) respectively.

The process illustrated in FIG. 3E is a process of forming a pixel electrode 36 by depositing a transparent conducting oxide (TCO) and patterning with a fifth mask.

Depositing and patterning one selected from a group of transparent conductive metals including indium tin oxide (ITO) and indium tin oxide (IZO) on the patterned passivation layer 30 to expose the partially exposed drain electrode 26; At the same time, the pixel electrode 36 positioned on the pixel region P is formed while contacting the exposed storage metal layer 28.

In this case, the storage metal layer 28 in contact with the pixel electrode 36 in the storage region S functions as a second storage electrode, and the gate wiring 14 functions as a first storage electrode. Capacitor C is configured.

By the above-described process, the thin film transistor substrate of the liquid crystal display device is completed.

The manufacturing method of the active matrix liquid crystal display described above is a five mask method used basically.

The mask process used in manufacturing a thin film transistor substrate used in a liquid crystal display device involves various processes such as cleaning, deposition, baking, and etching. Therefore, even if the mask process is shortened once, the manufacturing time is considerably reduced, which is advantageous in terms of production yield and manufacturing cost.

Accordingly, an object of the present invention is to provide a method for shortening the number of mask processes used in manufacturing a liquid crystal display device and to improve the production yield of a product.

1 is a view schematically showing a general liquid crystal display device,

2 is a plan view showing some pixels of an array substrate for a liquid crystal display device;

3A to 3E are sectional views taken along the line III-III of FIG. 2 and shown in a conventional process sequence.

4 is a plan view showing a part of an array substrate for a liquid crystal display device according to the present invention;

5a to 5e is a plan view showing a process sequence according to the present invention,

6A to 6E are cross-sectional views taken along lines VI-VI and VI-VII of FIGS. 5A to 5E.

<Explanation of symbols for the main parts of the drawings>

100 substrate 102 first gate wiring

104: gate shorting bar 106: gate pad

108: gate connection wiring 110: second gate wiring

112: gate electrode 116b: active layer

122: first data wiring 123: data shorting bar

124: pixel electrode 126: drain electrode

128: source electrode 130: data pad

132: connection wiring

In order to achieve the above object, the liquid crystal display device array substrate according to the present invention includes a substrate; A plurality of gate wirings defining a plurality of pixel regions by vertically crossing each other with a first insulating film interposed therebetween, comprising a double layer of a transparent electrode and an opaque electrode, and each having a gate pad and a data pad at one end thereof. And date wiring; A pixel electrode formed on the pixel area and having one side extending over the gate wiring; A gate electrode formed at an intersection point of the gate wiring and the data wiring, wherein a portion of the gate wiring is defined, a source electrode extending from the data wiring, and a predetermined distance from the source electrode and spaced apart from the source electrode; A thin film transistor including a drain electrode protruding upwardly and a semiconductor layer disposed on the gate electrode and in contact with a source electrode and a drain electrode; The passivation layer may cover the gate line, the data line, and the thin film transistor.

The plurality of gate wires are connected to each other by a gate shorting bar, and a portion of the gate pad and the data pad is formed with the transparent electrode layer exposed.

The opaque metal constituting the gate wiring and the data wiring may be formed by electrodeposition of a metal on the transparent electrode using an electroplating method.

An array substrate manufacturing method for a liquid crystal display device according to an aspect of the present invention includes the steps of preparing a substrate; Depositing a transparent metal on the substrate and patterning the same by using a first mask process to include a gate pad at one end and defining a portion of the gate electrode as a gate electrode, and a plurality of gate wires connected to the gate pad. Forming a gate shorting bar connected to the one; Dipping a substrate on which the gate wiring and the gate shorting bar are formed in an electrolytic solution and applying a voltage to electrodeposit metal on a portion of the gate pad adjacent to the gate wiring and the gate wiring; Depositing an insulating material on the entire surface of the substrate on which the gate wiring is formed to form a gate insulating film, which is a first insulating film; Sequentially depositing and patterning pure amorphous silicon and impurity amorphous silicon on the substrate on which the gate insulating film is formed, thereby forming an active layer and an ohmic contact layer planarly overlapping the gate wiring; A transparent electrode material is deposited on the entire surface of the substrate on which the active layer and the ohmic contact layer are formed, and then patterned by a second mask process to define a pixel area vertically crossing the gate wiring and include a data pad at one end. A data wiring including a source electrode formed to protrude above the gate wiring, a data shorting bar connected to the data pad to connect the plurality of data wirings to one, and one side protrudes above the gate electrode on the pixel region. Forming a pixel electrode extending from the source electrode and a drain electrode spaced a predetermined distance apart from the source electrode, and forming a pixel electrode extending on the other side of the gate wiring; Removing the exposed ohmic contact layer in a predetermined manner; Dipping a substrate on which the data line and the data shorting bar are formed in an electrolytic solution and applying a voltage to electrodeposit metal on a portion of the data pad close to the data line and the data line; Forming a passivation layer, which is a second insulating layer, on the data line and the gate line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

4 is a plan view schematically illustrating a part of an array substrate for a liquid crystal display according to the present invention.

As shown, a plurality of gate wirings 102 and 110 arranged in one direction on the substrate 100 and a plurality of data wirings 122 and 134 perpendicularly intersecting the gate wirings 102 and 110 to define a plurality of pixel regions P. As shown in FIG. ).

The plurality of gate wires 102 and 110 are connected to one through the gate shorting bar 104.

In this case, one end of the gate wirings 102 and 110 may be referred to as a gate pad 106, and the gate shorting bar 104 may be connected to the gate pad 106 through a connection wiring 108.

One end of the data line 122 and 134 and the data line 122 and 134 is called a data pad 130, and the data shorting bar 123 is connected to the data pad 130 through a connection line 132. do.

The gate wirings 102 and 110 and the data wirings 122 and 134 are formed of a double layer of a transparent electrode and an opaque electrode.

In this case, the opaque electrode is formed through an electrodeposition method to immerse the transparent electrode in an electrolyte solution and apply a voltage to form an opaque electrode on the surface of the transparent electrode.

In the above-described configuration, a transparent pixel electrode 124 is formed in the pixel area P, and the pixel electrode 124 forms a data line 122 and 134 (forming a primary data line through a transparent electrode). Process).

The thin film transistor T is formed at a portion where the data lines 122 and 134 intersect the gate lines 102 and 110. The thin film transistor T according to the present invention includes a gate electrode 112 which is a part of the gate lines 102 and 110, and The drain electrode 126 which is a part of the pixel electrode 124 and protrudes and extends above the gate wiring, and is spaced apart from the drain electrode 126 by a predetermined interval, and the gate electrode (the first electrode) in the data wirings 122 and 134. It consists of a source electrode 128 formed to extend above the 112.

In addition, the pixel electrode extending over a portion of the gate wiring forms a storage capacitor C together with the gate wirings 102 and 110 under the gate wiring.

In the above-described configuration, the active layer 116b formed between the source electrode 128 and the drain electrode 126, and the passivation layer 136 covering each of the wirings and the thin film transistor T are the gate wirings 102 and 110. And back exposure using the data wirings 122 and 134.

The process for manufacturing the array substrate according to the present invention as described above, the photolithography process for the first transparent electrode pattern for forming the gate wiring 110, the data wiring 134 and the pixel electrode 124 Photolithography process for the second transparent electrode pattern for forming a photonic annealing process and photolithography process for removing the ohmic contact layer 116b between the thin film transistor (T) and the storage capacitor (C). Can be produced through.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to the present invention will be described with reference to FIGS. 5A to 5D and 6A to 6D.

5A to 5D are process plan views sequentially illustrating a manufacturing process of an array substrate according to the present invention, and FIGS. 6A to 6D are cross-sectional views taken along the lines VI-VI and VIII-V of FIGS. 5A to 5D. (VI-VI is gate wiring and thin film transistor region, and Ⅶ-Ⅶ is data wiring region)

First, FIGS. 5A and 6A illustrate a process of forming a gate wiring and a gate electrode as a first mask process.

As shown in the drawing, one selected from a group of transparent conductive materials including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the transparent insulating substrate 100 and patterned to form one direction. A plurality of first gate wirings 102 and a gate shorting bar 104 connecting the first gate wirings 102 as one are formed.

In this case, one end of the first gate wiring 102 is referred to as a gate pad 106.

In the drawing, portions branched from the shorting bars 104 to the gate pads 106 are referred to as connection wirings 108.

Next, the shorting bar 104 and the substrate 100 covered with a portion of the gate pad 108 connected to the shorting bar 104 are immersed in an electrolyte solution.

In this case, when a voltage is applied to one end of the shorting bar 104 formed on the substrate 100 immersed in the electrolyte solution, metal is electrodeposited on the surface of the patterned transparent electrode of the unshielded region.

Accordingly, an opaque second gate line 110 (hereinafter, referred to as reference numeral 110) is formed on the first gate line 102 formed of the transparent electrode.

In this case, a part of the gate wiring 110 is used as the gate electrode 112.

The metal is formed of one of conductive metal groups including chromium (Cr), tungsten (W), aluminum (Al), molybdenum (Mo), and the like.

Deposition of one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the gate wiring 110 and the gate electrode 112 are formed. The gate insulating film 114 which is an insulating film is formed.

Next, FIGS. 5B and 6B illustrate a process of forming an active layer and an ohmic contact layer by using back exposure. The front surface of the substrate 100 on which the gate insulating layer 114 is formed. The semiconductor layers 116a and 118a are formed by continuously depositing pure amorphous silicon and amorphous silicon containing impurities on the substrate.

A PR layer 120 is formed by applying photoresist (hereinafter, referred to as "PR") on the semiconductor layers 116a and 118a.

In this case, the PR uses positive PR in which a portion of the light is developed by the developer.

When the light is irradiated from the lower part of the substrate 100 on which the PR layer is formed, all PR layers 120 except for the upper part of the gate wiring 110 are exposed by the light L, and then removed in the developing process. .

As a result, the semiconductor layer remains only on the gate wiring 110. In this case, an amorphous silicon layer disposed below the semiconductor layer is referred to as an active layer 116b and an impurity disposed above the active layer. The amorphous silicon layer is called an ohmic contact layer 118b.

Next, FIGS. 5C and 6C illustrate a second mask process in which data lines, a source electrode, a drain electrode, a pixel electrode, and an active channel are formed.

The plurality of gate wirings 110 may be formed by depositing and patterning the transparent conductive metal as described above on the entire surface of the substrate 100 on which the active layer 116b and the ohmic contact layer 118b are planarly overlapped. A plurality of first data wires 122 defining a plurality of pixel regions P and a data shorting bar 123 connecting the plurality of first data wires into one,

Simultaneously formed on the pixel region P, one side protrudes and extends on the gate electrode 112 defined in the gate wiring 110 of the thin film transistor T region, and the other side is the gate wiring 110. A pixel electrode 124 extending above is formed.

The portion protruding from the gate electrode 112 becomes the drain electrode 126 of the thin film transistor T.

In addition, protruding and extending from the first data line 122, the extended portion is formed around the drain electrode 126 while being spaced apart from the drain electrode 126 by a predetermined interval, and the extended portion is a source. It becomes the electrode 128.

The first data line 122 is connected to the data shorting bar 123 as one.

In this case, an end of the first data line 122 is referred to as a data pad 130, and a portion branched from the data shorting bar 124 and extended to the data pad 126 is referred to as a connection line 132. Do it.

Next, as shown in FIGS. 5D and 6D, the ohmic contact layer 118b exposed between the transparent electrode patterns is removed and a thin film transistor T and a storage capacitor C are formed in a third mask process. It is a process of removing amorphous silicon in between.

In this case, the ohmic contact layer exposes the active channel CH between the source electrode and the drain electrode 128 and 126. As a result, all of the ohmic contact layer 118b on the gate wiring 110 except for the lower portion of the source electrode 128 and the drain electrode 126 and the lower portion of the pixel electrode overlapping the gate wiring 110 is removed. Results.

Next, the second data line 134, which is an opaque metal electrode, is formed on the first data line 122 patterned with the transparent electrode by using an electrodeposition method, which is the same as the method of forming the gate line 110. Form.

In this case, an opaque metal is deposited on the transparent source electrode 128.

In the above-described process, the thin film transistor T and the storage capacitor C may be formed.

In this case, the active layer 116b, which is an amorphous silicon layer existing between the thin film transistor T and the storage capacitor (not shown), needs to be removed.

When a signal is applied, a signal may flow between the thin film transistor T and the storage capacitor C by the amorphous silicon layer 116b. This is because it causes a malfunction of the liquid crystal panel.

Therefore, the amorphous silicon layer 116b existing between the thin film transistor T and the storage capacitor C is removed through a third mask process, which is a separate photolithography process.

In this case, a lower gate insulating layer 114 is exposed through the removed amorphous silicon region B.

Next, as shown in FIGS. 5E and 6E, a group of organic insulating materials including benzocyclobutene (BCB), an acryl resin, and the like and silicon nitride (SiN _x ) in some cases on the substrate. A second insulating layer is formed by depositing one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ).

In this case, since the second insulating layer covers the entire area of the substrate, a photolithography process for exposing the pixel region P, the data pad 130, and the gate pad 106 is required.

A feature of the present invention for omitting the photolithography process as described above is to pattern the protective film by the back exposure method as described above.

In detail, after depositing the second insulating film, a positive PR layer (not shown) is formed on the second insulating film.

Next, when light is irradiated on the back surface of the substrate 100, the remaining PR layers (not shown) except for the upper portions of the gate line 110 and the data line 134 are exposed by light.

Next, when the second insulating film exposed between the PR layers (not shown) is removed through the developing process, the passivation layer 136 formed by patterning the second insulating layer may include the data wiring 134 and the gate wiring formed of opaque metal. The upper portion of the 110 and the thin film transistor (T) is formed in a structure covering.

In the above configuration, a portion of the gate pad 106 and the data pad 130, which are transparent electrodes, is exposed to the outside.

Therefore, the array substrate for a liquid crystal display device according to the present invention can be manufactured in a three mask process using a metal electroplating method and a back exposure method.

When manufacturing a liquid crystal display according to the embodiment of the present invention described above has the following features.

First, since the image area of the array substrate can be manufactured with three masks, the production time is shortened.

Second, the reduced mask process prevents yield reduction due to mis-alignment.

Third, there is a cost reduction effect due to the reduction of the manufacturing process of the liquid crystal display device.

Claims (13)

A substrate; A plurality of gate wirings defining a plurality of pixel regions by vertically crossing each other with a first insulating film interposed therebetween, comprising a double layer of a transparent electrode and an opaque electrode, and each having a gate pad and a data pad at one end thereof. And date wiring; A pixel electrode formed on the pixel area and having one side extending over the gate wiring; A gate electrode formed at an intersection point of the gate wiring and the data wiring, wherein a portion of the gate wiring is defined, a source electrode extending from the data wiring, and a predetermined distance from the source electrode and spaced apart from the source electrode; A thin film transistor including a drain electrode protruding upwardly and a semiconductor layer disposed on the gate electrode and in contact with a source electrode and a drain electrode; A passivation layer covering the gate line, data line, and thin film transistor Array substrate for a liquid crystal display device comprising a. The method of claim 1, The plurality of gate wirings are connected to one by a gate shorting bar array substrate. The method according to any one of claims 1 to 2, And a portion of the gate pad and the data pad, wherein the transparent electrode layer is exposed. The method of claim 1, And the semiconductor layer is an active layer and an ohmic contact layer formed between the active layer, the source electrode, and the drain electrode. The method of claim 1, And the pixel electrode overlaps the lower gate wiring with the first insulating film interposed therebetween to form a storage capacitor. The method of claim 1, And a transparent electrode forming the gate wiring and the data wiring, and the pixel electrode being selected from a group of transparent conductive metals including ITO and IZO. The method of claim 1, The opaque metal constituting the gate wiring and the data wiring is formed by electrodeposition of a metal on top of the transparent electrode using an electroplating method. Preparing a substrate; Depositing a transparent metal on the substrate and patterning the same by using a first mask process to include a gate pad at one end and defining a portion of the gate electrode as a gate electrode, and a plurality of gate wires connected to the gate pad. Forming a gate shorting bar connected to the one; Dipping a substrate on which the gate wiring and the gate shorting bar are formed in an electrolytic solution and applying a voltage to electrodeposit metal on a portion of the gate pad adjacent to the gate wiring and the gate wiring; Depositing an insulating material on the entire surface of the substrate on which the gate wiring is formed to form a gate insulating film, which is a first insulating film; Sequentially depositing and patterning pure amorphous silicon and impurity amorphous silicon on the substrate on which the gate insulating film is formed, thereby forming an active layer and an ohmic contact layer planarly overlapping the gate wiring; A transparent electrode material is deposited on the entire surface of the substrate on which the active layer and the ohmic contact layer are formed, and then patterned by a second mask process to define a pixel area vertically crossing the gate wiring and include a data pad at one end. A data wiring including a source electrode formed to protrude above the gate wiring, a data shorting bar connected to the data pad to connect the plurality of data wirings to one, and one side protrudes above the gate electrode on the pixel region. Forming a pixel electrode extending from the source electrode and a drain electrode spaced a predetermined distance apart from the source electrode, and forming a pixel electrode extending on the other side of the gate wiring; Removing the exposed ohmic contact layer in a predetermined manner; Dipping a substrate on which the data line and the data shorting bar are formed in an electrolytic solution and applying a voltage to electrodeposit metal on a portion of the data pad close to the data line and the data line; Forming a protective film, which is a second insulating film, on the data and gate lines Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 8, The active layer and the ohmic contact layer are formed by applying a positive photoresist on the impurity amorphous silicon layer, back exposing the same, and then etching the remaining portions except the amorphous silicon and the ohmic contact layer on the gate wiring. Method for manufacturing array substrate for device. The method of claim 8, And the protective film is formed by applying a positive photoresist on the second insulating film, and then back-exposing to remove the second insulating film except for the gate wiring, the data wiring, and the thin film transistor. The method of claim 8, And the source electrode is configured to surround the drain electrode at a predetermined interval. The method of claim 8, And a portion of the pixel electrode overlaps the lower gate wiring with the first insulating film interposed therebetween to form a storage capacitor. The method according to claim 8 or 12, And removing the amorphous silicon exposed between the source electrode and the storage capacitor.