KR20120056766A - Method for Manufacturing Thin Film Transistor and Electrode Substrate Used in Display Device - Google Patents

Abstract

The present invention has a bottom contact structure, which can be mass-produced in a self-aligned TAOS TFT without requiring a large investment of equipment or securing a place for depositing a film forming apparatus, and the production of an electrode substrate for a display device using the TAOS TFT. By providing a method, the method of manufacturing a TFT of the present invention includes the steps of forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, and overlapping the gate electrode on the gate insulating film. And forming a source electrode and a drain electrode, respectively, on the gate electrode, the source electrode, and the drain electrode, so as to connect the source electrode and the drain electrode with the gate electrode interposed therebetween. And a step of irradiating nitrogen plasma onto the transparent amorphous oxide semiconductor layer. And annealing the transparent amorphous oxide semiconductor layer in a nitrogen atmosphere, forming a island-like insulating film on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask, and the substrate. And irradiating a plasma from the island-like insulating film side using the island-like insulating film as a mask on the entire surface.

Description

Method for manufacturing thin film transistor and electrode substrate for display device {Method for Manufacturing Thin Film Transistor and Electrode Substrate Used in Display Device}

The present invention relates to a thin film transistor (TFT) using a transparent amorphous oxide semiconductor (TAOS) and a method of manufacturing an electrode substrate for a display device using a thin film transistor (TFT).

Conventionally, as the thin film transistor (TFT), a bottom gate and a top contact structure called a B / C type have been widely used. In recent years, it has been proposed to use a transparent amorphous oxide semiconductor (TAOS) as a semiconductor layer of a TFT (see Patent Document 1, for example). Here, when TAOS is used for TFT, development is progressing in mind that a semiconductor layer will replace conventional amorphous silicon (a-Si: amorphous silicon) with TAOS.

Patent Document 1: Japanese Patent Application Laid-Open No. 2000-150900.

However, the above conventional technology has the following problems.

In a conventional top contact TFT, when using TAOS (Transparent Amorphous Oxide Semiconductor) as a semiconductor layer, a metal layer serving as a source electrode and a drain electrode is located directly above the TAOS layer. It consists of In addition, IGZO (an oxide containing In, Ga, and Zn), which is likely to be commercialized in TAOS materials, has low chemical resistance against acids and alkalis, and is easy to obtain plasma damage.

Therefore, when patterning the source electrode and the drain electrode, TAOS having less chemical resistance is likely to receive process damage. That is, since damage is small with respect to a process, it is easy to produce the fall of TFT characteristic, or the fall of a yield. Therefore, it is preferable that the TFT (TAOS TFT) using TAOS has a bottom contact structure in which a TAOS layer is formed after the source electrode and the drain electrode are patterned.

In addition, in the conventional TFT (a-Si TFT) using a TFT using a-Si (amorphous silicon), in order to reduce the influence of the parasitic capacitance of the TFT due to the alignment error, the influence due to the alignment error is small. U] shape. However, the TAOS TFT has a mobility 10 times or more that of the a-Si TFT, and when the shape is [U], the size of the TFT exceeds the required value.

If the TFT is larger than the required size, the parasitic capacitance of the TFT causes the influence on the image quality to increase rapidly, and the TFT cannot be made into a [U] shape. Therefore, the TAOS TFT must take a straight shape in which the parasitic capacitance fluctuation due to the alignment error is likely to occur, and inevitably, the degradation of the image quality due to the alignment error is more likely to occur than the conventional a-Si TFT.

In addition, in the case of using a TAOS having a conventional top contact structure, by positioning the source electrode and the drain electrode with respect to the gate, the parasitic capacitance of the TFT having only an alignment error margin is increased, and the alignment error is increased. As a result, the parasitic capacitance in the display screen becomes uneven.

Here, in the liquid crystal display device, there is an i / s type self-aligned (self-aligned type) TFT using backside exposure by ultraviolet rays as a method of reducing the parasitic capacitance of the TFT in order to improve the aperture ratio and the image quality. Therefore, in order to reduce parasitic capacitance and to improve aperture ratio and image quality, it is preferable to make TAOS TFT self-aligned.

However, when the TAOS TFT has a bottom contact structure, the metal layers serving as the source electrode and the drain electrode have light shielding properties, and the TFT cannot be self-aligned. When the TAOS TFT is self-aligned by backside exposure, the metal layers serving as the source electrode and the drain electrode cannot be disposed so as to overlap the gate electrode.

That is, in the TAOS TFT, the self-alignment by the bottom contact structure and the backside exposure is a light shielding property of the metal layer serving as the source electrode and the drain electrode, and cannot be realized without matching with each other. Accordingly, in order to obtain a self-aligned TAOS TFT with a bottom contact structure, the following method is considered.

That is, first, a gate electrode is formed on a substrate, a gate insulating film is formed on the gate electrode, and a source electrode and a drain electrode are formed on the gate insulating film so as not to overlap with the gate electrode, respectively, and the gate electrode, the source electrode, and On the drain electrode, a TAOS layer is formed to connect the source electrode and the drain electrode with the gate electrode interposed therebetween.

Subsequently, an island insulation film is formed on the TAOS layer by exposure from the substrate side using the gate electrode as a mask, and plasma is irradiated from the island insulation film side with the island insulation film as a mask on the entire surface of the substrate. As a result, the region to which the plasma of the TAOS layer is irradiated (the region not masked by the island insulating film) is reduced in resistance, and the TAOS layer is divided into a source electrode, a drain region and a channel region. Therefore, a TAOS TFT having a bottom contact structure and a self-aligned structure is obtained.

At this time, SiNx, SiOx, or SiOxNy of silicon oxide or silicon nitride, which has conventionally been used as a channel protective film, is considered as a material of the island-like insulating film. In other words, when silicon oxide-based or silicon nitride-based SiNx, SiOx or SiOxNy is used as the material of the island-like insulating film, CVD or sputtering is used as the film forming apparatus.

Therefore, in the conventional LCD (Liquid Crystal Display) manufacturing line of a-Si TFT, in order to mass-produce TAOS TFTs having an island-like insulating film without a decrease in production, large-scale equipment investment and film formation to add CVD or sputtering It is necessary to secure the place of installation of the device. Therefore, in order to solve the problem of facility investment and the like, it is preferable to use a resin material which can be coated as a material of the island insulation film.

Here, the post bake temperature of the resin insulating film varies depending on the material and is in the range of about 150 to 250 ° C. This temperature is much lower than the temperature of the annealing performed to bring the resistance of the TAOS layer to a value suitable for the channel region. For example, after the TAOS layer performs IGZO annealing, it is necessary to form an island insulating film which is a resin insulating film.

However, when the TAOS layer after annealing is heated again to the post-baking temperature of the resin insulating film, the resistance value of the TAOS layer is reduced by two orders of magnitude (10 to 100) times. Therefore, there is a problem that the manufactured TAOS TFT becomes a depletion mode in which it is normally-ON and cannot be used as a charge-holding LCD pixel TFT.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a bottom contact structure and a manufacturing method capable of mass-producing a self-aligned TAOS TFT without using large-scale equipment investment or securing a place for a film deposition apparatus. And a method of manufacturing an electrode substrate for a display device using the TAOS TFT.

A TFT manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate electrode on a substrate, forming a gate insulating film on the gate electrode, and on the gate insulating film, the gate electrode Forming a source electrode and a drain electrode so as not to overlap with each other; and a transparent amorphous oxide such that the source electrode and the drain electrode are connected to each other with the gate electrode interposed on the gate electrode, the source electrode, and the drain electrode. Forming a semiconductor layer, irradiating a nitrogen plasma on the transparent amorphous oxide semiconductor layer, annealing the transparent amorphous oxide semiconductor layer in a nitrogen atmosphere, and on the transparent amorphous oxide semiconductor layer, the gate Island-shaped cutting by exposure from the substrate side using an electrode as a mask In step and the front surface of the substrate to form a film, and the seomsang insulating film as a mask, and a step of irradiating plasma from the seomsang insulating film side.

The manufacturing method of the TFT of the present invention as described above has the following effects.

According to the manufacturing method of TFT of this invention, after forming a transparent amorphous oxide semiconductor layer, nitrogen plasma is irradiated to a transparent amorphous oxide semiconductor layer, and a transparent amorphous oxide semiconductor layer is then annealed in nitrogen atmosphere. As a result, when the resistance of the transparent amorphous oxide semiconductor layer rises and the annealing transparent amorphous oxide semiconductor layer is heated again to the post-baking temperature of the island-like insulating film, the resistance of the transparent amorphous oxide semiconductor layer is adjusted to a value suitable for the channel region. can do.

Therefore, the manufacturing method which can mass-produce the self-aligned TAOS TFT in a bottom contact structure without requiring large-scale investment and installation place of film-forming apparatus, and manufacture of the electrode substrate for display devices using TAOS TFT. You can get a way.

1 is a cross-sectional view showing a configuration of a TAOS TFT according to Embodiment 1 of the present invention.
2 is an explanatory diagram showing a resistance value of a TAOS layer of a TAOS TFT according to Embodiment 1 of the present invention;

EMBODIMENT OF THE INVENTION Hereinafter, although the figure which concerns on preferred embodiment of TFT of this invention and the electrode substrate for a display apparatus of this invention is described with reference to attached drawing, in FIG. .

The manufacturing method of the TFT and the electrode substrate for a display device of this invention is demonstrated in detail as follows.

Embodiment 1

1 is a cross-sectional view showing the configuration of a TAOS TFT according to Embodiment 1 of the present invention.

In FIG. 1, the TAOS TFT includes a glass substrate 11, a gate electrode 12, a gate insulating film 13, a source electrode 14, a drain electrode 15, and a first TAOS layer 16. 16: 16a, 16b, and 16c are collectively referred to) (transparent amorphous oxide semiconductor layer), second TAOS layer 17 (17: 17a, 17b, and 17c are collectively referred to) (transparent amorphous oxide semiconductor layer), and island phase The insulating film 18 and the resin insulating film 19 are provided.

The gate electrode 12 is formed on the glass substrate 11. The substrate is not limited to the glass substrate 11, and any substrate may be used as long as it is transparent and has insulation. The gate insulating film 13 is formed on the gate electrode 12. The source electrode 14 and the drain electrode 15 are formed on the gate insulating film 13 so as not to overlap with the gate electrode 12, respectively.

In the first TAOS layer 16, the source electrode 14 and the drain electrode 15 are disposed on the gate electrode 12, the source electrode 14, and the drain electrode 15 with the gate electrode 12 interposed therebetween. TAOS layer formed to connect. Here, as the material, the first TAOS layer 16 and the second TAOS layer 17 use IGZO, which is an oxide containing In, Ga, and Zn described above.

The 2nd TAOS layer 17 is laminated | stacked on the 1st TAOS layer 16, and is formed continuously, Furthermore, the gate electrode 12 on the gate electrode 12, the source electrode 14, and the drain electrode 15 is carried out. The TAOS layer is formed so as to connect the source electrode 14 and the drain electrode 15 with each other). Here, the second TAOS layer 17 is formed under a deposition condition different from the first TAOS layer 16 (to be described later), and the first TAOS layer 16 and the second TAOS layer 17 are formed as follows. It is composed of a laminated structure.

The island-like insulating film 18 is an insulating film formed on the second TAOS layer 17 by exposure (backside exposure) from the glass substrate 11 side using the gate electrode 12 as a mask. The resin insulating film 19 is formed on the second TAOS layer 17 and the island-like insulating film 18.

Here, the resistance values of the regions of the first TAOS layer 16 and the second TAOS layer 17 that do not overlap with the island-like insulating film 18 are determined by the plasma processing described later. The resistance is lower than the resistance value. Specifically, the first TAOS layer 16 includes a source region 16a serving as a source, a drain region 16b serving as a drain, and a channel region 16c.

As described later, the second TAOS layer 17 has a large O ₂ content, which is further insulated even by plasma treatment, and has a source protection region 17a and a drain region 16b that protect the source region 16a. ) And a drain protection region 17b and a channel protection region 17c.

At this time, the channel region 16c and the channel protection region 17c of the first TAOS layer 16 and the second TAOS layer 17 are self-aligned with respect to the gate electrode 12 as described later. And between the source region 16a and the source protective region 17a and the drain region 16b and the drain protective region 17b.

In addition to the TAOS TFT 10, the electrode substrate for display device using the TAOS TFT 10 includes a plurality of scanning signal lines (not shown) on the transparent insulating substrate formed on the glass substrate 11, A plurality of display signal lines (not shown) formed so as to intersect the plurality of scan signal lines via an insulating film, and a plurality of TAOS TFTs 10 in each intersection region of the plurality of scan signal lines and the plurality of display signal lines; It further comprises a plurality of display pixel electrodes (not shown) electrically connected.

In this electrode substrate for display device, the gate electrode 12 is formed from a part or an extension of the scan signal line, and the source electrode 14 and the drain electrode 15 are formed by the same process as the display signal line. do.

Next, the manufacturing method of the TAOS TFT 10 will be described in order.

First, the gate electrode 12 is formed on the glass substrate 11. Here, the gate electrode 12 is formed by, for example, patterning a metal layer formed by sputtering.

Subsequently, a gate insulating layer 13 is formed on the gate electrode 12. Here, the gate insulating film 13 is formed by, for example, a CVD method.

Subsequently, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 13 so as not to overlap the gate electrode 12. Here, the source electrode 14 and the drain electrode 15 are formed by patterning the metal layer formed by sputtering, for example.

Next, the source electrode 14 and the drain electrode 15 are connected to the gate electrode 12, the source electrode 14, and the drain electrode 15 with the gate electrode 12 interposed therebetween. First TAOS layer (transparent amorphous oxide semiconductor layer) 16 is formed. Here, the 1 TAOS layer 16, at least a mixed gas containing Ar and O _2, is formed by sputtering.

Subsequently, the source electrode 14 is disposed on the first TAOS 16 and successively stacked on the gate electrode 12, the source electrode 14, and the drain electrode 15 with the gate electrode 12 interposed therebetween. ) And the drain electrode 15 are formed to form a second TAOS layer 17. Here, the 2 TAOS layer 17, at least a mixed gas containing Ar and O _2, is formed by sputtering.

At this time, the 1 TAOS layer 16 is, for example, is deposited to a flow ratio of O ₂ to the flow rate of the mixed gas of 1%, the 2 TAOS layer 17 is, for example, the mixed The film is formed by setting the flow rate ratio of O _{2 to} the flow rate of gas to 33%.

Next, nitrogen (N ₂ ) plasma is irradiated to the first TAOS layer 16 and the second TAOS 17. At this time, the irradiation conditions of the nitrogen plasma are, for example, back pressure = 20 Pa, power = 100 W, N ₂ flow rate = 50 sccm, irradiation time = 60 s. However, the irradiation conditions of nitrogen plasma are not limited to these and may be other conditions.

The first TAOS layer 16 and the second TAOS layer 17 are then annealed (flowing N ₂ ) in a nitrogen (N ₂ ) atmosphere. Under the present circumstances, nitrogen annealing conditions shall be temperature = 350 degreeC, N2 flow volume = 51 / m, and annealing time = 3h. The nitrogen annealing condition is not limited to this, and other conditions may be used.

Here, nitrogen plasma irradiation and nitrogen annealing of the first TAOS layer 16 and the second TAOS layer 17 are performed by the first bake layer 16 and the second by post-baking of the island-like insulating film 18 described later. Since the resistance of the TAOS layer 17 is reduced by about 10 to 100 times, the objective is to increase the resistance of the first TAOS layer 16 and the second TAOS layer 17 by about 10 to 100 times. Will be.

In general, the resistivity of the TAOS layer is determined by the carrier density, and the carrier density is determined by the oxygen vacancy density. Here, the TAOS layer is an ionic crystal, and the oxygen vacancy density is determined by the balance of oxygen release by heat of annealing and oxygen trapping by thermal oxidation.

Therefore, in order to increase the resistance value of the TAOS layer, it is effective to trap nitrogen in the TAOS layer, which has a covalent bond, which is stronger than the ionic bond. In addition, experiments have found that the increase in the resistance of the TAOS layer is small only by nitrogen annealing, and the resistance of the TAOS layer can be further increased by irradiating nitrogen plasma to the TAOS layer before the nitrogen annealing.

Next, the island-like insulating film 18 is formed on the 2nd TAOS layer 17 by exposure from the said glass substrate 11 side which used the said gate electrode 12 as a mask. Here, as a material of the island-like insulating film 18, the resin material which can be formed into a film is used. That is, the island-like insulating film 18 is post-baked at 150-250 degreeC after a coating film. For example, the island-like insulating film 18 is coated with a positive resin material on the entire surface of the substrate including the second TAOS layer 17, and then the lower surface of the glass substrate 11 is formed using the gate electrode 12 as a mask. It exposes and can form only the part which is not exposed.

Subsequently, plasma is irradiated from the island-like insulating film 18 side using the island-like insulating film 18 as a mask on the entire surface of the glass substrate 11. At this time, the glass substrate 11 is irradiated with a plasma to ionize a gas containing at least one of O ₂ , N ₂ , CF ₄ , CHF ₃ and Ar. When the plasma is irradiated to the first TAOS layer 16 and the second TAOS 17, oxygen atoms in the TAOS layer IGZO emerge and oxygen vacancies increase, and the property becomes closer to the conductor layer.

As a result, the source region 16a, the source protective region 17a, the drain region 16b, and the drain protective region 17b of the first TAOS layer 16 and the second TAOS layer 17 are reduced in resistance, The conductivity of the source region 16a and the drain region 16b can be used as an electrode. Next, on the second TAOS layer 17 and the island-like insulating film 18, a resin insulating film 19 is formed of a resin material.

In addition to the manufacturing method of the TAOS TFT 10, the manufacturing method of the electrode substrate for display devices using the TAOS TFT 1 is provided with the following procedures. That is, forming a plurality of scan signal lines (not shown) on the transparent insulating substrate formed on the glass substrate 11 and a plurality of display signal lines (not shown) so as to intersect the plurality of scan signal lines through an insulating film. And a plurality of display pixel electrodes (not shown) electrically connected to the plurality of TAOS TFTs 10 at respective intersection regions of the plurality of scan signal lines and the plurality of display signal lines. It further comprises the step of.

In the method of manufacturing an electrode substrate for a display device according to the present invention, the gate electrode 12 is formed simultaneously with forming a plurality of scan signal lines, and the source electrode 14 and the drain electrode 15 are And simultaneously forming the plurality of display signal lines.

Here, in the 1st TAOS layer 16 of TAOS TFT 10, the resistance value after nitrogen plasma irradiation and nitrogen annealing is shown in FIG. In FIG. 2, there is shown a second resistance value point (N ₂ plasma) shows a resistance value after nitrogen plasma irradiation, and the third point _{(350 ℃ / 3h with N 2} ) after a nitrogen annealing of from left to right.

As shown in FIG. 2, it can be seen that the resistance of the first TAOS layer 16 after the nitrogen plasma irradiation and the nitrogen annealing increases by about 10 to 100 times as compared with the nitrogen plasma irradiation and the nitrogen annealing. Moreover, although resistance value falls once by nitrogen plasma irradiation, resistance value after nitrogen annealing becomes higher than when nitrogen annealing is performed without performing nitrogen plasma irradiation.

As described above, in Embodiment 1, since the apparatus price is high, the resin insulating film which can be formed into a film can be formed without using CVD (Chemical Vapor Deposition) or Sputter, which causes the lowest productivity. It can be used as the insulating film 18. As a result, in the conventional LCD manufacturing line of a-Si TFT, when mass-producing TAOS TFT which has the formation process of the island insulation film 18 which does not exist in the manufacturing process of a-Si TFT, when CVD and sputter | spatter are added further, It can be done easily without enormous capital investment.

As described above, according to the TFT manufacturing method according to the first embodiment, after the transparent amorphous oxide semiconductor layer is formed, nitrogen plasma is irradiated to the transparent amorphous oxide semiconductor layer, and then the transparent amorphous oxide semiconductor layer is subjected to nitrogen atmosphere. To anneal. As a result, when the resistance of the transparent amorphous oxide semiconductor layer rises and the annealing transparent amorphous oxide semiconductor layer is heated again to the post-baking temperature of the island-like insulating film, the resistance of the transparent amorphous oxide semiconductor layer is adjusted to a value suitable for the channel region. can do.

Therefore, a manufacturing method capable of mass-producing a self-aligned TAOS TFT with a bottom contact structure without requiring a large investment of equipment or securing a place for a film deposition apparatus, and a manufacturing method of an electrode substrate for a display device using the TAOS TFT You can get it.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

11: glass substrate 12: gate electrode
13: gate insulating film 14: source electrode
15: drain electrode 16: first TAOS layer
16a: source region 16b: drain region
16c: channel region 17: second TAOS layer
17a: source protection area 17b: drain protection area
17c: channel protection region 18: island insulation film
19: resin insulating film

Claims (5)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a source electrode and a drain electrode on the gate insulating film so as not to overlap the gate electrode;
Forming a transparent amorphous oxide semiconductor layer on the gate electrode, the source electrode and the drain electrode so as to connect the source electrode and the drain electrode with the gate electrode interposed therebetween;
Irradiating nitrogen plasma on the transparent amorphous oxide semiconductor layer;
Annealing the transparent amorphous oxide semiconductor layer in a nitrogen atmosphere;
Forming an island insulating film on the transparent amorphous oxide semiconductor layer by exposure from the substrate side using the gate electrode as a mask; and
And irradiating a plasma from the island-like insulating film side with the island-like insulating film as a mask on the entire surface of the substrate. The method of claim 1,
The step of forming the transparent amorphous oxide semiconductor layer,
And forming a laminated structure by successively forming two or more transparent amorphous oxide semiconductor layers having different film forming conditions. The method of claim 2,
The step of forming the transparent amorphous oxide semiconductor layer,
A step of forming a transparent amorphous oxide semiconductor layer by sputtering using a mixed gas containing at least Ar and O ₂ ,
At the time of forming the lowermost layer of the laminated structure, the flow rate ratio of O _{2 to} the flow rate of the mixed gas is 5% or less,
In forming the uppermost layer of the laminated structure, the flow rate ratio of O _{2 to} the flow rate of the mixed gas is 20% or more. 4. The method according to any one of claims 1 to 3,
The step of irradiating the plasma,
A method of manufacturing a thin film transistor, comprising irradiating a plasma to ionize a gas containing at least one of O ₂ , N ₂ , CF ₄ , CHF ₃ , and Ar. In the manufacturing method of the electrode substrate for display apparatuses using the manufacturing method of the thin film transistor as described in any one of Claims 1-4.
Forming a plurality of scan signal lines on the transparent insulating substrate;
Forming a plurality of display signal lines to intersect the plurality of scan signal lines via an insulating film;
Forming a plurality of display pixel electrodes so as to be electrically connected to the plurality of thin film transistors formed at respective intersections of the plurality of scan signal lines and the plurality of display signal lines;
The step of forming the gate electrode and the step of forming the plurality of scan signal lines are the same step,
And the step of forming the source electrode and the drain electrode and the step of forming the plurality of display signal lines are the same step.

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