KR20110049090A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to reduce the amount of leaked currents, thereby enhancing on/off properties of a transistor. CONSTITUTION: A gate pattern(340) is formed on a semiconductor substrate(300). A first recess is formed by etching the semiconductor substrate exposed between gate patterns. An insulating film is formed on the first recess. The insulating film and the first recess are etched to form a second recess. A contact(400) is formed by burying a conductive material on the frontal surface including the second recess.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, in the formation of a fin type gate, a method of manufacturing a semiconductor device improving the on / off characteristics of a transistor by increasing a current by increasing a channel region and reducing current leakage. Is about technology.

In general, semiconductor memory devices are devices that store information such as data and program instructions, and are largely divided into DRAMs and SRAMs. Here, DRAM (DRAM) is a memory that can read stored information and store other information, and can read and write information, but periodically during a period of time when power is supplied. If you do not rewrite the memory, the memory will be lost. As described above, DRAM needs to continue refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the density can be increased.

Here, a metal-oxide semiconductor field effect transistor (hereinafter, abbreviated as "MOSFET"), which is mainly used for a memory such as DRAM, logic, or the like, is a gate oxide film or polysilicon on a semiconductor substrate. After depositing a film, a gate metal, and a gate hard mask layer, the gate is stacked by a mask / etch process to form a channel.

When the size of a semiconductor device having a general structure is reduced, the length of the channel is shortened. As the channel length of the device becomes shorter, short channel effects and gate induced drain leakage (GIDL) characteristics become worse, and the gate channel length needs to be increased to improve it, and the gate resistance increases due to the increased gate channel length. There is a problem.

1 and 2 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

1 and 2, a gate pattern 140 is formed on a semiconductor substrate 100 in which an active region and an isolation layer are defined. In this case, the gate pattern 140 includes a gate insulating layer 110, a gate conductive layer 120, and a gate hard mask layer 130. Herein, the fin-shaped active region 150 of the active regions is illustrated by a dotted line.

Next, the semiconductor substrate 100 exposed between the gate patterns 140 is etched, and then an ion implantation process is performed to form the source / drain regions 160. In this case, since the region 170 in which the semiconductor substrate 100 is etched has a shallow depth, there is a limit to increasing the current (Current, 180) between the source / drain regions 260.

On the other hand, as shown in FIG. 2, the semiconductor substrate 200 exposed between the gate patterns 240 is deeply etched to increase the current 280 between the source / drain regions 260, and then ion implantation is performed. When the / drain region 260 is formed, since the etched region 270 of the semiconductor substrate 200 has a deep depth, the current 280 between the source / drain regions 260 increases, but the source / drain As the area of the region 260 increases, there is a problem that is very weak in the punch through phenomenon.

In order to solve the above-mentioned conventional problems, the present invention forms a source / drain region at the bottom of the recess (middle height of the fin-type active region), whereby the fin active region can be used as a wider channel. Since the current flow in the fin active region is increased and current leakage is reduced, the transistor on / off characteristic can be improved, and a method of manufacturing a semiconductor device capable of preventing punch-through is provided. .

The present invention provides a method of forming a gate pattern on a semiconductor substrate, forming a first recess by etching the exposed semiconductor substrate between the gate patterns, and forming an insulating layer on the first recess. And etching the insulating layer and the first recess to form a second recess, and forming a contact by embedding a conductive material on the entire surface including the second recess.

Preferably, after the forming of the first recess, an ion implantation process is performed to form a source / drain region.

Preferably, the source / drain region is formed under the first recess.

Preferably, the insulating film is formed using a group selected from SiO 2, Si 3 N 4, SiON, and combinations thereof.

Preferably, after the forming of the second recess, the method may further include performing an ion implantation process or further depositing a barrier metal.

Preferably, the conductive material is characterized in that using metal (Metal) or doped silicon (Si).

Preferably, the gate pattern may include a gate pattern shape having a fin, a saddle fin, or a multi shape.

Preferably, when forming the second recess, the insulating film remains on the sidewall of the first recess.

According to the present invention, the source / drain regions are formed in the lower portion of the recess (middle height of the fin type active region), so that the fin active region can be used as a wider channel, thereby increasing the current flow in the fin active region and increasing the current. Since leakage can be reduced, transistor on / off characteristics can be improved and punch-through can be prevented.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, a gate pattern 340 is formed on a semiconductor substrate 300 in which an active region and an isolation layer are defined. The gate pattern 340 includes a gate insulating layer 310, a gate conductive layer 320, and a gate hard mask layer 330. At this time, the active region 350 having a fin shape among the active regions is illustrated by a dotted line.

3B and 3C, the semiconductor substrate 300 exposed between the gate patterns 340 is etched to form a first recess 360. Thereafter, an ion implantation process is performed in the first recess 360 to form a source / drain region 370. In this case, the source / drain region 370 may be formed under the first recess 360.

Referring to FIG. 3D, an insulating film 380 is formed on the first recess 360. In this case, the insulating film 380 is preferably formed using a group selected from SiO ₂ , Si ₃ N ₄ , SiON, and combinations thereof.

Referring to FIG. 3E, the insulating layer 380 and the first recess 360 are further etched to form a second recess 390. Here, when forming the second recess 390, a spacer 385 is formed on the sidewall of the first recess 360. In this case, after the forming of the second recess 390, an ion implantation process may be additionally performed or a process of depositing a barrier metal may be further performed. Here, the region etched to form the second recess 390 has a depth of about 'A' as shown. This depth allows formation of a narrow but deeply formed junction.

Referring to FIG. 3F, a contact 400 is formed by filling a conductive material on the entire surface including the second recess 390. In this case, it is preferable to use metal or doped silicon (Si) as the conductive material.

As described above, the present invention forms a source / drain region below the recess (middle height of the fin-type active region), whereby the fin active region can be used as a wider channel so that the current of the fin active region can be used. Increased flow and reduced current leakage can improve transistor on / off characteristics and prevent punch-through.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 and 2 are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (8)

Forming a gate pattern on the semiconductor substrate; Etching the exposed semiconductor substrate between the gate patterns to form a first recess; Forming an insulating film on the first recess; Further etching the insulating film and the first recess to form a second recess; And And forming a contact by filling a conductive material on the entire surface including the second recess. The method of claim 1, And forming a source / drain region by performing an ion implantation process after the forming of the first recess. The method of claim 2, The source / drain region is formed under the first recess. The method of claim 1, The insulating film is a method of manufacturing a semiconductor device, characterized in that formed using a group selected from SiO ₂ , Si ₃ N ₄ , SiON and combinations thereof. The method of claim 1, And after the forming of the second recess, further performing an ion implantation process or further depositing a barrier metal. The method of claim 1, The conductive material is a method of manufacturing a semiconductor device, characterized in that using metal (Metal) or doped silicon (Si). The method of claim 1, The gate pattern may include a fin pattern, a saddle fin, or a multi-gate pattern. The method of claim 1, And when forming the second recess, the insulating film remains on the sidewall of the first recess.

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