CN112652622B - Semiconductor memory, semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor memory, semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN112652622B CN112652622B CN201910955273.4A CN201910955273A CN112652622B CN 112652622 B CN112652622 B CN 112652622B CN 201910955273 A CN201910955273 A CN 201910955273A CN 112652622 B CN112652622 B CN 112652622B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
本公开涉及存储器技术领域，关于一种半导体结构、半导体结构的制造方法及半导体存储器。该半导体结构包括：衬底、隔离结构、字线沟槽及字线，隔离结构形成于所述衬底中，并在所述衬底中界定出多个有源区；字线沟槽形成于所述衬底与所述隔离结构上；字线设于所述字线沟槽中，所述字线穿过所述有源区及所述隔离结构；其中，在所述字线沟槽的深度方向上，位于所述有源区上的所述字线的高度大于至少部分位于所述隔离结构上的所述字线的高度。本公开提供的半导体结构，能够降低工作状态时有源隔离区域的字线对于相邻有源区域的存储晶体管电性的影响，减少泄露电流。
The present disclosure relates to the field of memory technology, and is about a semiconductor structure, a method for manufacturing a semiconductor structure, and a semiconductor memory. The semiconductor structure includes: a substrate, an isolation structure, a word line groove, and a word line, wherein the isolation structure is formed in the substrate and defines a plurality of active areas in the substrate; the word line groove is formed on the substrate and the isolation structure; the word line is arranged in the word line groove, and the word line passes through the active area and the isolation structure; wherein, in the depth direction of the word line groove, the height of the word line located on the active area is greater than the height of the word line located at least partially on the isolation structure. The semiconductor structure provided by the present disclosure can reduce the influence of the word line in the active isolation area on the electrical properties of the storage transistor in the adjacent active area during the working state, and reduce the leakage current.
Description
Technical Field
The disclosure relates to the technical field of memories, and in particular relates to a semiconductor structure, a manufacturing method of the semiconductor structure and a semiconductor memory.
Background
With the increasing development of light, thin, short and small electronic products, the design of dynamic random access memory (Dynamic Random Access Memory, DRAM) devices must also meet the requirements of high integration and high density and the trend of miniaturization, so as to increase the integration of dynamic random access memory to speed up the operation speed of the devices, and meet the requirements of consumers for miniaturized electronic devices, and embedded gate word line dynamic random access memory has been developed in recent years to meet the above requirements.
However, as the array of the dynamic random access memory is continuously reduced, the word line resistance is gradually increased along with the reduction of the size of the device, which increases the access time of the device, and the low resistance of the device is usually realized by increasing the height of the word line, and the reliability of the memory device is greatly reduced by larger gate-induced drain leakage current, the refresh frequency of the memory device is increased, and the power consumption of the memory device is increased.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure, and a semiconductor memory device capable of reducing an influence of a word line of an active isolation region on an electrical property of a memory transistor of an adjacent active region in an operating state and reducing a leakage current.
According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:
A substrate;
The isolation structure is formed in the substrate and defines a plurality of active areas in the substrate;
A word line trench formed on the substrate and the isolation structure, and
A word line disposed in the word line trench, the word line passing through the active region and the isolation structure, wherein,
The height of the word line located on the active region is greater than the height of the word line located at least partially on the isolation structure in the depth direction of the word line trench.
In one exemplary embodiment of the present disclosure, the depth of the word line trench located on the active region is greater than the depth of the word line trench located at least partially on the isolation structure.
In one exemplary embodiment of the present disclosure, a height of a region on the isolation structure where a depth of the word line trench is less than a depth of the word line trench on the active region is 28nm to 32nm.
In one exemplary embodiment of the present disclosure, a width of the word line located on the isolation structure is greater than a width of the word line located on the active region in a width direction of the word line trench.
In an exemplary embodiment of the present disclosure, the width of the word line on the isolation structure is 20nm to 35nm in the width direction of the word line trench.
In one exemplary embodiment of the present disclosure, at least one of the active regions is provided with two of the word lines passing therethrough.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, the method comprising:
Providing a substrate;
forming an isolation structure in the substrate, the isolation structure defining a plurality of active regions in the substrate;
Forming word line trenches on the substrate and the isolation structures;
and forming a word line penetrating through the active region and the isolation structure in the word line groove, wherein the height of the word line positioned on the active region is larger than that of the word line positioned on the isolation structure at least partially in the depth direction of the word line groove.
In one exemplary embodiment of the present disclosure, forming a word line trench over the substrate and the isolation structure includes:
Etching the active region to form a first groove with a first preset depth;
etching the isolation structure, forming a second groove with a second preset depth in at least part of the area, wherein the first groove is communicated with the second groove to form the word line groove, and the first preset depth is larger than the second preset depth.
In an exemplary embodiment of the present disclosure, etching the isolation structure includes:
etching the isolation structure by isotropic etching;
and etching the isolation structure to the second preset depth by adopting anisotropic etching to form the second groove.
In one exemplary embodiment of the present disclosure, forming a word line in the word line trench through the active region and the isolation structure includes:
forming a gate oxide layer on an inner wall of the word line trench;
The word line is formed on the gate insulating layer.
According to yet another aspect of the present disclosure, there is provided a semiconductor memory comprising the semiconductor structure of any one of the above.
According to the semiconductor structure provided by the disclosure, in the depth direction of the word line groove, the height of the word line positioned on the active region is larger than that of the word line positioned on the isolation structure at least partially, so that the overlapping area of the word line positioned on the isolation structure and the word line positioned on the active region on the adjacent word line is reduced, the influence of the word line on the isolation structure on the electrical property of the memory transistor in the adjacent active region in the working state is reduced, the leakage current is reduced, the device refreshing time is prolonged, and the reliability of the semiconductor device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a top view of a semiconductor structure provided by an embodiment of the present disclosure;
Fig. 2 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIGS. 3-8 are process diagrams of a method of fabricating a semiconductor structure from the cross-section of the A-A plane of FIG. 1;
fig. 9 to 14 are process charts of a method of manufacturing a semiconductor structure in cross section from the B-B plane in fig. 1.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the aspects of the disclosure may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc., the terms "comprising" and "having" are intended to mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc., and the terms "first," "second," etc. are used merely as labels, and do not limit the number of its objects.
A semiconductor structure is first provided in this example embodiment. As shown in fig. 1, 8 and 14, the semiconductor structure comprises a substrate 10, an isolation structure 20, a word line trench 40 and a word line 30, wherein the isolation structure 20 is formed in the substrate 10 and defines a plurality of active regions 101 in the substrate 10, the word line trench 40 is formed on the substrate 10 and the isolation structure 20, the word line 30 is arranged in the word line trench 40, and the word line 30 passes through the active regions 101 and the isolation structure 20, wherein the height of the word line 30 on the active regions 101 is greater than the height of the word line 30 on the isolation structure 20 in the depth direction of the word line trench 40.
According to the semiconductor structure provided by the disclosure, in the depth direction of the word line groove 40, the height of the word line 30 on the active region 101 is larger than the height of the word line 30 at least partially on the isolation structure 20, so that the overlapping area of the word line 30 on the isolation structure 20 and the word line 30 on the active region 101 on the adjacent word line 30 can be reduced, the influence of the word line 30 on the isolation structure on the electrical property of a memory transistor in the adjacent active region 101 in the working state is reduced, the leakage current is reduced, the device refreshing time is prolonged, and the reliability of a semiconductor device is improved.
The substrate 10 is a semiconductor substrate, and the forming material of the substrate 10 includes, but is not limited to, a monocrystalline silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate is a monocrystalline substrate or a polycrystalline substrate, the semiconductor substrate may be an intrinsic silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The isolation structure 20 is made of an insulating material, the isolation structure 20 may be made of silicon nitride or silicon oxide, and the filling medium may be made of silicon nitride or silicon oxide. The word line 30 is a conductive material, and the conductive material forming the word line may include one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof.
Specifically, in the width direction of the word line trench 40, the width of the word line 30 located on the isolation structure 20 is larger than the width of the word line 30 located on the active region 101. The depth direction of the word line trench 40 is the height direction of the cross-sectional view shown in fig. 8, and the width direction of the word line trench 40 is the width direction of the cross-sectional view shown in fig. 8. By relatively increasing the width of the word line 30, the area of the cross section of the word line 30 can be increased, and then the resistance of the word line 30 on the isolation structure 20 can be reduced, so that the problem of increasing the resistance of the word line 30 due to the reduction of the height of the word line 30 on the isolation structure 20 is avoided, the reduction of the overlapping area of the word line 30 on the isolation structure 20 and the word line 30 on the active region on the adjacent word line 30 is ensured, and the resistance of the word line 30 is not relatively increased at the same time, thereby being beneficial to the starting speed of the transistor.
The width of the word line 30 on the isolation structure 20 is 20nm to 35nm in the width direction of the word line trench 40. For example, the width of the word line 30 on the isolation structure 20 may be 20nm, 22nm, 25nm, 27nm, 29nm, 30nm, 32nm, 35nm, etc., which are not illustrated herein. It can be seen that the width of the word line 30 on the isolation structure 20 provided by the present disclosure may reach 30nm, so that the width of the word line 30 is relatively increased greatly, and the area of the cross section of the word line 30 can be greatly increased, thereby ensuring that the resistance of the word line 30 on the isolation structure 20 is within a preset range.
Specifically, the depth of the word line trench 40 located on the active region 101 is greater than the depth of the word line trench 40 located at least partially on the isolation structure 20, as shown in fig. 14, the depth of the region of the word line trench on the isolation structure 20 adjacent to the active region 101 is greater than the depth of the word line trench on the active region 101. By making the depth of the word line trench 40 on the active region 101 greater than the depth of the word line trench 40 at least partially located on the isolation structure 20, when the word line 30 is formed in the trench by a deposition process or the like, the height of the word line 30 deposited on the active region 101 can be made greater than the height of the word line 30 deposited on the isolation structure 20, thereby enabling the overlapping area of the word line 30 located on the isolation structure 20 and the word line 30 located on the active region 101 on the adjacent word line 30 to be reduced, reducing the influence of the word line 30 on the isolation structure 20 on the memory transistor electrical properties of the adjacent active region 101 region in the operating state, and reducing the leakage current.
Further, as shown in fig. 14, the side of the word line 30 facing the opening of the word line trench 40 is a plane. By making the side of the word line 30 facing the opening of the word line trench 40 planar, the height of the overlapping region of the word line 30 located on the isolation structure 20 and the word line 30 located on the active region 101 on the adjacent word line 30 is the height of the word line 30 located on the isolation structure 20, so as to control the height of the overlapping region of the word line 30 located on the isolation structure 20 and the word line 30 located on the active region 101 on the adjacent word line 30, further ensure that the overlapping region is reduced, and reduce the influence of the word line 30 on the isolation structure on the memory transistor of the adjacent active region 101 in the operating state.
The depth of the word line trench on the isolation structure 20 is 28nm to 32nm, which is smaller than the depth of the word line trench on the active region 101. By setting the height of the isolation structure 20 under the word line trench 40 to 28nm to 32nm, the height of the isolation structure 20 under the word line trench 40 is increased, the depth of the word line trench 40 on the isolation structure 20 is relatively reduced, and the overlapping area of the word line 30 on the isolation structure 20 and the word line 30 on the active region 101 on the adjacent word line 30 is reduced.
As shown in fig. 1, at least one active region 101 is provided with two word lines 30 passing therethrough, and the isolation structure 20 may be a Shallow Trench Isolation (STI).
The present exemplary embodiment also provides a method for manufacturing a semiconductor structure, as shown in fig. 2, including:
Step S100, providing a substrate;
Step 200, forming an isolation structure in a substrate, wherein the isolation structure defines a plurality of active areas in the substrate;
Step S300, forming word line grooves on the substrate and the isolation structures;
Step S400, forming a word line penetrating through the active region and the isolation structure in the word line groove, wherein the height of the word line positioned on the active region is larger than that of the word line positioned on the isolation structure at least partially in the depth direction of the word line groove.
According to the manufacturing method of the semiconductor memory, the height of the word line positioned on the active area is larger than that of the word line positioned on the isolation structure at least partially in the depth direction of the word line groove, so that the overlapping area of the word line positioned on the isolation structure and the word line positioned on the active area on the adjacent word line can be reduced, the influence of the word line on the isolation structure on the electrical property of the memory transistor in the adjacent active area in the working state is reduced, the leakage current is reduced, the device refreshing time is prolonged, and the reliability of the semiconductor device is improved.
Next, each step of the method for manufacturing a semiconductor structure in this exemplary embodiment will be further described.
In step S100, a substrate is provided.
Specifically, as shown in fig. 3, a semiconductor substrate 10 is provided, and the material of the substrate includes, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and in addition, when the semiconductor substrate is a single crystal substrate or a polycrystalline substrate, it may be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
In step S200, an isolation structure is formed in a substrate, the isolation structure defining a plurality of active regions in the substrate.
Specifically, as shown in fig. 3 and 9, the semiconductor substrate is isolated by a shallow trench isolation technique (Shallow Trench Isolation, STI), shallow trench isolation trenches are formed in the semiconductor substrate, the depth of the shallow trench isolation trenches may be 28nm to 32nm, and then the isolation structures 20 are formed in the etched shallow trench isolation trenches by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD) or other deposition techniques. The plurality of active regions 101 isolated by the isolation structure 20 may be, but is not limited to, arranged in an array as shown in fig. 1. The material of the isolation structure 20 may include an insulating material such as silicon nitride or silicon oxide. As an example, a MOS device (not shown) is formed in the active region 101, and the MOS device includes a gate, a source, and a drain, the source and the drain being located on opposite sides of the gate, respectively.
In step S300, a word line trench is formed over the substrate and the isolation structure.
Specifically, step S310 and step S320 are included:
in step S310, the active region is etched to form a first trench having a first preset depth.
Specifically, as shown in fig. 4 and 10, a photoresist layer is formed on the upper surfaces of the substrate 10 and the isolation structure 20, then a pattern 70 of a word line is formed on the photoresist layer by exposure, then the active region 101 is etched by the patterned photoresist layer, and an etching solution corresponding to the material of the active region 101 is selected to avoid etching the isolation structure 20. Or the active region 101 is etched using an anisotropic dry etching process, and a first trench is formed on the active region 101.
In step S320, the isolation structure is etched, at least a part of the region is formed with a second trench with a second preset depth, and the first trench is communicated with the second trench to form a word line trench, wherein the first preset depth is greater than the second preset depth.
Specifically, as shown in fig. 5 and 11, the isolation structure 20 is etched by patterning a photoresist layer, and the isolation structure 20 is first etched by isotropic etching to form a wide opening on the isolation structure 20. The isolation structure 20 may be etched down by isotropic etching to about 10nm to form an opening with a width of 20nm to 35nm on the isolation structure 20.
Next, as shown in fig. 6, fig. 12 and fig. 14, the isolation structure 20 is etched down from the opening continuously by using anisotropic etching, and the isolation structure 20 may be etched down by using anisotropic etching to form a second trench with a second predetermined depth in at least a part of the region, as shown in fig. 14, where the depth of the word line trench on the isolation structure 20 near the active region 101 is greater than the depth of the word line trench on the active region 101. After the second trench is formed in the isolation structure 20 row, the second trench is communicated with the first trench to form the word line trench 40, and the first predetermined depth is greater than the second predetermined depth, that is, the depth of the first trench is greater than 100nm.
It should be clear to a person skilled in the art that the width of the isolation structure 20 should be larger than 32nm to ensure that after the second trench is formed on the isolation structure, the isolation structure material is still present between the inner wall of the second trench and the active region 101 to form an insulation of the second trench from the active region 101.
In step S400, a word line is formed in the word line trench through the active region and the isolation structure, such that a height of the word line located on the active region is greater than a height of the word line located at least partially on the isolation structure in a depth direction of the word line trench.
Specifically, step S410 and step S420 are included:
in step S410, a gate oxide layer is formed on the inner walls of the word line trenches.
Specifically, as shown in fig. 7 and 13, a chemical vapor deposition, physical vapor deposition or other deposition techniques may be used to form a gate oxide layer 50 on the inner wall of the word line trench 40, where the gate oxide layer 50 has a U-shape at the bottom portion of the word line trench 40, and the thickness of the gate oxide layer 50 may be 5nm to 6nm. Alternatively, a thermal oxidation process is used to oxidize a portion of the inner surface of the word line trench 40 to form a gate oxide layer 50 on the inner surface of the word line trench 40. The gate oxide layer 50 is made of a superbright material such as silicon dioxide.
In step S420, a word line is formed in the word line trench.
Specifically, as shown in fig. 8 and 14, the metal word line 30 may be formed on the gate oxide layer 50 on the inner surface of the word line trench 40 by a chemical vapor deposition method, a physical vapor deposition method, or other means. The conductive material forming the word line 30 may include one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof, and other conductive materials may be selected by those skilled in the art, which is not limited in this disclosure. Since the second trench is communicated with the first trench to form the word line trench 40, and the first preset depth is greater than the second preset depth, the height of the word line 30 located on the active region 101 is greater than the height of the word line 30 located at least partially on the isolation structure 20, so that the overlapping area of the word line 30 located on the isolation structure 20 and the word line 30 located on the active region 101 on the adjacent word line 30 can be reduced, the influence of the word line 30 on the isolation structure on the electrical property of the memory transistor in the adjacent active region 101 in the operating state is reduced, the leakage current is reduced, the device refresh time is increased, and the reliability of the semiconductor device is increased.
The method for manufacturing the semiconductor structure further comprises the step of forming a top protection layer.
Specifically, as shown in fig. 8 and 14, after forming the word line 30, a top protective layer 60 is then formed by using chemical vapor deposition, physical vapor deposition, or other deposition techniques, the top protective layer 60 completely covering the active region 101 of the substrate 10, the isolation structures 20, and the word line 30. The top protective layer 60 is an insulating oxide, such as silicon oxide or silicon carbide, and the application is not limited thereto.
It should be noted that although the steps of the methods in the present disclosure are depicted in the accompanying drawings in a particular order, this does not require or imply that the steps must be performed in that particular order, or that all illustrated steps be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
The semiconductor structure with the embedded gate line provided by the disclosure can be applied to, for example, a metal oxide semiconductor field effect Transistor (metal oxide semiconductor FIELD EFFECT Transistor, MOSFET), an insulated gate barrier bipolar Transistor (Insulated Gate Bipolar Transistor, IGBT), a Junction FIELD EFFECT Transistor (JFET), or the like. By reducing the overlapping area of the word line on the isolation structure and the word line on the active region on the adjacent word lines, the influence of the word line on the isolation structure on the electrical property of the memory transistor of the adjacent active region in the working state is reduced, the leakage current is reduced, the device refreshing time is improved, and the reliability of the semiconductor device is improved.
The present disclosure also provides a semiconductor memory including the above semiconductor structure. The semiconductor memory may be a computing memory (e.g., DRAM, SRAM, DDR SDRAM, DDR2SDRAM, DDRSDRAM, etc.), a consumer memory (e.g., DDR3SDRAM, DDR2SDRAM, DDRSDRAM, SDRSDRAM, etc.), a graphics memory (e.g., DDR3SDRAM, GDDR 3SDRA, GDDR4SDRAM, GDDR5SDRAM, etc.), a mobile memory, and the like. The beneficial effects thereof can be described with reference to the above semiconductor structure and will not be described herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
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