KR20090106822A - 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 - Google Patents
웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 Download PDFInfo
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- KR20090106822A KR20090106822A KR1020080032193A KR20080032193A KR20090106822A KR 20090106822 A KR20090106822 A KR 20090106822A KR 1020080032193 A KR1020080032193 A KR 1020080032193A KR 20080032193 A KR20080032193 A KR 20080032193A KR 20090106822 A KR20090106822 A KR 20090106822A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
- B32B2309/02—Temperature
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
- B32B2309/02—Temperature
- B32B2309/027—Ambient temperature
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
- B32B2309/12—Pressure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2310/00—Treatment by energy or chemical effects
- B32B2310/14—Corona, ionisation, electrical discharge, plasma treatment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/14—Semiconductor wafers
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/0008—Electrical discharge treatment, e.g. corona, plasma treatment; wave energy or particle radiation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Led Devices (AREA)
Abstract
Description
Claims (25)
- 도전성 웨이퍼와 다수의 절연성 웨이퍼를 제공하되, 상기 도전성 웨이퍼의 크기는 상기 절연성 웨이퍼의 크기보다 크고,상기 도전성 웨이퍼와 상기 절연성 웨이퍼 중 적어도 하나를 전처리(pre-treatment)하고,상기 도전성 웨이퍼와 상기 다수의 절연성 웨이퍼를 직접 본딩하는 것을 포함하는 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 전처리는 플라즈마 처리 또는 습식 처리인 웨이퍼 본딩 방법.
- 제 2항에 있어서,상기 플라즈마 처리는 O2, NH3, SF6, Ar, Cl2, CHF3, H2O 중 적어도 하나를 이용한 플라즈마 처리인 웨이퍼 본딩 방법.
- 제 2항에 있어서,상기 습식 처리는 H2SO4, HNO3, HCl, H2O2, H5IO6, SC-1, SC-2 중 적어도 하나를 이용한 습식 처리인 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 전처리를 한 웨이퍼의 본딩면에는 댕글링 본드(dangling bond)가 형성되는 웨이퍼 본딩 방법.
- 제 5항에 있어서,상기 댕글링 본드는 친수성(hydrophilic) 댕글링 본드 또는 소수성(hydrophobic) 댕글링 본드인 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 직접 본딩하는 것은, 상기 도전성 웨이퍼 상에 다수의 절연성 웨이퍼를 배치하고, 상기 도전성 웨이퍼와 상기 다수의 절연성 웨이퍼를 열처리하거나 물리적으로 압착하여 본딩하는 웨이퍼 본딩 방법.
- 제 7항에 있어서,상기 열처리하는 것은, 약 25℃에서 약 400℃에서 진행되는 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 도전성 웨이퍼의 본딩면(bonding surface)과 상기 절연성 웨이퍼의 본 딩면은 평평한 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 도전성 웨이퍼의 본딩면과, 상기 절연성 웨이퍼의 본딩면 중 적어도 하나에는 절연막이 형성되어 있는 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 전처리하기 전에 상기 도전성 웨이퍼의 본딩면과, 상기 절연성 웨이퍼의 본딩면 중 적어도 하나를 연마하는 것을 더 포함하는 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 전처리하기 전에 상기 도전성 웨이퍼와 상기 다수의 절연성 웨이퍼를 세정하는 것을 더 포함하는 웨이퍼 본딩 방법.
- 제 1항에 있어서,상기 도전성 웨이퍼는 실리콘 웨이퍼이고, 상기 절연성 웨이퍼는 사파이어 웨이퍼인 웨이퍼 본딩 방법.
- 도전성 웨이퍼와 다수의 절연성 웨이퍼를 제공하되, 상기 도전성 웨이퍼의 크기는 상기 절연성 웨이퍼의 크기보다 크고,상기 도전성 웨이퍼의 본딩면과 상기 절연성 웨이퍼의 본딩면 중 적어도 하나에 댕글링 본드를 형성하고,상기 도전성 웨이퍼의 본딩면과 상기 절연성 웨이퍼의 본딩면이 마주보도록, 상기 도전성 웨이퍼와 상기 다수의 절연성 웨이퍼를 직접 본딩하는 것을 포함하는 웨이퍼 본딩 방법.
- 제 14항에 있어서,상기 댕글링 본드를 형성하는 것은, 상기 도전성 웨이퍼와 상기 절연성 웨이퍼 중 적어도 하나를 플라즈마 처리 또는 습식 처리하는 웨이퍼 본딩 방법.
- 제 15항에 있어서,상기 플라즈마 처리는 O2, NH3, SF6, Ar, Cl2, CHF3, H2O 중 적어도 하나를 이용한 플라즈마 처리인 웨이퍼 본딩 방법.
- 제 15항에 있어서,상기 습식 처리는 H2SO4, HNO3, HCl, H2O2, H5IO6, SC-1, SC-2 중 적어도 하나를 이용한 습식 처리인 웨이퍼 본딩 방법.
- 제 14항에 있어서,상기 직접 본딩하는 것은, 상기 도전성 웨이퍼의 본딩면과 상기 절연성 웨이퍼의 본딩면이 마주보도록 배치하고, 상기 도전성 웨이퍼와 상기 다수의 절연성 웨이퍼를 열처리하거나 물리적으로 압착하여 본딩하는 웨이퍼 본딩 방법.
- 제 14항에 있어서,상기 도전성 웨이퍼의 본딩면과, 상기 절연성 웨이퍼의 본딩면 중 적어도 하나에는 절연막이 형성되어 있는 웨이퍼 본딩 방법.
- 제 14항에 있어서,상기 댕글링 본드를 형성하기 전에 상기 도전성 웨이퍼의 본딩면과, 상기 절연성 웨이퍼의 본딩면 중 적어도 하나를 연마하는 것을 더 포함하는 웨이퍼 본딩 방법.
- 제 14항에 있어서,상기 댕글링 본드를 형성하기 전에 상기 도전성 웨이퍼와 상기 다수의 절연성 웨이퍼를 세정하는 것을 더 포함하는 웨이퍼 본딩 방법.
- 제1 크기의 도전성 웨이퍼; 및상기 도전성 웨이퍼 상에 직접 본딩된 다수의 제2 크기의 절연성 웨이퍼를 포함하되, 상기 제1 크기는 상기 제2 크기보다 큰 웨이퍼 구조체.
- 제 22항에 있어서,상기 도전성 웨이퍼와 상기 절연성 웨이퍼는 산소 공유 결합을 통해서 연결된 본딩된 웨이퍼 구조체.
- 제 22항에 있어서,상기 도전성 웨이퍼와 상기 절연성 웨이퍼 사이에 절연막이 형성되어 있는 본딩된 웨이퍼 구조체.
- 제 22항에 있어서,상기 도전성 웨이퍼의 본딩면과 상기 절연성 웨이퍼의 본딩면은 평평한 웨이퍼 구조체.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080032193A KR20090106822A (ko) | 2008-04-07 | 2008-04-07 | 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 |
JP2009093014A JP2009253302A (ja) | 2008-04-07 | 2009-04-07 | ウェハ構造体およびウェハボンディング方法 |
US12/384,617 US8268699B2 (en) | 2008-04-07 | 2009-04-07 | Wafer structures and wafer bonding methods |
TW098111531A TW201001503A (en) | 2008-04-07 | 2009-04-07 | Wafer structures and wafer bonding methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080032193A KR20090106822A (ko) | 2008-04-07 | 2008-04-07 | 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 |
Publications (1)
Publication Number | Publication Date |
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KR20090106822A true KR20090106822A (ko) | 2009-10-12 |
Family
ID=41133544
Family Applications (1)
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KR1020080032193A Ceased KR20090106822A (ko) | 2008-04-07 | 2008-04-07 | 웨이퍼 본딩 방법 및 그 방법에 의해 본딩된 웨이퍼 구조체 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8268699B2 (ko) |
JP (1) | JP2009253302A (ko) |
KR (1) | KR20090106822A (ko) |
TW (1) | TW201001503A (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101331685B1 (ko) * | 2011-12-29 | 2013-11-20 | 삼성전기주식회사 | 관성센서 및 그 제조방법 |
US8722513B2 (en) | 2010-12-21 | 2014-05-13 | Korea Institute Of Machinery & Materials | Semiconductor chip stack package and manufacturing method thereof |
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KR101428719B1 (ko) * | 2008-05-22 | 2014-08-12 | 삼성전자 주식회사 | 발광 소자 및 발광 장치의 제조 방법, 상기 방법을이용하여 제조한 발광 소자 및 발광 장치 |
KR20120119845A (ko) * | 2011-04-22 | 2012-10-31 | 삼성전기주식회사 | 관성센서 및 그의 제조방법 |
JP5417399B2 (ja) * | 2011-09-15 | 2014-02-12 | 信越化学工業株式会社 | 複合ウェーハの製造方法 |
FR3000092B1 (fr) * | 2012-12-26 | 2015-01-16 | Commissariat Energie Atomique | Traitement de surface par plasma chlore dans un procede de collage |
US10707364B2 (en) | 2014-05-30 | 2020-07-07 | University Of Central Florida Research Foundation, Inc. | Solar cell with absorber substrate bonded between substrates |
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US9741620B2 (en) * | 2015-06-24 | 2017-08-22 | Invensas Corporation | Structures and methods for reliable packages |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
CN106571334B (zh) * | 2016-10-26 | 2020-11-10 | 上海集成电路研发中心有限公司 | 一种硅片间的混合键合方法 |
US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
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WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
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US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
US12080672B2 (en) | 2019-09-26 | 2024-09-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive |
US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
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JPH06232236A (ja) | 1991-08-20 | 1994-08-19 | Fujitsu Ltd | 半導体装置の製造方法 |
US5349207A (en) | 1993-02-22 | 1994-09-20 | Texas Instruments Incorporated | Silicon carbide wafer bonded to a silicon wafer |
US6248646B1 (en) | 1999-06-11 | 2001-06-19 | Robert S. Okojie | Discrete wafer array process |
US6814833B2 (en) * | 2001-10-26 | 2004-11-09 | Corning Incorporated | Direct bonding of articles containing silicon |
US6960490B2 (en) * | 2002-03-14 | 2005-11-01 | Epitactix Pty Ltd. | Method and resulting structure for manufacturing semiconductor substrates |
JP2007180273A (ja) * | 2005-12-28 | 2007-07-12 | Toyota Central Res & Dev Lab Inc | 半導体装置の製造方法 |
JP2007227415A (ja) * | 2006-02-21 | 2007-09-06 | Shin Etsu Chem Co Ltd | 貼り合わせ基板の製造方法および貼り合わせ基板 |
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2008
- 2008-04-07 KR KR1020080032193A patent/KR20090106822A/ko not_active Ceased
-
2009
- 2009-04-07 US US12/384,617 patent/US8268699B2/en not_active Expired - Fee Related
- 2009-04-07 TW TW098111531A patent/TW201001503A/zh unknown
- 2009-04-07 JP JP2009093014A patent/JP2009253302A/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8722513B2 (en) | 2010-12-21 | 2014-05-13 | Korea Institute Of Machinery & Materials | Semiconductor chip stack package and manufacturing method thereof |
KR101331685B1 (ko) * | 2011-12-29 | 2013-11-20 | 삼성전기주식회사 | 관성센서 및 그 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
US20090252939A1 (en) | 2009-10-08 |
US8268699B2 (en) | 2012-09-18 |
TW201001503A (en) | 2010-01-01 |
JP2009253302A (ja) | 2009-10-29 |
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