KR20090083200A - Variable Resistance Memory Device Reduces Rise in Word Line Voltage - Google Patents

Abstract

A variable resistance memory device according to the present invention includes a memory cell array having a plurality of block units and a plurality of word line drivers, each block unit being connected between neighboring word line drivers and configured to have a plurality of memory blocks; A sense amplifier circuit having a plurality of sense amplifier units, each sense amplifier unit configured to provide a read current to a corresponding block unit and have a plurality of sense amplifiers; And a column select circuit connected between the memory cell array and the sense amplifier circuit to select at least one memory block from the plurality of memory blocks in response to a column select signal, and to deliver the read current to the selected memory block. Include. According to the present invention, the increase in the word line voltage due to the parasitic resistance or the parasitic capacitor during the program operation or the read operation can be reduced.

Description

Variable resistance memory device reduces the rise of word line voltage {RESISTNACE VARIABLE MEMORY DEVICE REDUCING WORDLINE VOLTAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a variable resistance memory device which reduces a rise in a word line voltage during a program operation or a read operation.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Semiconductor memory devices can be roughly divided into random access memory (RAM) and read only memory (ROM). ROM is nonvolatile memory that does not lose its stored data even when its power source is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory Device. RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes Dynamic RAM (DRAM) and Static RAM (SRAM).

In addition, semiconductor memory devices that replace DRAM capacitors with nonvolatile materials are emerging. Variable resistance memory devices using ferroelectric RAM (FRAM) using ferroelectric capacitors, magnetic RAM (MRAM) using tunneling magneto-resistive (TMR) films, and chalcogenide alloys change memory device). In particular, the variable resistance memory device is a nonvolatile memory device using a phase resistance, that is, a resistance change according to a temperature change. The variable resistance memory device has a relatively simple manufacturing process and can implement a large capacity memory at low cost.

1 shows a memory cell of a variable resistance memory device. Referring to FIG. 1, the memory cell 10 includes a memory element 11 and a select element 12. The memory element 11 is connected between the bit line BL and the selection element 12, and the selection element 12 is connected between the memory element 11 and the ground.

The memory element 11 includes a variable resistance material GST. The variable resistive material GST is a variable resistive element whose resistance varies with temperature, such as Ge-Sb-Te. The variable resistance material GST has one of two stable states, that is, a crystal state and an amorphous state, depending on the temperature. The variable resistance material GST changes into a crystal state or an amorphous state according to a current supplied through the bit line BL. The variable resistance memory device uses this characteristic of the variable resistance material (GST) to program data.

The selection element 12 is composed of an NMOS transistor NT. The word line WL is connected to the gate of the NMOS transistor NT. When a predetermined voltage is applied to the word line WL, the NMOS transistor NT is turned on. When the NMOS transistor NT is turned on, the memory device 11 receives a current through the bit line BL. In FIG. 1, the memory element 11 is connected between the bit line BL and the selection element 12. However, the selection element 12 may be connected between the bit line BL and the memory element 11.

2 shows another memory cell of a variable resistance memory device. Referring to FIG. 2, the memory cell 20 includes a memory element 21 and a selection element 22. The memory element 21 is connected between the bit line BL and the selection element 22, and the selection element 22 is connected between the memory element 21 and ground. The memory element 21 is the same as the memory element 11 of FIG. 1.

The selection element 22 is composed of a diode D. The memory element 21 is connected to the anode of the diode D, and the word line WL is connected to the cathode. When the voltage difference between the anode and the cathode of the diode D becomes higher than the threshold voltage of the diode D, the diode D is turned on. When the diode D is turned on, the memory device 21 receives a current through the bit line BL.

FIG. 3 is a graph for explaining the characteristics of the variable resistance material GST shown in FIGS. 1 and 2. In Fig. 3, reference numeral 1 denotes a condition for the variable resistive material GST to be in an amorphous state, and reference numeral 2 denotes a condition for becoming a crystal state.

Referring to FIG. 3, the variable resistance material GST is heated to a temperature higher than the melting temperature Tm for a period of time T1 by a current supply, and then rapidly cooled to a amorphous state. The amorphous state is usually called the reset state and stores data '1'. In contrast, the variable resistive material is brought into a crystal state by heating for a longer time T2 than T1 at a temperature above the crystallization temperature (Tc) and below the melting temperature (Tm) and then slowly cooling. The decision state is also commonly called the set state and stores the data '0'. Memory cells vary in resistance depending on the amorphous volume of the variable resistive material. The resistance of the memory cell is high in the amorphous state and low in the crystalline state.

The variable resistance memory device provides a program current to a selected memory cell during a program operation. The selected memory cell is programmed to the reset state or the set state according to the program current. The reset current is a current for programming the memory cell to the reset state, and the set current is a current for programming to the set state. That is, the set current causes the variable resistance material GST to be in a crystalline state, and the reset current causes the variable resistance material GST to be in an amorphous state.

As shown in FIG. 3, in order to make the variable resistance material GST into a crystalline state, a set current corresponding to a temperature between Tc and Tm must be provided to the memory cell for a T2 time. In order to make the variable resistance material (GST) amorphous, a reset current corresponding to a temperature above Tm must be provided to the memory cell during the T1 time. In other words, the set current and the reset current should have a size and an application time corresponding to a change in state of the variable resistance material GST. In general, the reset current is larger than the set current, and the set current has a longer application time than the reset current.

The memory cell array of the variable resistance memory device is composed of a plurality of memory cells. Each memory cell is connected to a word line and a bit line. A large number of memory cells are connected to one word line. Memory cells in a row direction are selected according to the voltage level of the word line. When the NMOS transistor (see FIG. 1, NT) is included in the memory cell, the memory cell in the row direction is selected according to the high level word line voltage. When a diode (see FIG. 2, D) is included in the memory cell, the memory cell in the row direction is selected according to the word line voltage at the low level. When the memory cell has a diode as the selection element, a word line is connected to the cathode terminal of the diode.

When a program current or a read current is applied to a plurality of memory cells connected to one word line, the voltage level of the word line may increase undesirably. This phenomenon is caused by parasitic resistance and parasitic capacitors present in the word line. Here, the voltage level of the word line rises as the number of memory cells connected to the word line increases. This is a factor that degrades the program and read characteristics of the variable resistance memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a variable resistance memory device which minimizes an increase in a word line voltage when a program current or a read current is applied to a plurality of memory cells connected to a word line. To provide.

A variable resistance memory device according to the present invention includes a memory cell array having a plurality of block units and a plurality of word line drivers, each block unit being connected between neighboring word line drivers and configured to have a plurality of memory blocks; A sense amplifier circuit having a plurality of sense amplifier units, each sense amplifier unit configured to provide a read current to a corresponding block unit and have a plurality of sense amplifiers; And a column select circuit connected between the memory cell array and the sense amplifier circuit to select at least one memory block from the plurality of memory blocks in response to a column select signal, and to deliver the read current to the selected memory block. Include.

In an embodiment, the word line driver is connected between the main word line and the sub word line, and drives the sub word line according to the voltage level of the main word line. The word line driver includes a PMOS transistor and an NMOS transistor, wherein the main word line is connected to gates of the PMOS transistor and the NMOS transistor, and the sub word line is connected to a source.

Each memory block has a plurality of memory cells connected to the sub word line. The memory cell includes a memory element having a phase change material; And a selection device for selecting the memory cell, wherein the selection device is a diode connected between the memory device and the sub word line.

The column selection circuit has a plurality of column selection units, each column selection unit being connected between a corresponding block unit and a corresponding sense amplifier unit. Each column selection unit is composed of a plurality of NMOS transistors turned on or off in response to the column selection signal.

The variable resistance memory device according to the present invention can reduce the increase in the word line voltage due to the parasitic resistance or the parasitic capacitor during the program operation or the read operation. According to the present invention, it is possible to prevent a decrease in program or read characteristics due to an increase in the word line voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

I. Variable resistance memory device

4 is a block diagram illustrating a variable resistance memory device according to the present invention. Referring to FIG. 4, the variable resistance memory device 100 includes a memory cell array 110, an address decoder 120, a column select circuit 130, a data input / output circuit 135, and a control unit 160. . The data input / output circuit 135 includes a write driver circuit 140 and a sense amplifier circuit 150.

The memory cell array 110 is connected to the main word line MWL and the bit line BL. The memory cell array 110 includes a plurality of block units 111, 112, 113, and 114, and a plurality of word line drivers WD1 to WD5. Each block unit includes a plurality of memory blocks (not shown) and is located between neighboring word line drivers. For example, the first block unit 111 is located between the first and second word line drivers WD1 and WD2.

The address decoder 120 decodes the address ADDR input from the outside. Here, the address ADDR includes a row address RA and a column address CA. The address decoder 120 selects the main word line MWL by the row address RA, and selects the bit line BL by the column address CA. To this end, the address decoder 120 provides a column select signal BAi to the column select circuit 130.

The column select circuit 130 is connected to the memory cell array 110 through the bit line BL, and is connected to the data input / output circuit 135 through the data line DL and the sensing line SL. The column select circuit 130 electrically connects the data line DL or the sensing line SL with the bit line BL in response to the column select signal BAi.

The data input / output circuit 135 includes a write driver circuit 140 and a sense amplifier circuit 150. The write driver circuit 140 provides a program current to the memory cell array 110 through the data line DL during a program operation. The sense amplifier circuit 150 provides a read current to the memory cell array 110 through the sensing line SL in a read operation.

The write driver circuit 140 receives a program pulse and data, and provides a program current to the data line DL. The program pulse is input from the control unit 160. Here, the program pulse includes a set pulse P_SET and a reset pulse P_RST, and the program current includes a set current I_SET and a reset current I_RST. The write driver circuit 140 generates the set current I_SET in response to the set pulse P_SET when data '0' is input, and in response to the reset pulse P_RST when the data '1' is input. Generates a reset current I_RST.

The sense amplifier circuit 150 reads the data stored in the memory cell by comparing the voltage of the sensing line SL with the reference voltage Vref during a read operation. Here, the reference voltage Vref is provided from a reference voltage generation circuit (not shown). Meanwhile, the sense amplifier circuit 150 provides a read current (or bias current) to the memory cell array 110 through the sensing line SL during a read operation.

The control unit 160 generates a signal for controlling the data input / output circuit 135 in response to the control signal CTRL. For example, the control unit 160 provides the write driver circuit 140 with program pulses P_SET and P_RST for generating a program current during a program operation. The control unit 160 provides a sense signal to the sense amplifier circuit 150 for generating a read current in the read operation.

In a conventional variable resistance memory device including a diode in a memory cell, when a program current or a read current is applied to a plurality of memory cells connected to one word line, the voltage level of the word line may increase undesirably. Increasing the word line voltage can degrade the program and read characteristics of the variable resistance memory device.

The variable resistance memory device according to the present invention divides a memory cell array into a plurality of block units and includes a word line driver between each block unit, thereby minimizing the increase of the word line voltage during a program operation and a read operation. . Hereinafter, a program method and a read method of a variable resistance memory device according to the present invention will be described in detail.

II. Program method of variable resistance memory device

FIG. 5 is a block diagram illustrating a program method of the variable resistance memory device illustrated in FIG. 4. 5 exemplarily shows the memory cell array, the column selection circuit, and the write driver circuit shown in FIG. 4. Although one main word line MWL is shown in FIG. 5, the variable resistance memory device actually has a larger number of main word lines than this.

Referring to FIG. 5, the memory cell array 110 may include first to fourth block units 111 to 114 and first to fifth word line drivers WD1 to WD5. Each block unit is located between neighboring word line drivers and includes four memory blocks. For example, the first block unit 111 is positioned between the first and second word line drivers WD1 and WD2 and includes first to fourth memory blocks 211 to 214. Each memory block includes a plurality of memory cells.

6 exemplarily shows a first block unit shown in FIG. 5. Referring to FIG. 6, the first and second word line drivers WD1 and WD2 are connected between the main word line MWL and the sub word line SWL. Each word line driver consists of a PMOS transistor and an NMOS transistor. The main word line MWL is connected to the gate of the PMOS transistor and the NMOS transistor, and the sub word line SWL is connected to the drain.

The sub word line SWL is driven according to the voltage level of the main word line MWL. When the voltage of the main word line MWL is high, the sub word line SWL has a low level. On the contrary, when the voltage of the main word line MWL is low level, the sub word line SWL has a high level voltage.

First to fourth memory blocks 211 to 214 are connected to the sub word line SWL connecting the first and second word line drivers WD1 and WD2. The first memory block 211 has a plurality of memory cells connected to the sub word line SWL. Each memory cell is composed of a memory element and a select element. The memory element comprises a variable resistance material GST, and the selection element comprises a diode D.

Referring back to FIG. 5, the column select circuit 130 is connected between the bit line BL and the data line DL. The column select circuit 130 electrically connects the data line and the selected bit line in response to the column select signal BAi. The column select circuit 130 includes first to fourth column select units 131 to 134. The first to fourth column selection units 131 to 134 are connected to the first to fourth block units 111 to 114, respectively.

Each column selection unit is composed of a plurality of NMOS transistors, and receives the first to fourth column selection signals BA1 to BA4. For example, the first column selection unit 131 selects the first memory block 211 in response to the first column selection signal BA1 and the second memory block in response to the second column selection signal BA2. Select (212).

The write driver circuit 140 receives a program pulse and data, and provides a program current to the data line DL. Referring to FIG. 5, the write driver circuit 140 includes first to fourth write driver units 141 to 144. Each write driver unit provides a program current to the corresponding block unit. For example, the first write driver unit 141 provides a program current to the first block unit 111, and the second write driver unit 142 provides a program current to the second block unit 112.

Each write driver unit includes four write drivers. For example, the first write driver unit 141 includes first to fourth write drivers W / D1 to W / D4. Each write driver has the same configuration and operating principle.

7 exemplarily shows the first write driver W / D1. Referring to FIG. 7, the write driver W / D1 includes a pulse control circuit 410, a current control circuit 420, and a current driving circuit 430. The pulse control circuit 410 includes first and second transfer gates TG1 and TG2 and first to third inverters INV1 to INV3. The current control circuit 420 includes first to seventh transistors TR1 to TR7. Here, the first to fifth transistors TR1 to TR5 are NMOS transistors, and the sixth and seventh transistors TR6 and TR7 are PMOS transistors. The current driving circuit 430 includes a pull up transistor PUTR and a pull down transistor PDTR.

First, the case where the input data DQ1 is '0' will be described. When the input data DQ1 is '0', the second transfer gate TG2 of the pulse control circuit 410 is turned on, and the third and fourth transistors TR3 and TR4 of the current control circuit 420 are turned on. Is off. The fifth transistor TR5 is turned on by the set pulse P_SET1, and the seventh transistor TR7 and the pull-down transistor PDTR are turned off. At this time, the current flowing through the transistors TR1, TR2, TR5, and TR6 forming the first current path flows through the pull-up transistor PUTR by the current mirror effect. The current flowing through the pull-up transistor PUTR is the set current I_SET1 and is provided to the selected memory cell MC through the data line DL1.

Next, the case where the input data DQ1 is '1' will be described. When the input data DQ1 is '1', the first transfer gate TG1 of the pulse control circuit 410 and the third and fourth transistors TR3 and TR4 of the current control circuit 420 are turned on. The fifth transistor TR5 is turned on by the reset pulse P_RST1, and the seventh transistor TR7 and the pull-down transistor PDTR are turned off. At this time, the current flowing through the transistors TR1, TR2, TR5, and TR6 forming the first current path and the transistors TR3, TR4, TR5, and TR6 forming the second current path are pulled up by the current mirror effect. Flow through transistor PUTR. The current flowing through the pull-up transistor PUTR is a reset current I_RST1 and is provided to the selected memory cell MC through the data line DL1.

Here, the reset current I_RST1 has a larger current value than the set current I_SET1. In addition, the reset pulse P_RST1 has a pulse width smaller than that of the set pulse P_SET1. Therefore, the reset current I_RST1 has a larger current value than the set current I_SET1 and has a small pulse width. The selected memory cells are programmed to the reset state or the set state by the reset current I_RST1 or the set current I_SET1, respectively.

Referring back to FIG. 5, the first to fourth write driver units 141 to 144 provide program currents to the first to fourth block units 111 to 114, respectively. When the first column selection signal BA1 is activated, a program current is provided to the first memory blocks 211, 221, 231, and 241 in each block unit. When the second column select signal BA2 is activated, a program current is provided to the second memory blocks 212, 222, 232, and 242.

Meanwhile, the variable resistance memory device 100 illustrated in FIG. 5 has various program methods according to an application method of program pulses P_SET and P_RST. That is, the variable resistance memory device 100 may program 16_bit data simultaneously in the selected memory cell. This is explained in detail in FIG. 8.

In addition, the variable resistance memory device 100 may be programmed eight times in units of 2 bits, four times in units of 4 bits, or twice in units of 8 bits to reduce program currents applied at one time. Can be programmed over. In this specification, such a program method is defined as a 'multi program method'. Multi-program methods include an x2 program method, an x4 program method, an x8 program method, and the like, depending on the number of memory cells that are simultaneously programmed. The multi program method is described in detail with reference to FIGS. 9 and 10.

Here, 2_bit data, 4_bit data, and 8_bit data are data programmed simultaneously in response to one program pulse. According to the x2 programming method, the program current applied at one time is reduced to 1/8, and to 1/4 according to the x4 programming method, and to 1/2 according to the x8 programming method. In addition, according to the multi-program method, it is possible to prevent the program characteristics from deteriorating due to the increase in the sub word line voltage.

The variable resistance memory device 100 illustrated in FIG. 5 divides the memory cell array 110 into a plurality of block units 111 to 114, and writes a plurality of writes so that the write driver circuit 140 corresponds to each block unit. It is divided into driver units 141 to 144. The variable resistance memory device has a respective column selection unit for electrically connecting each block unit and each write driver unit. The variable resistance memory device 100 having such a configuration can efficiently use a multi-program method. According to the present invention, the voltage rise of the sub word line can be prevented during the program operation. This is described in detail with reference to FIGS. 8 to 10.

8 shows a case where 16_bit data is programmed at the same time. 8 shows that the first column selection signal BA1 is activated and 4_bit data is simultaneously programmed into the first memory block 211 through the first to fourth write drivers W / D1 to W / D4. Shows. Similarly, the remaining first memory blocks 221, 231, and 241 are also programmed at the same time.

The first memory block 211 includes first to fourth memory cells A1 to A4. The first to fourth memory cells A1 to A4 are selected memory cells, that is, memory cells to be programmed. The first to fourth memory cells A1 to A4 are connected to the sub word line SWL. As shown in FIG. 8, during a program operation, a program current is simultaneously applied to the first to fourth memory cells A1 to A4.

Referring to FIG. 8, the first to fourth memory cells A1 to A4 include diodes as selection elements. The cathode of the diode is connected to the sub word line SWL. When the voltage difference between the anode and the cathode of the diode is higher than the threshold voltage of the diode, the diode is turned on. When the diode is turned on, the memory cell is supplied with a program current through the bit line BL.

However, when a program current is simultaneously provided to the first to fourth memory cells A1 to A4, the diode may not turn on properly. This is because the voltage of the sub word line SWL suddenly rises due to the parasitic resistance Rc or the parasitic capacitor (not shown) present on the sub word line SWL. That is, the charge of the sub word line SWL falls to the ground through the NMOS transistors N1 and N2 of the first and second sub word lines WD1 and WD2 due to the influence of the parasitic resistance Rc or the parasitic capacitor. Because you can't go out. When the voltage of the sub word line SWL rises, the program characteristic of the variable resistance memory device is degraded.

The variable resistance memory device 100 according to the present invention has a block unit, a column selection unit, and a write driver unit structure as shown in FIG. 5 to solve this problem, and uses a multi-program method.

FIG. 9 is a timing diagram illustrating a multi program method of the variable resistance memory device illustrated in FIG. 5. In FIG. 5, first program pulses P_SET1 and P_RST1 are applied to the first and ninth write drivers W / D1 and W / D9. The second program pulses P_SET2 and P_RST2 are applied to the second and tenth write drivers W / D2 and W / D10. The eighth and sixteenth write drivers W / D8 and W / D16 are applied in this manner. ), Eighth program pulses P_SET8 and P_RST8 are applied. Although only the set pulse P_SET is illustrated in FIG. 9, the reset pulse P_RST is also applied in the same manner.

9 (a) shows a program pulse application method according to the x2 program method. According to the x2 program method, memory cells in the first and third block units 111 and 113 are sequentially programmed when the first to fourth program pulses are sequentially applied. When the fifth to eighth program pulses are applied, the memory cells in the second and fourth block units 112 and 114 are sequentially programmed. That is, using the x2 programming method, the variable resistance memory device 100 may sequentially program 16_bit data 8 times in 2_bit units.

9 (b) shows a program pulse application method according to the x4 program method. According to the x4 program method, the first and fifth program pulses, the second and sixth program pulses, the third and seventh program pulses, and the fourth and eighth program pulses are simultaneously applied. For example, selected memory cells of the first to fourth block units 111 to 114 are programmed simultaneously when the first and fifth program pulses are applied. At this time, there is one selected memory cell for each block unit. That is, 4_bit data is programmed at the same time by applying one program pulse. This is explained in detail with reference to FIG.

9 (c) shows a program pulse application method according to the x8 program method. According to the x8 program method, the first and second and fifth and sixth program pulses, and the third and fourth and seventh and eighth and program pulses are simultaneously applied. For example, when the first and second and fifth and sixth program pulses are applied, selected memory cells of the first to fourth block units 111 to 114 are programmed at the same time. At this time, there are two selected memory cells for each block unit. That is, 8_bit data is programmed at the same time by applying one program pulse.

FIG. 10 shows a case where 4_bit data is simultaneously programmed by the x4 program method shown in FIG. 9 (b). FIG. 10 illustrates memory cells B1 to B4 in which 4_bit data is selected through the first column selection signal BA1 and the write driver W / D1, W / D5, W / D9, and W / D13 are selected. Show that it is programmed at the same time. The memory cells B1 to B4 are included in different block units, respectively. The first memory cell B1 is the first block unit 111, the second memory cell B2 is the second block unit 112, the third memory cell B3 is the third block unit 113, and Four memory cells B4 are included in the fourth block unit 114.

 Referring to FIG. 10, a first memory cell B1 is connected between the first and second word line drivers WD1 and WD2, and a second memory is connected between the second and third word line drivers WD2 and WD3. The cell B2 is connected, the third memory cell B3 is connected between the third and fourth word line drivers WD3 and WD4, and the fourth memory cell B3 is connected between the fourth and fifth word line drivers WD4 and WD5. The memory cell B4 is connected.

When the program current is simultaneously provided to the first to fourth memory cells B1 to B4 by the x4 program method, the sub word line SWL may be affected by the parasitic resistance Rc or the parasitic capacitor. Receive less than In FIG. 8, four memory cells A1 to A4 are connected between the first and second word line drivers WD1 and WD2. Therefore, in FIG. 8, the voltage level of the sub word line SWL is greatly affected by the parasitic resistance Rc and the like during the program operation. On the other hand, in FIG. 10, only one memory cell B1 is connected between the first and second word line drivers WD1 and WD2. Therefore, the sub word line SWL is relatively less affected by the parasitic resistance Rc.

The variable resistance memory device according to the present invention is configured to have a block unit, a column selection unit, and a write driver unit as shown in FIG. The present invention can prevent the rise of the word line voltage using a multi-program method. This is because the number of program cells existing between adjacent word line drivers during the program operation is reduced.

Meanwhile, in the variable resistance memory device 100 according to the present invention, one or two write drivers may be connected to one block unit. FIG. 11 illustrates a structure in which two write drivers are connected to one block unit, and FIG. 12 illustrates a structure in which one write driver is connected to one block unit.

Referring to FIG. 11, the variable resistance memory device 100a may include a memory cell array 110a and a write driver circuit 140a. The memory cell array 110a includes first to eighth block units and first to ninth word line drivers WD1 to WD9. Each block unit is located between neighboring word line drivers and includes two memory blocks. For example, the first block unit is positioned between the first and second word line drivers WD1 and WD2 and includes first and second memory blocks.

The write driver circuit 140a includes first to eighth write driver units 141a to 148a. Each write driver unit provides a program current to the corresponding block unit. For example, the first write driver unit 141a provides the program current to the first block unit, and the second write driver unit 142a provides the program current to the second block unit.

Each write driver unit includes two write drivers. For example, the first write driver unit 141a is composed of first and second write drivers W / D1 and W / D2. The variable resistance memory device 110a shown in FIG. 11 has the same operating principle as the variable resistance memory device 110 shown in FIG. 5. The variable resistance memory device 110a illustrated in FIG. 11 may further reduce the increase in the word line voltage due to the parasitic resistance or the parasitic capacitor than the variable resistance memory device 110 illustrated in FIG. 5. This is because the number of program cells between word line drivers is reduced.

Referring to FIG. 12, the variable resistance memory device 100b includes a memory cell array 110b and a write driver circuit 140b. The memory cell array 110b includes first to sixteenth block units and first to seventeenth word line drivers WD1 to WD17. Each block unit consists of one memory block. The write driver circuit 140b includes first to sixteenth write drivers W / D1 to W / D16. The variable resistance memory device 110b illustrated in FIG. 12 may further reduce an increase in the word line voltage due to the parasitic resistance or the parasitic capacitor than the variable resistance memory device 110a illustrated in FIG. 11.

III. How to read a variable resistance memory device

FIG. 13 is a block diagram illustrating a read method of the variable resistance memory device illustrated in FIG. 4. FIG. 13 exemplarily shows the memory cell array, the column selection circuit, and the sense amplifier circuit shown in FIG. 4.

Referring to FIG. 13, the memory cell array 110 includes first to fourth block units 111 to 114 and first to fifth word line drivers WD1 to WD5. Each block unit includes four memory blocks. The column select circuit 130 is connected between the bit line BL and the sensing line SL. The column select circuit 130 electrically connects the sensing line SL and the selected bit line in response to the column select signal BAi. The column select circuit 130 includes first to fourth column select units 131 to 134. The first to fourth column selection units 131 to 134 are connected to the first to fourth block units 111 to 114, respectively.

The sense amplifier circuit 150 provides a read current (or bias current) to the memory cell through the sensing line SL, and compares the data stored in the memory cell by comparing the voltage of the sensing line SL with a reference voltage during the sensing operation. Read. Referring to FIG. 13, the sense amplifier circuit 150 includes first to fourth sense amplifier units 151 to 154. Each sense amplifier unit provides a read current to the corresponding block unit. For example, the first sense amplifier unit 151 provides a read current to the first block unit 111, and the second sense amplifier unit 152 provides a read current to the second block unit 112.

Each sense amplifier unit includes four sense amplifiers. For example, the first sense amplifier unit 151 includes first to fourth sense amplifiers S / A1 to S / A4. Each sense amplifier has the same configuration and principle of operation.

According to the conventional read method, when a read current is simultaneously provided to the memory cells, the parasitic resistor Rc or the parasitic capacitor (not shown) present on the sub word line SWL may cause the The voltage may rise. When the voltage of the sub word line SWL rises, the read characteristic of the variable resistance memory device becomes worse.

In the read operation, more read cells are simultaneously supplied to more memory cells than in the program operation. At this time, when the sub word line voltage increases, the set resistance distribution of the memory cells moves toward the reset resistance distribution. By such a mechanism, the sensing margin of the memory cell is lowered, and the read characteristic of the variable resistance memory device is worsened.

The variable resistance memory device 100 according to the present invention has a block unit, a column selection unit, and a sense amplifier unit structure as shown in FIG. 13 to solve this problem. That is, the present invention divides the memory block into a plurality of block units and minimizes the word line voltage rise by disposing a word line driver between each block unit. This is because, as described in FIG. 5, the number of memory cells existing between adjacent word line drivers during a read operation is reduced.

Meanwhile, in the variable resistance memory device 100 according to the present invention, one or two sense amplifiers may be connected to one block unit. FIG. 14 shows a structure in which two sense amplifiers are connected to one block unit, and FIG. 15 shows a structure in which one sense amplifier is connected to one block unit.

Referring to FIG. 14, the variable resistance memory device 100c may include a memory cell array 110c and a sense amplifier circuit 150a. The memory cell array 110c includes first to eighth block units and first to ninth word line drivers WD1 to WD9. Each block unit is located between neighboring word line drivers and includes two memory blocks. For example, the first block unit is positioned between the first and second word line drivers WD1 and WD2 and includes first and second memory blocks.

The sense amplifier circuit 150a includes first to eighth sense amplifier units 151a to 158a. Each sense amplifier unit provides a read current to the corresponding block unit. For example, the first sense amplifier unit 151a provides a read current to the first block unit, and the second sense amplifier unit 152a provides a read current to the second block unit.

Each sense amplifier unit includes two sense amplifiers. For example, the first write driver unit 151a is composed of first and second sense amplifiers S / A1 and S / A2. The variable resistance memory device 110c shown in FIG. 14 has the same operating principle as the variable resistance memory device 110 shown in FIG. 13. The variable resistance memory device 110c illustrated in FIG. 14 may further reduce the increase in the word line voltage due to the parasitic resistance or the parasitic capacitor than the variable resistance memory device 110 illustrated in FIG. 13.

Referring to FIG. 15, the variable resistance memory device 100d includes a memory cell array 110d and a sense amplifier circuit 150b. The memory cell array 110d includes first to sixteenth block units and first to seventeenth word line drivers WD1 to WD17. Each block unit consists of one memory block. The sense amplifier circuit 150b includes first to sixteenth sense amplifiers S / A1 to S / A16. The variable resistance memory device 110d illustrated in FIG. 15 may further reduce an increase in a word line voltage due to a parasitic resistance or a parasitic capacitor than the variable resistance memory device 110c illustrated in FIG. 14.

16 is a block diagram schematically illustrating a memory system 500 including a variable resistance memory device according to the present invention. Referring to FIG. 16, a memory system 500 according to an exemplary embodiment of the present invention may include central processing electrically connected to a semiconductor memory device 510 and a system bus 550 including a variable resistance memory device 511 and a memory controller 512. Device 530, user interface 540, and power supply 520.

The variable resistance memory device 511 stores data provided through the user interface 540 or processed by the CPU 530 through the memory controller 512. The semiconductor memory device 510 may be configured as a semiconductor disk device (SSD).

Although not shown in the drawings, the memory system according to the present invention may be further provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-evident to one.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

1 shows a memory cell of a variable resistance memory device.

2 shows another memory cell of a variable resistance memory device.

3 is a graph for explaining the characteristics of the variable resistance material.

4 is a block diagram illustrating a variable resistance memory device according to the present invention.

FIG. 5 is a block diagram illustrating a program method of the variable resistance memory device illustrated in FIG. 4.

FIG. 6 is a circuit diagram illustrating the memory cell array shown in FIG. 5.

FIG. 7 is a circuit diagram illustrating the write driver illustrated in FIG. 5.

FIG. 8 illustrates a case where 16_bit data is simultaneously programmed in the variable resistance memory device of FIG. 5.

FIG. 9 is a timing diagram illustrating a multi program method of the variable resistance memory device illustrated in FIG. 5.

FIG. 10 illustrates a case in which 4_bit data is simultaneously programmed by the x4 program method of FIG. 9.

11 and 12 are block diagrams illustrating another example of a program method of the variable resistance memory device illustrated in FIG. 4.

FIG. 13 is a block diagram illustrating a read method of the variable resistance memory device illustrated in FIG. 4.

14 and 15 are block diagrams illustrating another example of a reading method of the variable resistance memory device illustrated in FIG. 4.

16 is a block diagram schematically illustrating a memory system including a variable resistance memory device according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100; Variable resistance memory device 110; Memory cell array

120; Address decoders 111, 112, 113, 114; Block unit

130; Column selection circuit 140; Write driver circuit

150; Sense amplifier circuit 160; Control unit

Claims (7)

A memory cell array having a plurality of block units and a plurality of word line drivers, each block unit being coupled between neighboring word line drivers and configured to have a plurality of memory blocks; A sense amplifier circuit having a plurality of sense amplifier units, each sense amplifier unit configured to provide a read current to a corresponding block unit and have a plurality of sense amplifiers; And A column select circuit connected between the memory cell array and the sense amplifier circuit to select at least one memory block from the plurality of memory blocks in response to a column select signal and to deliver the read current to the selected memory block. Variable resistance memory device. The method of claim 1, And the word line driver is coupled between a main word line and a sub word line and drives the sub word line according to a voltage level of the main word line. The method of claim 2, The word line driver includes a PMOS transistor and an NMOS transistor, wherein the main word line is connected to a gate of the PMOS transistor and the NMOS transistor, and the sub word line is connected to a source. The method of claim 2, Wherein each memory block has a plurality of memory cells connected to the sub word line. The method of claim 4, wherein The memory cell is A memory element having a phase change material; And A selection element for selecting the memory cell, And the selection element is a diode connected between the memory element and the sub word line. The method of claim 1, And said column selection circuit has a plurality of column selection units, each column selection unit being connected between a corresponding block unit and a corresponding sense amplifier unit. The method of claim 6, Wherein each column selection unit comprises a plurality of NMOS transistors turned on or off in response to the column selection signal.

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