KR20080102628A - Manufacturing Method of Semiconductor Integrated Circuit Device - Google Patents

Abstract

A method for manufacturing a semiconductor integrated circuit device is provided. A method for manufacturing a semiconductor integrated circuit device forms a semiconductor substrate including a lower substrate in a first orientation and an upper substrate in a second orientation, and forms an amorphous region in a portion of the semiconductor substrate, wherein the depth of the amorphous region is greater than the depth of the upper substrate. It forms deeply, and irradiates a laser to an amorphous region, and melt | dissolves an amorphous region and recrystallizes.

Description

Method of fabricating semiconductor integrated circuit device

1 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

 (Explanation of symbols for the main parts of the drawing)

105: device isolation region 110: lower substrate

120: upper substrate 130: amorphous region

132: recrystallization area 210: mask pattern

310: first transistor 312: first gate insulating film

314: First gate electrode 316: First source / drain region

318: First spacer 320: Second transistor

322: second gate insulating film 324: second gate electrode

326: second source / drain region 328: second spacer

The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a method for manufacturing a semiconductor integrated circuit device with improved reliability.

As semiconductor integrated circuit devices become more compact and highly integrated, it is required to further improve the characteristics of semiconductor devices.

In general, a semiconductor integrated circuit device uses a semiconductor substrate having a (100) orientation. However, the mobility of electrons in the (100) orientation is good, but the mobility of holes is relatively poor. On the other hand, in the (110) orientation, the mobility of electrons is poor, and the mobility of holes is good. Therefore, when the N-type transistor whose main carrier is electron is formed on the semiconductor substrate in the (100) orientation, the P-type transistor whose main carrier is in the hole is formed on the semiconductor substrate in the (110) orientation, the characteristics of each element can be further improved. have.

These characteristics are used to form semiconductor substrates having different surface orientations, which are referred to as hybrid orientation structures. When forming a hybrid orientation structure, crystals are grown in a part of an upper region separated by a device isolation region or the like by using a selective epitaxial growing (SEG) process or a solid phase epitaxy (SPE) process, so that the orientation is different from the surrounding region. .

However, when the SEG process or the SPE process is performed, defects may occur in the sidewall or the lower region which is the boundary region. In this case, the reliability of the semiconductor integrated circuit device may be degraded.

It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit device with improved reliability.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor integrated circuit device may include forming a semiconductor substrate including a lower substrate having a first orientation and an upper substrate having a second orientation, and part of the semiconductor substrate. Forming an amorphous region in the depth of the amorphous region is formed deeper than the depth of the upper substrate, and irradiating a laser to the amorphous region by melting the amorphous region and recrystallization.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, which includes forming a semiconductor substrate including a lower substrate having a first orientation and an upper substrate having a second orientation, and forming a plurality of semiconductor substrates on the semiconductor substrate. Forming a plurality of device isolation regions to define a plurality of active regions separated by the plurality of device isolation regions, forming a mask pattern that opens only a portion of the plurality of active regions, and forming an active region opened by the mask pattern An ion implantation process is performed to form an amorphous region in the open active region, wherein the depth of the amorphous region is formed deeper than the depth of the upper substrate. The region has the same orientation as the lower substrate, and the mask pattern Removing a portion and planarizing a portion of the upper surface of the semiconductor substrate.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Thus, well-known device structures and well-known techniques in some embodiments are not described in detail in order to avoid obscuring the present invention.

Like reference numerals refer to like elements throughout the specification. And / or include each and all combinations of one or more of the items mentioned.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, including and / or comprising the components, steps, operations and / or elements mentioned exclude the presence or addition of one or more other components, steps, operations and / or elements. I never do that.

Hereinafter, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7. 1 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

In the following description of the manufacturing method, a process that can be formed according to process steps that are well known to those skilled in the art will be briefly described in order to avoid being ambiguously interpreted.

First, referring to FIG. 1, a semiconductor substrate including a lower substrate 110 in a first orientation and an upper substrate 120 in a second orientation is formed.

The semiconductor substrate including the upper substrate 120 and the lower substrate 110 may be an Si semiconductor substrate, a silicon on insulator (SOI) semiconductor substrate, a GaAs semiconductor substrate, a SiGe semiconductor substrate, a ceramic semiconductor substrate, a quartz semiconductor substrate, or a display glass. Semiconductor substrates or the like. That is, a semiconductor substrate having a lower substrate 110 in a first orientation and an upper substrate 120 in a second orientation may be used on the sub-semiconductor substrate. Meanwhile, the lower substrate 110 in the first orientation and the upper substrate 120 in the second orientation include Si, and may further include one or more combinations selected from the group including SiGe and Ge.

In addition, the first and second orientations of the lower substrate 110 may be, for example, a (100) or (110) orientation. At this time, the first orientation and the second orientation have different orientations, for example, when the first orientation is a (100) orientation, the second orientation may have a (110) orientation.

2, a plurality of device isolation regions 105 are formed on a semiconductor substrate to define a plurality of active regions separated by a plurality of device isolation regions 105.

That is, device isolation regions 105 such as shallow trench isolation (STI) or field oxide (FOX) are formed on the semiconductor substrate and separated into active and inactive regions.

Next, referring to FIG. 3, a mask pattern 210 that opens only a part of the plurality of active regions is formed.

That is, a mask pattern 210 that opens only a portion of the plurality of active regions separated by the device isolation region 105 is formed. In this case, a photolithography process may be performed to form a mask pattern 210 that opens only a part of the plurality of active regions. In this case, the region to be opened is separated by the device isolation region 105 with respect to the region not opened by the mask pattern 210.

4, an ion implantation process is performed on the active region opened by the mask pattern 210 to form the amorphous region 130 in the open active region.

Here, the ion implantation process may be, for example, a Pre Amorphization Implantation (PAI) process, and Ge may be implanted in the PAI process. That is, the amorphous region 130 is formed by injecting Ge into the active region opened by the mask pattern 210. At this time, the active region opened by the mask pattern 210 includes the lower substrate 110 in the first orientation and the upper substrate 120 in the second orientation, which is changed to the amorphous region 130 by the Ge PAI process. do. At this time, the depth where the amorphous region 130 is formed is formed deeper than the depth of the upper substrate 120 so that the lower surface of the amorphous region 130 is in contact with the lower substrate 110 in the second orientation.

Subsequently, referring to FIG. 5, the amorphous region 130 is irradiated with a laser to melt and recrystallize the amorphous region 130.

Specifically, the laser is irradiated to the amorphous region 130 opened by the mask pattern 210. At this time, the wavelength and intensity of the laser are adjusted so that the temperature of the amorphous region 130 is higher than 1410 ° C., which is the melting point of silicon. That is, by irradiating a laser to make the temperature of the amorphous region 130 higher than the melting point, the amorphous region 130 is melted. When the laser is irradiated and the amorphous region 130 is melted, it is recrystallized while cooling. At this time, the orientation of the region to be recrystallized has the same orientation as that of the lower substrate 110 in contact with the lower portion. Thus, the recrystallized region 132 has a second orientation. For example, when the lower substrate 110 has a (100) orientation, the recrystallized region 132 also has a second orientation.

Subsequently, the mask pattern 210 on the semiconductor substrate is removed. The mask pattern 210 may be removed by an etching process, a cleaning process, or the like.

Next, referring to FIG. 6, a portion of the upper surface of the semiconductor substrate is planarized.

Specifically, for example, a chemical mechanical polishing process (CMP) is performed to planarize the upper surface of the semiconductor substrate. That is, since the surface of the semiconductor substrate may be uneven while the recrystallization region 132 is formed, the planarization process is performed to even the surface of the semiconductor substrate. The semiconductor substrate subjected to the planarization process includes a plurality of active regions separated by the device isolation region 105, the second upper substrate region 120 having a first orientation and a second crystal region having a second orientation. It is divided into the upper substrate region 132. In this case, the first upper substrate region 120 and the second upper substrate region 132 are separated by the device isolation region 105.

Next, referring to FIG. 7, a first transistor 310 is formed in the first upper substrate region 120, and a second transistor 320 is formed in the second upper substrate region 132.

At this time, an N-type transistor is formed in a region of the (100) orientation, and a P-type transistor is formed in a region of the (110) orientation. For example, when the first orientation is a (100) orientation, the first transistor 310 is an N-type transistor, and when the second orientation is a (110) orientation, the second transistor is a P-type transistor.

Here, the first transistor 310 includes a first gate insulating layer 312, a first gate electrode 314, a first source / drain region 316, and a first spacer 318, and the second transistor 320. ) Includes a second gate insulating layer 322, a second gate electrode 324, a second source / drain region 326, and a second spacer 328.

According to the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, when forming a semiconductor substrate including regions having different orientations, the defects of the semiconductor substrate are reduced by melting and recrystallizing a part of the semiconductor substrate. do. Therefore, the reliability of the semiconductor integrated circuit device can be improved.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the method for manufacturing a semiconductor integrated circuit device as described above has the following advantages. That is, when forming a semiconductor substrate including regions having different orientations, by melting and recrystallizing a part of the semiconductor substrate, defects of the semiconductor substrate can be reduced, and the reliability of the semiconductor integrated circuit device can be improved.

Claims (9)

Forming a semiconductor substrate comprising a lower substrate in a first orientation and an upper substrate in a second orientation, Form an amorphous region on a portion of the semiconductor substrate, wherein a depth of the amorphous region is formed deeper than a depth of the upper substrate, And irradiating a laser to the amorphous region to melt and recrystallize the amorphous region. The method of claim 1, And the recrystallized region is formed in the same orientation as the lower substrate. The method of claim 1, Forming an amorphous region in a portion of the semiconductor substrate includes forming an amorphous region by implanting ions into a portion of the semiconductor substrate. The method of claim 1, Forming an amorphous region in a portion of the semiconductor substrate Forming a plurality of device isolation regions on the semiconductor substrate to define a plurality of active regions separated by the plurality of device isolation regions; Forming a mask pattern which opens only a part of the plurality of active regions, And forming an amorphous region in the open active region by performing an ion implantation process on the active region opened by the mask pattern. The method of claim 4, wherein The ion implantation process is a Pre Amorphization Implantation (PAI) process. The method of claim 4, wherein A method for manufacturing a semiconductor integrated circuit device in which Ge is implanted in the ion implantation step. The method of claim 1, And said semiconductor substrate comprises one or more combinations selected from the group consisting of SiGe and Ge. The method of claim 1, After irradiating a laser to the amorphous region by melting a portion of the amorphous region and recrystallization, And planarizing a portion of an upper surface of the semiconductor substrate. Forming a semiconductor substrate comprising a lower substrate in a first orientation and an upper substrate in a second orientation, Forming a plurality of device isolation regions on the semiconductor substrate to define a plurality of active regions separated by the plurality of device isolation regions; Forming a mask pattern which opens only a part of the plurality of active regions, An ion implantation process is performed on the active region opened by the mask pattern to form an amorphous region in the open active region, but the depth of the amorphous region is formed deeper than the depth of the upper substrate. Irradiating the amorphous region with a laser to melt and recrystallize the amorphous region, but the recrystallized region has the same orientation as the lower substrate, Remove the mask pattern, And planarizing a portion of an upper surface of the semiconductor substrate.

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