JP2007299976A - Process for fabricating semiconductor device - Google Patents

Abstract

Provided is a method of manufacturing a semiconductor device in which the time required for film formation of a first semiconductor layer and a second semiconductor layer can be shortened in the SBSI method.
A first amorphous or polycrystalline structure is formed on a surface region of a single crystal semiconductor substrate.
A step of forming the semiconductor layer 11, a step of forming the second semiconductor layer 12 having an amorphous or polycrystalline structure on the first semiconductor layer 11, and the surface region 2 of the semiconductor substrate 1 from the second semiconductor layer 12. The surface region 2 of the semiconductor substrate 1 and the first semiconductor layer 11 are ion-implanted with Si or Ar.
And the step of amorphizing the second semiconductor layer 12 and amorphization by ion implantation, and then subjecting the semiconductor substrate 1 to heat treatment, the surface region 2 of the semiconductor substrate 1, the first semiconductor layer 11 and the second semiconductor And single crystallizing the layer 12.
[Selection] Figure 1

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique capable of shortening the time required for film formation of a first semiconductor layer and a second semiconductor layer in the SBSI method.

Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. As a method for forming an SOI structure, for example, SiGe / Si is epitaxially grown on a Si substrate, then the SiGe layer is selectively etched away to form a cavity, and then the cavity is filled with an insulating film. There is a method for constructing an SOI structure on a Si substrate. Such a method is called an SBSI method, and is disclosed in, for example, Patent Document 1 and Non-Patent Document 1.
JP 2005-354024 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

In the conventional SBSI method, SiGe / Si is formed by an epitaxial growth method. However, in epitaxial growth, the movement of atoms on the surface becomes free and large, and therefore, in the initial stage of epitaxial growth of SiGe heterocrystals on Si, crystal defects are likely to occur in the process of releasing strain resulting from differences in lattice constants. It was necessary to suppress the generation of crystal defects by keeping the temperature low overall and stopping the movement of atoms. Where SiGe /
When the epitaxial growth of Si is performed at a low temperature, the film formation rate decreases. For this reason, a long time is required for epitaxial growth, resulting in an increase in process cost.

Furthermore, the epitaxial growth temperature of Si is higher than that of SiGe. In order to prevent generation of crystal defects in SiGe and Si, it is necessary to further lower the epitaxial growth temperature of Si of at least several atomic layers on SiGe and to adjust the value to the epitaxial growth temperature of SiGe. For this reason, it takes a long time to epitaxially grow Si, and there is a problem that the process cost further increases.

Accordingly, the present invention has been made in view of such circumstances, and provides a method for manufacturing a semiconductor device in which the time required for film formation of the first semiconductor layer and the second semiconductor layer in the SBSI method can be shortened. With the goal.

[Invention 1] In order to achieve the above object, a manufacturing method of a semiconductor device of Invention 1 includes a step of forming an amorphous or polycrystalline first semiconductor layer on a surface region of a single crystal semiconductor substrate,
Forming an amorphous or polycrystalline second semiconductor layer on the first semiconductor layer; and ion-implanting a predetermined impurity from the second semiconductor layer toward the surface region of the semiconductor substrate, Amorphizing the surface region of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer; and amorphizing by the ion implantation; And a step of single-crystallizing the surface region and the first semiconductor layer and the second semiconductor layer.

With such a configuration, the first semiconductor layer and the second semiconductor layer can be formed not by epitaxial growth but by CVD processing in the SBSI method, so that the time required for film formation can be shortened. Further, when the first semiconductor layer and the second semiconductor layer are single-crystal grown by heat treatment, the atoms on the surface of the single-crystal surface that is solid-phase grown (that is, the single crystal-amorphous interface) Since it is held down by the amorphous layer, it cannot move freely like the outermost atoms. For this reason, even if heat treatment is performed at a higher temperature than the epitaxial growth of SiGe or Si on the outermost surface, almost no crystal defects are generated in the present manufacturing method. Accordingly, the first and second semiconductor stacks made of single crystals can be formed in a short time.

[Invention 2] A method of manufacturing a semiconductor device according to Invention 2 includes a step of forming a first semiconductor layer having an amorphous or polycrystalline structure on a surface region of a single crystal semiconductor substrate, and the semiconductor substrate from above the first semiconductor layer. A step of ion-implanting a predetermined impurity toward the surface region of the semiconductor substrate to make the surface region of the semiconductor substrate and the first semiconductor layer amorphous, and after performing the amorphousization by the ion implantation, Forming a second semiconductor layer having an amorphous structure on the first semiconductor layer; and forming the second semiconductor layer and then subjecting the semiconductor substrate to a heat treatment so that the surface region of the semiconductor substrate and the first semiconductor are formed. And single crystallizing the layer and the second semiconductor layer.

With such a configuration, the first semiconductor layer and the second semiconductor layer can be formed not by epitaxial growth but by CVD processing in the SBSI method, so that the time required for film formation can be shortened. Further, when the first semiconductor layer and the second semiconductor layer are single-crystal grown by heat treatment, the atoms on the surface of the single-crystal surface that is solid-phase grown (that is, the single crystal-amorphous interface) Since it is held down by the amorphous layer, it cannot move freely like the outermost atoms. For this reason, even if heat treatment is performed at a higher temperature than the epitaxial growth of SiGe or Si on the outermost surface, almost no crystal defects are generated in the present manufacturing method. Accordingly, the first and second semiconductor stacks made of single crystals can be formed in a short time.

[Invention 3] In the method of manufacturing a semiconductor device of Invention 3, a step of ion-implanting a predetermined impurity into a single crystal semiconductor substrate to amorphize the surface region of the semiconductor substrate, and amorphization by the ion implantation are performed. A step of forming a first semiconductor layer having an amorphous structure on the surface region of the semiconductor substrate; a step of forming a second semiconductor layer having an amorphous structure on the first semiconductor layer; and the second semiconductor layer. Forming a single crystal of the surface region of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer after the semiconductor substrate is formed. is there.
With such a configuration, the first semiconductor layer and the second semiconductor layer can be formed not by epitaxial growth but by CVD processing in the SBSI method, so that the time required for film formation can be shortened.

[Invention 4] The method for manufacturing a semiconductor device according to Invention 4 is the method for manufacturing a semiconductor device according to any one of Inventions 1 to 3, wherein an insulating film pattern is formed on the semiconductor substrate before forming the first semiconductor layer. And selectively exposing the surface region of the semiconductor substrate from under the insulating film pattern.
In such a configuration, the first semiconductor layer and the second semiconductor layer having a polycrystalline structure are formed on the insulating film pattern, and the region exposed from below the insulating film pattern in the surface region has a single crystal structure. A first semiconductor layer and a second semiconductor layer are formed. That is, a stacked structure including the first semiconductor layer and the second semiconductor layer having a single crystal structure can be selectively formed over the semiconductor substrate.

[Invention 5] A method for manufacturing a semiconductor device according to Invention 5 is the method for manufacturing a semiconductor device according to any one of Inventions 1 to 4, whereby the first semiconductor layer and the second semiconductor layer are monocrystallized. Process,
After single crystallizing the first semiconductor layer and the second semiconductor, the second semiconductor layer and the first semiconductor
Forming a first groove through the semiconductor layer to expose the semiconductor substrate, forming a support in the first groove to support the second semiconductor layer, and after forming the support The step of forming a second groove exposing the first semiconductor layer from below the second semiconductor layer, and the specific etching conditions in which the first semiconductor layer is more easily etched than the second semiconductor layer, Etching the first semiconductor layer through a second groove to form a cavity between the semiconductor substrate and the second semiconductor layer; and forming an insulating layer in the cavity; It is characterized by including.

Here, when the first semiconductor layer is silicon germanium (SiGe) and the second semiconductor layer is silicon (Si), “specific etching conditions” include, for example, wet etching using hydrofluoric acid.
According to the semiconductor device manufacturing method of the fifth aspect of the present invention, the first semiconductor layer and the second semiconductor layer can be formed not by epitaxial growth but by CVD processing in the SBSI method, thereby reducing the time required for film formation. Can do. Therefore, an SOI structure including the semiconductor substrate, the insulating layer, and the single crystal second semiconductor layer can be formed more efficiently and at a lower cost.

[Invention 6] The method for manufacturing a semiconductor device according to Invention 6 is the method for manufacturing a semiconductor device according to any one of Inventions 1 to 5, wherein the first semiconductor layer is silicon germanium (SiGe),
The second semiconductor layer is silicon (Si).
With such a configuration, since the SiGe layer and the Si layer can be formed not by epitaxial growth but by CVD processing in the SBSI method, the time required for film formation can be shortened. Therefore, the SO is composed of a semiconductor substrate, an insulating layer, and a single crystal Si layer.
The I structure can be formed more efficiently and at a lower cost.

[Invention 7] The semiconductor device manufacturing method of Invention 7 is the semiconductor device manufacturing method of any one of Inventions 1 to 6, wherein the impurity used for the ion implantation is Si, Ge, or Ar. It is a feature.

[Invention 8] A method for manufacturing a semiconductor device according to Invention 8 includes a step of forming a first semiconductor layer having an amorphous or polycrystalline structure on a surface region of a single-crystal semiconductor substrate, and an amorphous or polycrystalline structure on the first semiconductor layer. Forming a second semiconductor layer having a crystalline structure, forming a third semiconductor layer having an amorphous or polycrystalline structure on the second semiconductor layer, and forming a second semiconductor layer having an amorphous or polycrystalline structure on the third semiconductor layer. A step of forming four semiconductor layers, ion implantation of a predetermined impurity from above the fourth semiconductor layer toward the surface region of the semiconductor substrate, and the surface region of the semiconductor substrate, the first semiconductor layer, After the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are amorphized, and after the amorphization by the ion implantation,
Applying heat treatment to the semiconductor substrate to monocrystallize the surface region of the semiconductor substrate, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer; After performing the single crystallization by the heat treatment, the fourth semiconductor layer, the third semiconductor layer,
Forming a first groove penetrating the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate; and a support for supporting the second semiconductor layer and the fourth semiconductor layer. A step of forming the first semiconductor layer in a groove, and exposing the third semiconductor layer from below the fourth semiconductor layer and exposing the first semiconductor layer from below the second semiconductor layer after forming the support. A step of forming two grooves, and a specific etching condition in which the first semiconductor layer and the third semiconductor layer are more easily etched than the second semiconductor layer and the fourth semiconductor layer. The first semiconductor layer and the third semiconductor layer are etched to form a first cavity between the semiconductor substrate and the second semiconductor layer, and the second semiconductor layer and the fourth semiconductor layer.
Forming a second cavity between the semiconductor layer and forming a first insulating layer in the first cavity and forming a second insulating layer in the second cavity. It is characterized by.

Here, when the first semiconductor layer and the third semiconductor layer are SiGe and the second semiconductor layer and the fourth semiconductor layer are Si, the “specific etching conditions” include, for example, wet etching using hydrofluoric acid. .
According to the manufacturing method of the semiconductor device of the invention 7, the first semiconductor layer to the fourth semiconductor layer can be formed not by epitaxial growth but by CVD processing in the SBSI method.
The time required for film formation can be shortened. Therefore, the semiconductor substrate, the first insulating layer, the single crystal second semiconductor layer (the second semiconductor layer is used as a back gate electrode or a double gate electrode), the second insulating layer, and the single crystal An SOI structure including the fourth semiconductor layer can be formed more efficiently and at a lower cost.

Embodiments of the present invention will be described below with reference to the drawings.
(1) First Embodiment FIGS. 1A to 11A are plan views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIGS. 1B to 11B. 1A to A1 ′ to A in FIG.
Sectional views taken along the line 11-A11 ′, FIGS. 1C to 11C, respectively.
It is sectional drawing when (a)-FIG. 11 (a) are each cut | disconnected by the B1-B1 '-B11-B11' line | wire.

As shown in FIGS. 1A to 1C, first, an amorphous (that is, amorphous) or polycrystalline (that is, poly) first semiconductor layer 11 is formed on a single crystal semiconductor substrate 1. And the second semiconductor layer 12 having an amorphous or polycrystalline structure are sequentially stacked. The first semiconductor layer 11 and the second semiconductor layer 12 are formed by, for example, a CVD process.
The first semiconductor layer 11 is made of a material having an etching rate (that is, etching rate) higher than that of the semiconductor substrate 1 and the second semiconductor layer 12. Here, the etching rate is shown in FIG.
The etching amount per unit time when forming the cavity 37 shown in FIGS.

1A to 1C, a semiconductor substrate 1, a first semiconductor layer 11, and a second semiconductor layer 12 are used.
Examples of the material include Si, Ge, SiGe, SiC, SiSn, PbS, and GaAs.
A combination selected from InP, GaP, GaN, ZnSe, or the like can be used. For example, the material of the semiconductor substrate 1 is Si, and the material of the first semiconductor layer 11 is Si.
Ge is used, and the material of the second semiconductor layer 12 is Si. The film thicknesses of the first semiconductor layer 11 and the second semiconductor layer 12 are, for example, about 1 to 200 nm.

Next, as shown in FIGS. 1A to 1C, predetermined impurities (elements) are ion-implanted from the second semiconductor layer 12 toward the surface region 2 of the semiconductor substrate 1, so that the semiconductor substrate 1 Surface area 2;
The first semiconductor layer 11 and the second semiconductor layer 12 are all made amorphous.
That is, the first semiconductor layer 11 and the second semiconductor layer 12 are formed in an amorphous or polycrystalline structure by a CVD method. When each of these semiconductor layers is polycrystalline, each semiconductor layer is made amorphous by ion implantation. Moreover, when each of these semiconductor layers is amorphous, each semiconductor layer is made more finely amorphous by ion implantation.

In addition, there may be a case where a native oxide (natural oxide film) remains at the interface between the surface region 2 of the semiconductor substrate 1 and the first semiconductor layer 11, and this native oxide is also mixed by ion implantation. Furthermore, since predetermined impurities reach the surface region 2 of the semiconductor substrate 1, the crystal structure of the surface region 2 is changed from a single crystal to an amorphous state. Therefore, the interface between the amorphous layer and the single crystal layer after implantation can be formed in the bulk of the semiconductor substrate, and a clean interface can be obtained. The predetermined impurity (element) is, for example, silicon (Si), germanium (
Ge) or argon (Ar). The dose of these impurities is, for example, 10 ¹⁵ to 1
It is about 0 ¹⁶ [cm ⁻² ].

After the amorphization by such ion implantation, the semiconductor substrate 1 is subjected to a heat treatment, and the surface region 2 of the semiconductor substrate 1, the first semiconductor layer 11 and the second semiconductor layer 12 are formed into a single crystal by solid layer growth. Turn into. Here, solid phase growth means that the crystal growth is performed while maintaining the solid state without changing the raw material for crystal growth into a liquid or gas state. The interface between the amorphous layer and the single crystal layer (for example, the interface between the amorphized surface region 2 and the non-amorphized single crystal region directly below it in the semiconductor substrate 1) is in a solid, and single crystal growth Since the surface is suppressed by the amorphous layer, the single crystal can be grown without relaxing on the single crystal growth surface (that is, the amorphous / single crystal interface). That is, a single crystal film free from crystal defects can be formed.

In addition, it is preferable to perform this heat processing in inert gas atmosphere, such as Ar and N2, for example. When the material of the semiconductor substrate 1 is single crystal Si, the material of the first semiconductor layer 11 is SiGe, and the material of the second semiconductor layer 12 is Si, the heat treatment temperature is preferably set to 800 ° C. or lower. . Thereby, the diffusion of Ge can be ignored and a flat SiGe / Si interface can be formed.

Next, as shown in FIGS. 2A to 2C, a base oxide film 21 is formed on the surface of the second semiconductor layer 12 by thermal oxidation of the second semiconductor layer 12. Then, an antioxidant film 23 is formed on the entire surface of the base oxide film 21 by a method such as CVD. The antioxidant film 23 is, for example, a silicon nitride film. When the antioxidant film 23 is a silicon nitride film, it can function as a stopper layer for a planarization process by CMP (Chemical Mechanical Polishing) in addition to the function of preventing the second semiconductor layer 12 from being oxidized.

Here, the base oxide film 21 and the antioxidant film 23 are formed after single crystallization by heat treatment.
However, the order of the heat treatment and film formation is not limited to this. For example, the base oxide film 21 is formed on the amorphous or polycrystalline second semiconductor layer 12.
After the formation of the anti-oxidation film 23, single crystallization may be performed by heat treatment. Even with such a configuration, the surface region of the semiconductor substrate 1 and the first semiconductor layer 11 and the second semiconductor layer 12 can all be single-crystallized.

Next, as shown in FIGS. 3A to 3C, the anti-oxidation film 23, the base oxide film 21, the second semiconductor layer 12, and the first semiconductor layer 11 are formed using a photolithography technique and an etching technique.
Then, a groove 31 exposing the surface of the semiconductor substrate 1 is formed. In the etching step for forming the groove 31, the etching may be stopped on the surface of the semiconductor substrate 1, or the semiconductor substrate 1 may be over-etched to form a recess in the semiconductor substrate 1. Further, the arrangement position of the groove 31 corresponds to a part of the element isolation region in the second semiconductor layer 12.

Next, as shown in FIGS. 4A to 4C, the first semiconductor layer 11 is etched through the groove 31 to form a recess 33 in the inner wall of the groove 31. The semiconductor substrate 1 and the second substrate
When the semiconductor layer 12 is Si and the first semiconductor layer 11 is SiGe, for example, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 11. Thereby, it is possible to cut the first semiconductor layer 11 while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 12.

Next, as shown in FIGS. 5A to 5C, a support body 41 embedded in the groove 31 is formed so as to cover the entire surface of the substrate by a method such as CVD. Here, the support body 41 has a groove 3.
1 is also formed on the side walls of the first semiconductor layer 11 and the second semiconductor layer 12, and the recess 33 facing the inner wall of the groove 31 is buried. That is, the second semiconductor layer 12 is supported by the support 41.
It is supported so as to be sandwiched not only from the side but also from the top and bottom. Thereby, the support body 41 can support the second semiconductor layer 12 on the semiconductor substrate 1 when the first semiconductor layer 11 is removed.

Note that the support body 41 formed so as to cover the entire substrate needs to support the second semiconductor layer 12 while suppressing the bending of the second semiconductor layer 12 and maintaining the flatness. Therefore, it is preferable to set the film thickness to 400 nm or more in order to ensure the mechanical strength. Moreover, as a material of the support body 41, for example, an insulator such as a silicon oxide film is used.

Next, as illustrated in FIGS. 6A to 6C, the support 41, the antioxidant film 23, the base oxide film 21, the second semiconductor layer 12, and the first semiconductor layer are formed using a photolithography technique and an etching technique. By patterning 11, a groove 35 exposing the surface of the semiconductor substrate 1 is formed. In the etching process for forming the groove 35, the etching may be stopped on the surface of the semiconductor substrate 1, or the semiconductor substrate 1 may be over-etched to form a recess in the semiconductor substrate 1. Further, the position of the groove 35 corresponds to a part of the element isolation region in the second semiconductor layer 12, and the direction thereof is, for example, a direction substantially orthogonal to the formation direction of the previously formed groove in plan view.

Next, as shown in FIGS. 7A to 7C, the first semiconductor layer 11 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 11 through the groove 35. A cavity 37 is formed between the substrate 1 and the second semiconductor layer 12.
Here, since the support body 41 is provided in the groove 31, the second semiconductor layer 12 can be supported on the semiconductor substrate 1 even when the first semiconductor layer 11 is removed. Further, since the groove 35 is provided separately from the groove 31, it becomes possible to contact the etching gas or the etching liquid with the first semiconductor layer 11 under the second semiconductor layer 12. For this reason, it is possible to form the cavity 37 between the semiconductor substrate 1 and the second semiconductor layer 12 without impairing the quality of the second semiconductor layer 12.

When the semiconductor substrate 1 and the second semiconductor layer 12 are Si and the first semiconductor layer 11 is SiGe, for example, hydrofluoric acid is used as the etchant for the first semiconductor layer 11. Thereby, it is possible to remove the first semiconductor layer 11 while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 12.

Next, as shown in FIGS. 8A to 8C, the semiconductor substrate 1 is thermally oxidized to form an insulating film 43 on at least the wall surface of the cavity portion 37. As shown in FIGS. 9A to 9C, CV
An insulating film 45 is formed on the entire surface of the substrate by a method such as D to fill the trench. This insulating film 45
By the formation, the filling of the cavity 37 with the insulating film 43 is also complemented. Insulating film 4
3 is a silicon oxide film when the semiconductor substrate 1 and the second semiconductor layer 12 are Si.
Further, as a material of the insulating film 45 formed by a method such as CVD, for example, a silicon nitride film or the like may be used in addition to the silicon oxide film.

Next, the insulating film covering the entire surface of the substrate is planarized by, for example, CMP, and the insulating film 45 is removed from the antioxidant film 23. As described above, when the antioxidant film 23 is a silicon nitride film, the antioxidant film 23 functions as a stopper layer for a planarization process by CMP. Next, the antioxidant film 23 and the base oxide film 21 are removed by etching. When the antioxidant film 23 is a silicon nitride film, for example, hot phosphoric acid is used as an etchant, and the base oxide film 21 is used.
When is a silicon oxide film, for example, dilute hydrofluoric acid is used as an etchant. Thereby, as shown in FIGS. 10A to 10C, the surface of the second semiconductor layer 12 is exposed.

Next, as shown in FIGS. 11A to 11C, the surface of the second semiconductor layer 12 is thermally oxidized to form the gate insulating film 51 on the surface of the second semiconductor layer 12. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 12 on which the gate insulating film 51 is formed by a method such as CVD. Furthermore, the gate electrode 53 is formed on the second semiconductor layer 12 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

Next, using the gate electrode 53 as a mask, impurities such as As, P, and B are added to the second semiconductor layer 12.
By implanting ions therein, an LDD layer composed of low-concentration impurity introduction layers disposed on both sides of the gate electrode 53 is formed in the second semiconductor layer 12. Then, an insulating layer is formed on the second semiconductor layer 12 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 55 are formed on the side walls. Further, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 12 using the gate electrode 53 and the sidewall 55 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 55. Source layer 57 consisting of layers
The drain layer 58 is formed in the second semiconductor layer 12.

As described above, according to the first embodiment of the present invention, the first semiconductor layer 11 and the second semiconductor layer 12 can be formed not by epitaxial growth but by CVD in the SBSI method. Time can be shortened. Accordingly, an SOI structure including the semiconductor substrate 1, the insulating film 43, and the single crystal second semiconductor layer 12 can be formed more efficiently and at a lower cost.

That is, in the present invention, an amorphous or polycrystalline SiGe thin film is formed on the surface of a Si substrate (or an Si substrate patterned with an insulating layer) by CVD, and further amorphous or polycrystalline Si is formed by CVD. Next, Si or Ar ions are implanted to make the surface of the Si substrate amorphous. Thereafter, solid phase growth is performed by heat treatment to form single crystal SiGe and single crystal Si on the Si substrate.

According to the present invention, since SiGe and Si are formed by a CVD process, film growth is fast, batch processing is possible, and the film formation throughput is significantly improved. In addition, S in the SiGe lower layer
For the amorphization of the surface of the i substrate, a dose of 10 ¹⁵ -10 ¹⁶ is sufficient, and single crystal SiG
e and single crystal Si can be produced at low cost. As for solid phase growth, the interface between the amorphous layer and the single crystal layer is in the solid (not the surface), and the single crystal growth surface is suppressed by the amorphous layer. A single crystal layer of Si substrate / SiGe / Si can be formed without relaxing at the crystal interface. 800 ° C
In the following heat treatment, the diffusion of Ge can be almost ignored and a flat SiGe / Si interface can be formed.

(2) Second Embodiment FIGS. 12A to 23A are plan views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention, and FIGS. 12B to 23B. FIG. 12 (a) to FIG.
Sectional drawing when cut along lines 12 'to A23-A23', FIGS. 12 (c) to 23 (
FIG. 12C is a cross-sectional view taken along lines B12-B12 ′ to B23-B23 ′ of FIGS. 12A to 23A. In FIG. 23A, illustration of the interlayer insulating film 160 is omitted.

As shown in FIGS. 12A to 12C, first, an amorphous or polycrystalline first semiconductor layer 111 and an amorphous or polycrystalline second layer are formed on a single crystal semiconductor substrate 101.
The semiconductor layer 112 is sequentially stacked. Next, an amorphous or polycrystalline third semiconductor layer 113 and an amorphous or polycrystalline fourth semiconductor layer 114 are sequentially stacked on the second semiconductor layer 112. The first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 11
The third and fourth semiconductor layers 114 are formed by, for example, a CVD process.

The first semiconductor layer 111 and the third semiconductor layer 113 include the semiconductor substrate 101 and the second semiconductor layer 11.
A material having an etching rate (that is, an etching rate) larger than that of the second and fourth semiconductor layers 114 is used. Here, the etching rate is the cavity portion 137 shown in FIGS.
138 is an etching amount per unit time.

12A to 12C, the materials of the semiconductor substrate 101, the first semiconductor layer 111, the second semiconductor layer 112, the third semiconductor layer 113, and the fourth semiconductor layer 114 are, for example, Si,
A combination selected from Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or the like can be used. For example, the material of the semiconductor substrate 101 is Si, and the material of the first semiconductor layer 111 and the third semiconductor layer 113 is SiG.
e, and the material of the second semiconductor layer 112 and the fourth semiconductor layer 114 is Si. The film thicknesses of the first semiconductor layer 111, the second semiconductor layer 112, the third semiconductor layer 113, and the fourth semiconductor layer 114 are as follows:
For example, it is about 1 to 200 nm.

Next, as shown in FIGS. 12A to 12C, the semiconductor substrate 10 is formed on the fourth semiconductor layer 114.
Predetermined impurities are ion-implanted toward one surface region 102, and the surface region 102 of the semiconductor substrate 101, the first semiconductor layer 111, the second semiconductor layer 112, the third semiconductor layer 113, and the fourth semiconductor layer All of 114 is made amorphous.
That is, the first semiconductor layer 111, the second semiconductor layer 112, the third semiconductor layer 113, and the fourth semiconductor layer 114 are formed in an amorphous or polycrystalline structure by a CVD method. When each of these semiconductor layers is polycrystalline, each semiconductor layer is made amorphous by ion implantation. Moreover, when each of these semiconductor layers is amorphous, each semiconductor layer is made more finely amorphous by ion implantation.

In addition, there may be a case where a native oxide (natural oxide film) remains at the interface between the semiconductor substrate 101 and the first semiconductor layer 111. This native oxide is also mixed by ion implantation. Furthermore, since predetermined impurities reach the surface region 102 of the semiconductor substrate 101, the crystal structure of the surface region 102 changes from single crystal to amorphous. The predetermined impurity is, for example, silicon (Si), germanium (Ge), or argon (Ar). The dose of these impurities is, for example, about 10 ¹⁵ to 10 ¹⁶ [cm ⁻² ].

After performing the amorphization by such ion implantation, the semiconductor substrate 101 is subjected to a heat treatment, and the surface region 102 of the semiconductor substrate 101, the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer. 113 and the fourth semiconductor layer 114 are single-crystallized by solid layer growth.
This heat treatment is preferably performed, for example, in an inert gas atmosphere such as Ar or N2. Further, the material of the semiconductor substrate 101 is single crystal Si, and the first semiconductor layer 111 and the third semiconductor layer 11.
When the third material is SiGe and the material of the second semiconductor layer 112 and the fourth semiconductor layer 114 is Si, the heat treatment temperature is preferably set to 800 ° C. or lower. Thereby, the diffusion of Ge can be ignored and a flat SiGe / Si interface can be formed.

Next, as shown in FIGS. 13A to 13C, a base oxide film 121 is formed on the surface of the fourth semiconductor layer 114 by thermal oxidation of the fourth semiconductor layer 114. And by methods such as CVD,
An antioxidant film 123 is formed on the entire surface of the base oxide film 121. The antioxidant film 123 is, for example, a silicon nitride film. When the antioxidant film 123 is a silicon nitride film, in addition to the function of preventing the fourth semiconductor layer 114 from being oxidized, it can also function as a stopper layer for a planarization process by CMP (Chemical Mechanical Polishing).

Here, the base oxide film 121 and the antioxidant film 1 are formed after single crystallization by heat treatment.
However, the order of these processes is not limited to this. For example, after the base oxide film 121 and the antioxidant film 123 are formed over the fourth semiconductor layer 114 having an amorphous or polycrystalline structure, single crystallization may be performed by heat treatment. Even in such a configuration, the surface region 102 of the semiconductor substrate 101, the first semiconductor layer 111, the second semiconductor layer 112, the third semiconductor layer 113, and the fourth semiconductor layer 114 are all monocrystallized. Is possible.

Next, as shown in FIGS. 14A to 14C, using an photolithography technique and an etching technique, the antioxidant film 123, the base oxide film 121, the fourth semiconductor layer 114, the third semiconductor layer 113, the first By patterning the two semiconductor layers 112 and the first semiconductor layer 111,
A groove 131 exposing the surface of the semiconductor substrate 101 is formed. In the etching process for forming the groove 131, the etching may be stopped on the surface of the semiconductor substrate 101,
The semiconductor substrate 101 may be over-etched to form a recess in the semiconductor substrate 101. In addition, the arrangement position of the groove 131 corresponds to a part of the element isolation region in the fourth semiconductor layer 114.

Next, as shown in FIGS. 15A to 15C, the first semiconductor layer 111 and the third semiconductor layer 113 are etched through the groove 131, thereby forming the recesses 133, 13 on the inner wall of the groove 131.
4 is formed. When the semiconductor substrate 101, the second semiconductor layer 112, and the fourth semiconductor layer 114 are Si, and the first semiconductor layer 111 and the third semiconductor layer 113 are SiGe, the first semiconductor layer 11
As the etchant for the first and third semiconductor layers 113, for example, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used. Accordingly, the first semiconductor layer 111 and the third semiconductor layer 11 are suppressed while suppressing overetching of the semiconductor substrate 101, the second semiconductor layer 112, and the fourth semiconductor layer 114.
3 can be shaved.

Next, as shown in FIGS. 16A to 16C, a support 141 embedded in the groove 131 is formed so as to cover the entire surface of the substrate by a method such as CVD. Here, the support 141
Are the first semiconductor layer 111, the second semiconductor layer 112, and the third semiconductor layer 113 in the groove 131.
And the recesses 133 and 13 formed on the side walls of the fourth semiconductor layer 114 and facing the inner wall of the groove 131.
4 is embedded. In other words, the second semiconductor layer 112 and the fourth semiconductor layer 114 are formed of the support 14.
1 is supported so that it may be pinched | interposed not only from the side surface but from an up-down direction. This
The support 141 can support the second semiconductor layer 112 and the fourth semiconductor layer 114 on the semiconductor substrate 101 when the first semiconductor layer 111 and the third semiconductor layer 113 are removed.

Note that the support 141 formed so as to cover the entire substrate includes the second semiconductor layer 112 and the fourth
It is necessary to support the fourth semiconductor layer 114 while maintaining the flatness by suppressing the bending or the like of the semiconductor layer 114. Therefore, it is preferable to set the film thickness to 400 nm or more in order to ensure the mechanical strength. In addition, as a material of the support 141, for example, an insulator such as a silicon oxide film is used.

Next, as shown in FIGS. 17A to 17C, the support 141, the antioxidant film 123, the base oxide film 121, and the fourth semiconductor layer 114 are used by using a photolithography technique and an etching technique.
Then, by patterning the third semiconductor layer 113, the second semiconductor layer 112, and the first semiconductor layer 111, a groove 135 exposing the surface of the semiconductor substrate 101 is formed. Groove 135
In the etching step for forming the semiconductor substrate 101, the etching may be stopped on the surface of the semiconductor substrate 101, or the semiconductor substrate 101 may be over-etched to form a recess in the semiconductor substrate 101. In addition, the position of the groove 135 corresponds to a part of the element isolation region in the fourth semiconductor layer 114, and the direction thereof is, for example, a direction substantially orthogonal to the formation direction of the previously formed groove in plan view.

Next, as shown in FIGS. 18A to 18C, an etching gas or an etching solution is brought into contact with the first semiconductor layer 111 and the third semiconductor layer 113 through the groove 135, so that the first
The semiconductor layer 111 and the third semiconductor layer 113 are removed by etching to form a cavity 137 between the semiconductor substrate 101 and the second semiconductor layer 112, and between the second semiconductor layer 112 and the fourth semiconductor layer 114. A cavity 138 is formed.

Here, since the support 141 is provided in the groove 131, the second semiconductor layer 112 and the fourth semiconductor layer 114 can be used as semiconductors even when the first semiconductor layer 111 and the third semiconductor layer 113 are removed. It can be supported on the substrate 101. In addition to the groove 131, the groove 1
By providing 35, the first semiconductor layer 111 and the third semiconductor layer 113 can be brought into contact with an etching gas or an etching solution. For this reason, the second semiconductor layer 1
The cavity 137 is formed between the semiconductor substrate 101 and the second semiconductor layer 112 without impairing the quality of the 12th and fourth semiconductor layers 114, and the second semiconductor layer 112 and the fourth semiconductor layer 1 are formed.
A cavity 138 can be formed between the first and second cavities 14.

Note that when the semiconductor substrate 101, the second semiconductor layer 112, and the fourth semiconductor layer 114 are Si, and the first semiconductor layer 111 and the third semiconductor layer 113 are SiGe, an etching solution for the first semiconductor layer 111 and the third semiconductor layer 113 is used. For example, hydrofluoric acid is used. Thereby, the semiconductor substrate 1
01, while suppressing over-etching of the second semiconductor layer 112 and the fourth semiconductor layer 114,
The first semiconductor layer 111 and the third semiconductor layer 113 can be removed.

Next, as shown in FIGS. 19A to 19C, the semiconductor substrate 101 is thermally oxidized to form the cavity 1.
An insulating film 143 is formed on at least the wall surface of 37, and an insulating film 144 is formed on at least the wall surface of the cavity 138. Then, as shown in FIGS. 20A to 20C, an insulating film 145 is formed on the entire surface of the substrate by a method such as CVD, and the trench 135 is buried. This insulating film 14
5, the filling of the cavities 137 and 138 with the insulating films 143 and 144 is also supplemented. The materials of the insulating films 143 and 144 are the semiconductor substrate 101 and the second semiconductor layer 112.
When the fourth semiconductor layer 114 is Si, a silicon oxide film is formed. Further, as a material of the insulating film 145 formed by a method such as CVD, for example, a silicon nitride film or the like may be used in addition to the silicon oxide film.

Next, the insulating film covering the entire surface of the substrate is planarized by, for example, CMP, and the insulating film 145 is removed from the antioxidant film 123. As described above, when the antioxidant film 123 is a silicon nitride film, the antioxidant film 123 functions as a stopper layer for a planarization process by CMP. Next, the antioxidant film 123 and the base oxide film 121 are removed by etching. When the antioxidant film 123 is a silicon nitride film, for example, hot phosphoric acid is used as an etchant,
When the base oxide film 121 is a silicon oxide film, for example, dilute hydrofluoric acid is used as an etching solution. Thereby, as shown in FIGS. 21A to 21C, the surface of the fourth semiconductor layer 114 is exposed.

Here, after removing the antioxidant film 123, an impurity such as phosphorus or boron is ion-implanted into the second semiconductor layer 112. Accordingly, the second semiconductor layer 112 can be made conductive, and the second semiconductor layer 112 can be used as one of the back gate electrode and the double gate electrode. When the p-type layer and the n-type layer are separately formed in the second semiconductor layer 112, ion implantation is selectively performed using a resist pattern or the like. In the case where the p-type layer and the n-type layer are not separately formed (that is, only the p-type layer or the n-type layer is formed on the second semiconductor layer 112 over the entire substrate), the resist pattern Without being formed, phosphorus or boron ions are implanted into the entire surface of the substrate.

Note that this ion implantation step is preferably performed before the base oxide film 121 is removed. Thereby, crystal defects near the surface of the fourth semiconductor layer 114 can be reduced as much as possible. Furthermore, in this ion implantation step, it is preferable to adjust the implantation energy so that the impurity implantation peak is at the interface between the insulating film 143 and the second semiconductor layer 112. Thus, the amount of impurities introduced into the insulating film 144 can be reduced as much as possible.

Next, as shown in FIGS. 22A to 22C, the fourth semiconductor layer 114 is patterned by using a photolithography technique and an etching technique to expose a part of the upper surface of the insulating film 144. 147 is formed in the fourth semiconductor layer 114. Next, the fourth semiconductor layer 1
14 is performed on the surface of the fourth semiconductor layer 114 by performing thermal oxidation of the surface of the gate insulating film 151.
Form. Then, a polycrystalline silicon layer is formed on the fourth semiconductor layer 114 on which the gate insulating film 151 is formed by a method such as CVD. Further, the gate electrode 153 is formed on the fourth semiconductor layer 114 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

Next, using the gate electrode 153 as a mask, impurities such as As, P, and B are added to the fourth semiconductor layer 1.
14 is formed in the fourth semiconductor layer 114 by LDD layers made of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 153. Then, an insulating layer is formed on the fourth semiconductor layer 114 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE, whereby the gate electrode 153 is formed.
Sidewalls 155 are formed on the side walls. Further, impurities such as As, P, and B are ion-implanted into the fourth semiconductor layer 114 using the gate electrode 153 and the sidewall 155 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 155. A source layer 157 and a drain layer 158 made of layers are formed in the fourth semiconductor layer 114.

Thereafter, as shown in FIGS. 23A to 23C, the gate electrode 1 is formed by a method such as CVD.
An interlayer insulating layer 160 is deposited on 53. Then, using the photolithography technique and the etching technique, the interlayer insulating film 160 and the insulating film 144 immediately below the opening 147 are etched and removed, and the source layer 157, the drain layer 158, and the second semiconductor layer 112 are removed. Contact holes are formed on the top and the bottom, respectively. Then, after forming and patterning a metal film, the source contact electrode 171 and the drain contact electrode 172, and the gate contact electrode 1
73 and a back gate contact electrode 174 are formed. Source contact electrode 171
The drain contact electrode 172 and the gate contact electrode 173 are electrodes embedded in the interlayer insulating layer 160 and connected to the source layer 157, the drain layer 158, and the gate electrode 153, respectively. Further, the back gate contact electrode 174 is formed of the interlayer insulating layer 1
60 and an electrode embedded in the insulating film 144 and connected to the second semiconductor layer (that is, the back gate electrode) 112 through the opening 147.

Thus, according to the second embodiment of the present invention, the first semiconductor layer 111 in the SBSI method.
Since the second semiconductor layer 112, the third semiconductor layer 113, and the fourth semiconductor layer 114 can be formed not by epitaxial growth but by CVD processing, the time required for film formation can be shortened. Therefore, the semiconductor substrate 101, the first insulating film 143, and the single crystal second
An SOI structure including a semiconductor layer 112 (the second semiconductor layer 112 is used as a back gate electrode or a double gate electrode 153), a second insulating film 144, and a single crystal fourth semiconductor layer 114 is further provided. It can be formed efficiently and at a lower cost.

(3) Third Embodiment FIGS. 24A to 24C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. In the third embodiment, a case (part 1) in which the procedure for single-crystallizing the second semiconductor layer and the first semiconductor layer in the first embodiment is described will be described. In the third embodiment, parts having the same configuration as in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
As shown in FIG. 24A, first, the first semiconductor layer 11 having an amorphous or polycrystalline structure is formed on the surface region 2 of the single crystal semiconductor substrate 1. The semiconductor substrate 1 is, for example, silicon (Si), and the first semiconductor layer 11 is, for example, silicon germanium (SiGe).

Next, as shown in FIG. 24B, the surface region 2 of the semiconductor substrate 1 is formed on the first semiconductor layer 11.
Predetermined impurities are ion-implanted toward
Are all made amorphous. The predetermined impurity is, for example, silicon (Si), germanium (Ge), or argon (Ar). The dose amount of these impurities is, for example, 10 ¹⁵ to 10 ^16.
It is about [cm ^-2 ]. Then, after amorphization by ion implantation, the second semiconductor layer 12 having an amorphous structure is formed on the first semiconductor layer 11.

Here, unlike the first embodiment, the crystal structure of the second semiconductor layer 12 is limited to amorphous. The second semiconductor layer 12 is, for example, silicon (Si). Thereafter, the semiconductor substrate 1 is subjected to a heat treatment, and the surface region 2 of the semiconductor substrate 1 and the first semiconductor layer 11 as shown in FIG.
The second semiconductor layer 12 is monocrystallized by solid layer growth.
With such a configuration, the first semiconductor layer 11 is formed by the SBSI method as in the first embodiment.
And the second semiconductor layer 12 can be formed not by epitaxial growth but by CVD. Accordingly, the time required for forming the film for forming the single crystal first semiconductor layer and the single crystal second semiconductor layer can be shortened, and the semiconductor substrate 1, the insulating film 43, and the single crystal second semiconductor are formed. The SOI structure including the layer 12 can be formed more efficiently and at a lower cost.

(4) Fourth Embodiment FIGS. 25A to 25C are cross-sectional views showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. In the fourth embodiment, a case (part 2) in which the procedure for single-crystallizing the second semiconductor layer and the first semiconductor layer in the first embodiment is replaced will be described. In the fourth embodiment, parts having the same configuration as in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 25A, first, a predetermined impurity is ion-implanted toward the surface region 2 of the single crystal semiconductor substrate 1 to make the entire surface region 2 amorphous. The semiconductor substrate 1 is, for example, silicon (Si). The predetermined impurity is, for example, silicon (Si),
Germanium (Ge) or argon (Ar). The dose of these impurities is, for example, 1
It is about 0 ¹⁵ to 10 ¹⁶ [cm ⁻² ].

Next, as shown in FIG. 25B, the first semiconductor layer 11 having an amorphous structure is formed on the surface region 2 of the semiconductor substrate 1, and the second semiconductor layer having the amorphous structure is formed on the first semiconductor layer 11.
The semiconductor layer 12 is formed. Here, unlike the first embodiment, the crystal structures of the first semiconductor layer 11 and the second semiconductor layer 12 are both limited to amorphous. The first semiconductor layer 11 is, for example, silicon germanium (SiGe), and the second semiconductor layer 12 is, for example, silicon (Si).
It is. Thereafter, the semiconductor substrate 1 is subjected to heat treatment, and as shown in FIG. 25C, the surface region 2 of the semiconductor substrate 1, the first semiconductor layer 11 and the second semiconductor layer 12 are monocrystallized by solid layer growth.

With such a configuration, the first semiconductor layer 11 is formed by the SBSI method as in the first embodiment.
And the second semiconductor layer 12 can be formed not by epitaxial growth but by CVD. Accordingly, the time required for forming the film for forming the single crystal first semiconductor layer and the single crystal second semiconductor layer can be shortened, and the semiconductor substrate 1, the insulating film 43, and the single crystal second semiconductor are formed. The SOI structure including the layer 12 can be formed more efficiently and at a lower cost.

In the fourth embodiment, ion implantation for amorphization is performed in the first semiconductor layer 1.
1, the semiconductor substrate 1 is made of Si, and the first semiconductor layer 11 is S
In the case of iGe, Ge in SiGe is not pushed by ion-implanted atoms (for example, Si or Ar) and blown toward the Si substrate. Therefore, G on Si substrate
It is easy to keep the e concentration low, and the SiGe / Si interface can be formed more flatly.

(5) Fifth Embodiment FIGS. 26A to 26C are cross-sectional views showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. In the fifth embodiment, a method for selectively forming a single crystal first semiconductor layer and a single crystal second semiconductor layer in a surface region of a semiconductor substrate in the first embodiment will be described. In the fifth embodiment, parts having the same configurations as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 26A, first, an insulating film pattern 3 is formed on a single crystal semiconductor substrate 1.
Form. The insulating film pattern 3 selectively covers the surface region 2 of the semiconductor substrate 1 (that is, there are a covered portion and a non-covered portion). The semiconductor substrate 1 is, for example, silicon (
Si), and the insulating film pattern 3 is, for example, a silicon oxide film (SiO2). The thickness of the insulating film pattern 3 is, for example, several tens to several hundreds [nm].

Next, as shown in FIG. 26B, an amorphous or polycrystalline first semiconductor layer 11 and an amorphous or polycrystalline second semiconductor layer 12 are sequentially stacked on the entire upper surface of the semiconductor substrate 1. . The first semiconductor layer 11 and the second semiconductor layer 12 are formed by, for example, a CVD process. First
The semiconductor layer 11 is, for example, silicon germanium (SiGe), and the second semiconductor layer 12 is silicon (Si).

Next, as shown in FIG. 26B, the surface region 2 of the semiconductor substrate 1 is formed on the second semiconductor layer 12.
A predetermined impurity is ion-implanted to make the first semiconductor layer 11 and the second semiconductor layer 12 amorphous, and the portion of the surface region 2 exposed from below the insulating film pattern 3. Thereafter, the semiconductor substrate 1 is subjected to a heat treatment for single crystallization. As shown in FIG. 26C, the first semiconductor layer 11 and the second semiconductor layer 12 having a polycrystalline structure are formed on the insulating film pattern 3 by this heat treatment, and the insulating film pattern 3 in the surface region 2 is formed. In a region exposed from below, a first semiconductor layer 11 and a second semiconductor layer 12 having a single crystal structure are formed. That is, in a Si substrate having an insulating film pattern, a polycrystalline Si / SiGe layer is formed on the insulating film pattern, and single crystal SiGe / Si is formed only on the exposed surface of the Si substrate.

In the SBSI method, single crystal SiGe, polycrystalline Si, and polycrystalline SiGe are selectively removed at the time of selective etching for forming a cavity under the Si layer, and single crystal Si has a low etching rate. It remains on the Si substrate. Therefore, by using the insulating film pattern,
It is possible to realize a single crystal Si / SiGe laminated structure at a specific position on the Si substrate at low cost. Therefore, it is possible to provide a semiconductor device having an SOI structure at low cost.

FIG. 3 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 1). FIG. 6 is a diagram (No. 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. 3A and 3B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 3). 4A and 4B are diagrams illustrating the method for fabricating a semiconductor device according to the first embodiment (No. 4). FIG. 5 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 5). 6A and 6B are diagrams illustrating the method for manufacturing a semiconductor device according to the first embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 8). FIG. 9 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 9). FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the first embodiment (No. 10). FIG. 11 is a view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment (the 1). FIG. 6 is a view (No. 2) showing the method for manufacturing a semiconductor device according to the second embodiment. FIG. 9 is a diagram (No. 3) for illustrating a method for manufacturing a semiconductor device according to the second embodiment. FIG. 8 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 6 is a diagram (No. 5) for explaining a method for manufacturing a semiconductor device according to the second embodiment; FIG. 6 illustrates a method for manufacturing a semiconductor device according to the second embodiment (No. 6). FIG. 7 is a view showing the method for manufacturing a semiconductor device according to the second embodiment (No. 7). FIG. 8 is a view showing the method for manufacturing a semiconductor device according to the second embodiment (No. 8). FIG. 9 is a view showing a method for manufacturing a semiconductor device according to the second embodiment (No. 9). FIG. 10 is a view showing a method for manufacturing a semiconductor device according to the second embodiment (No. 10). FIG. 11 is a view showing a method for fabricating a semiconductor device according to the second embodiment (No. 11). FIG. 12 is a view showing a method for producing a semiconductor device according to the second embodiment (No. 12). FIG. 6 is a view showing a method for manufacturing a semiconductor device according to a third embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment. FIG. 6 is a view showing a method for manufacturing a semiconductor device according to a fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 Semiconductor substrate 2,102 Surface region, 11, 111 1st semiconductor layer, 12
, 112 Second semiconductor layer, 113 Third semiconductor layer, 114 Fourth semiconductor layer, 21, 121
Base oxide film, 23, 123 Antioxidation film, 31, 131 Groove (first groove), 33, 133
, 134 recess, 35, 135 groove (second groove), 37 137, 138 cavity, 43, 1
43, 144 Insulating film (insulating layer), 51, 151 Gate insulating film, 53, 153 Gate electrode, 55, 155 Side wall, 57, 157 Source layer, 58, 158 Drain layer, 147 Opening, 160 Interlayer insulating film, 171 Source contact electrode, 172
Drain contact electrode, 173 Gate contact electrode, 174 Back gate contact electrode

Claims (8)

Forming an amorphous or polycrystalline first semiconductor layer on a surface region of a single crystal semiconductor substrate;
Forming an amorphous or polycrystalline second semiconductor layer on the first semiconductor layer;
A step of ion-implanting a predetermined impurity from above the second semiconductor layer toward the surface region of the semiconductor substrate to amorphize the surface region of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer; When,
A heat treatment is performed on the semiconductor substrate after the amorphousization by the ion implantation,
And a step of single-crystallizing the surface region of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer. Forming an amorphous or polycrystalline first semiconductor layer on a surface region of a single crystal semiconductor substrate;
A step of ion-implanting a predetermined impurity from above the first semiconductor layer toward the surface region of the semiconductor substrate to amorphize the surface region of the semiconductor substrate and the first semiconductor layer;
Forming a second semiconductor layer having an amorphous structure on the first semiconductor layer after amorphization by the ion implantation;
After the second semiconductor layer is formed, the semiconductor substrate is subjected to a heat treatment to monocrystallize the surface region of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer. A method of manufacturing a semiconductor device. A step of ion-implanting predetermined impurities into a single-crystal semiconductor substrate to amorphize the surface region of the semiconductor substrate;
Forming a first semiconductor layer having an amorphous structure on the surface region of the semiconductor substrate after performing the amorphization by the ion implantation;
Forming an amorphous second semiconductor layer on the first semiconductor layer;
After the second semiconductor layer is formed, the semiconductor substrate is subjected to a heat treatment to monocrystallize the surface region of the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer. A method of manufacturing a semiconductor device. Forming an insulating film pattern on the semiconductor substrate and selectively exposing the surface region of the semiconductor substrate from under the insulating film pattern before forming the first semiconductor layer. A method for manufacturing a semiconductor device according to any one of claims 1 to 3. Performing the method of manufacturing a semiconductor device according to any one of claims 1 to 4 to monocrystallize the first semiconductor layer and the second semiconductor layer;
Forming a first groove that exposes the semiconductor substrate through the second semiconductor layer and the first semiconductor layer after the first semiconductor layer and the second semiconductor are monocrystallized;
Forming a support in the first groove for supporting the second semiconductor layer;
A second layer that exposes the first semiconductor layer from under the second semiconductor layer after forming the support;
Forming a groove;
The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. Forming a cavity between the layers;
And a step of forming an insulating layer in the cavity. 6. The semiconductor device manufacturing method according to claim 1, wherein the first semiconductor layer is silicon germanium (SiGe), and the second semiconductor layer is silicon (Si). Method. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity used for the ion implantation is Si, Ge, or Ar. Forming an amorphous or polycrystalline first semiconductor layer on a surface region of a single crystal semiconductor substrate;
Forming an amorphous or polycrystalline second semiconductor layer on the first semiconductor layer;
Forming an amorphous or polycrystalline third semiconductor layer on the second semiconductor layer;
Forming an amorphous or polycrystalline fourth semiconductor layer on the third semiconductor layer;
A predetermined impurity is ion-implanted from above the fourth semiconductor layer toward the surface region of the semiconductor substrate, and the surface region of the semiconductor substrate, the first semiconductor layer, the second semiconductor layer, Amorphizing the third semiconductor layer and the fourth semiconductor layer;
After the amorphization by the ion implantation, the semiconductor substrate is subjected to a heat treatment, and the surface region of the semiconductor substrate, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, Single crystallizing the fourth semiconductor layer;
After performing the single crystallization by the heat treatment, the fourth semiconductor layer, the third semiconductor layer,
Forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate;
Forming a support in the first groove to support the second semiconductor layer and the fourth semiconductor layer;
Forming a second groove exposing the third semiconductor layer from below the fourth semiconductor layer and exposing the first semiconductor layer from below the second semiconductor layer after forming the support;
The first semiconductor layer and the third semiconductor layer may be more easily etched than the second semiconductor layer and the fourth semiconductor layer under specific etching conditions via the second groove. By etching the third semiconductor layer, a first cavity is formed between the semiconductor substrate and the second semiconductor layer, and a second cavity is formed between the second semiconductor layer and the fourth semiconductor layer. Forming the cavity,
Forming a first insulating layer in the first cavity, and forming a second insulating layer in the second cavity. A method for manufacturing a semiconductor device, comprising:

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