KR20080045050A - Erasing Circuit in Nonvolatile Semiconductor Memory - Google Patents

Abstract

In the erase processing in units of memory cell blocks, a nonvolatile semiconductor memory device capable of suppressing chip area without complicated control of the erase process and forming a boundary area for electrically insulating each memory cell block is provided. to provide. Memory cells formed by arranging memory cells in a matrix in rows and columns in a second conductivity type well region formed in a first conductivity type semiconductor substrate, and connecting control gates of memory cells in the same row to common word lines, respectively. An array is formed, and a memory cell array is divided into a plurality of memory cell blocks including a plurality of word lines, and a nonvolatile semiconductor memory device performs erase processing in units of memory cell blocks. The erase process is performed by applying the same erase negative voltage to all word lines in the erase target block, and the erase positive voltage to the control gates of all the memory cells included in the memory cell block except the erase target block.

Description

Erasing circuit of nonvolatile semiconductor memory device {ERASING CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a nonvolatile semiconductor memory device which performs erase processing on a memory cell block basis.

Nonvolatile semiconductor memory devices such as Flash EEPROM (Electronically Erasable and Programmable Read Only Memory) are generally of a second conductivity type (e.g. P-type) formed on a semiconductor substrate of the first conductivity type (e.g., N-type). A memory cell array including a plurality of charge storage layers capable of accumulating charge in a well region and a memory cell having an electrically rewriteable MOS transistor structure in which control gates are stacked is formed. In such flash EEPROMs, generally, the erase processing is selectively performed in units of memory cell blocks for the purpose of reducing the area of the memory cell array and improving the speed of the erase processing.

In the erase process of a nonvolatile semiconductor memory device such as a flash EEPROM, a high positive voltage (for example, 8 V) is applied to a well region where a memory cell is formed, and a reference voltage (for example, a ground voltage, 0 V) is applied to a control gate. An erase process for drawing a charge from the floating gate to the well region side by applying a negative voltage lower than the reference voltage (for example, -8 V), or applying a high positive voltage to the source of the memory cell and a reference voltage to the control gate There is an erase process for drawing charge from the floating gate to the source side.

In addition, in the nonvolatile semiconductor memory device which performs an erase process for applying a high electric field between the control gate well region, each memory cell block is interposed between each memory cell block so that the erase process can be selectively performed in units of memory cell blocks. A boundary region for electrically insulating the formed well region is formed.

5 shows a memory cell array configuration of a general NOR flash EEPROM. The memory cell array is divided into two memory cell blocks MB1 and a memory cell block MB2, and a boundary area BO12 is formed between the memory cell block MB1 and the memory cell block MB2. Border area (BO12) memory cell block (MB1) and the memory cell P-type well region (PW ₁₎ which is formed in a block (MB2) by is formed on the P-type well region in (PW ₂₎ is electrically insulated, and The memory cell block MB1 and the memory cell block MB2 can be selectively erased. Specifically, in the erase process, for example, when the memory cell block MB1 is the erase target block and the memory cell block MB2 is the non-erasure target block, the P-type well region of the memory cell block MB1 which is the erase target block is erased. By applying a high positive voltage to PW ₁ and a negative voltage to word lines WL _{11 to} WL _1n included in the memory cell block MB1, data can be erased to the memory cell block MB1. The voltage is not applied to the P-type well region PW _{2 of the} memory cell block MB2 that is the non-erasing block and the word lines WL _{21 to} WL _2n included in the memory cell block MB2. As a result, both the P-type well region PW _{2 of the} memory cell block MB2 and the word lines WL _{21 to} WL _2n included in the memory cell block MB2 have the same voltage (for example, 0 V). The recorded data is protected without being erased.

In such a nonvolatile semiconductor memory device, a memory cell block obtained by dividing a plurality of memory cell arrays is formed in a second conductivity type well region formed on a semiconductor substrate of a first conductivity type, and the memory cell block is a diffusion layer of a first conductivity type. There is a nonvolatile semiconductor memory device which is separated by (wiring) and forms an electrode for setting a well potential for each block in each memory cell block to enable erasure processing for each memory cell block (for example, in Japanese Patent Laid-Open No. See 3-290960).

However, in the nonvolatile semiconductor memory device according to the prior art, the voltage value of the well region in which the memory cell block MB1 is formed and the voltage value of the well region in which the memory cell block MB2 is formed in the erase process. Since the setting of the voltage value of the well region of the block to be erased is different from that of the well region of the block to be erased, the memory cell blocks need to be electrically insulated from other memory cell blocks. In other words, since it is necessary to form a boundary area for electrically insulating each memory cell block between each memory cell block, there is a problem that the chip area is increased due to the formation of the boundary area so that the manufacturing cost is not sufficiently reduced. .

On the other hand, by applying the ground voltage to the control gate of the cell to be erased, the high voltage for erasing to the source, and the high voltage for erasing to the control gate and the source of the memory cells other than the cell to be erased, thereby erasing in units of word lines. There is a nonvolatile semiconductor memory device capable of performing the above operation (see, for example, Japanese Patent Application Laid-open No. Hei 4-355299). In this nonvolatile semiconductor memory device, since a high electric field is applied between the control gate and the source by controlling the voltage applied to the control gate and the source, erase processing in units of word lines is realized. It is not necessary to form a boundary area for electrically insulating each memory cell block in the semiconductor device, thereby increasing the chip area.

However, the nonvolatile semiconductor memory device described in Japanese Patent Laid-Open No. Hei 4-355299 realizes the erase process by controlling the voltage applied to the control gate and the source, and thus the control according to the erase process is complicated. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a boundary area for electrically insulating each memory cell block without complicating the control according to the erase process in the erase process in units of memory cell blocks. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of suppressing chip area.

A nonvolatile semiconductor memory device according to the present invention for achieving the above object is a charge accumulation layer and control capable of accumulating charge in a well region of a second conductivity type different from the first conductivity type formed on a semiconductor substrate of a first conductivity type. A memory cell array including a plurality of gated stacked electrically rewritable MOS transistor structures is formed, and the memory cell arrays array the memory cells in matrix in row and column directions and are in the same row. The control gates of the memory cells are respectively connected to a common word line, the drains of the memory cells in the same column are connected to a common bit line, and at least the source of the memory cells in the same column or the same row is a common ground line. Is divided into a plurality of memory cell blocks formed by connecting to and comprising a plurality of word lines. A positive voltage for erasing is applied to the well region, the same negative voltage is applied to all word lines included in the erase target block for the erase target block among the memory cell blocks, and the erase target block The erase process is performed for each of the memory cell blocks by applying the erase positive voltage to the control gates of all the memory cells included in the memory cell block except for the above.

The nonvolatile semiconductor memory device of the above aspect includes a plurality of memory cell block groups in which a plurality of the memory cell blocks are formed in a common well area, and the well areas of the memory cell block groups are adjacent to each of the memory cell block groups. In the selected memory cell block group which is electrically separated from the well region of the well region, the positive positive voltage for the well region is equal to all word lines included in the erase target block. In the non-selected memory cell block group, the erase positive voltage is applied to all word lines included in the memory cell block except the erase target block, and the erase target voltage is not included. A predetermined reference voltage is applied to an area, and the reference is applied to all word lines included in all the memory cell blocks. That by the pressure applied to the floating state, or performs the erasing process to the erasing target blocks in the selected memory cell block group it is characterized.

The nonvolatile semiconductor memory device according to any one of the above features further comprises a row decoder configured to switch a voltage applied to a word line of the memory cell block in units of the memory cell block in the erase process in each of the memory cell blocks. And to switch and supply the reference voltage or the positive positive voltage in common to the row decoders of one of the memory cell blocks of each of the memory cell block groups, respectively, for each of the memory cell blocks of the memory cell block group. A voltage supply source, and each of the voltage supply sources outputs the reference voltage when the erase target block is included in any one of the memory cell blocks that supply a common voltage among the memory cell block groups, and erases the reference voltage. When the target block is not included, the positive voltage for erasing is output. And that is characterized.

According to the present invention of the above aspect, each memory cell block is formed in the same well region, and in the erase process, an erase positive voltage is applied to the well region, and the same erase sound is applied to all word lines included in the erase target block. The erase process is performed by applying a voltage and applying an erase positive voltage to the control gates of all the memory cells included in the memory cell block (non-erasure target block) except the erase target block, thereby controlling the well region and each memory cell. The erase process can be performed only by the voltage control on the gate (word line). Therefore, according to the present invention, since it is not necessary to form a boundary area for electrically insulating each memory cell block between each memory cell block, the chip area can be reduced. In addition, since an erase positive voltage such as a well region is applied to the word line to the non-erasing block, adverse effects on the data retention characteristic of each memory cell can be suppressed.

For example, when the erase processing is performed in units of word lines, a negative voltage for erasing is applied to a word line connected to an erasing target cell among memory cells, and an amount of erasing amount is applied to a word line connected to an adjacent non-erasing target memory cell. In terms of applying a voltage, the voltage difference between the adjacent word lines becomes very large. However, when the erase process is performed in units of memory cell blocks as in the present invention, no voltage difference occurs between the word lines. In addition, when the erase processing is performed in units of word lines, the row decoder which controls the voltage applied to each word line in the memory cell block needs to be configured so that voltages can be applied separately from each word line. When the erase processing is performed in units of memory cell blocks as in the present invention, since the voltages applied to each word line in the same memory cell block are the same, the row decoder can be simplified.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of the nonvolatile semiconductor memory device (henceforth abbreviated suitably "this invention apparatus") concerning this invention is described based on drawing.

<1st embodiment>

EMBODIMENT OF THE INVENTION The 1st Embodiment of the apparatus of this invention is described based on FIGS. 1 is a schematic block diagram showing an example of a partial configuration according to the erasing process of the apparatus of the present invention, and FIG. 2 is a schematic diagram showing the voltage waveform applied to the well region and each word line in the erasing process of the apparatus of the present invention. It is a waveform diagram. In this embodiment, a case where the memory cell array is divided into two memory cell blocks will be described.

The apparatus of the present invention applies a positive voltage for erasing to a well region, applies the same negative voltage to all word lines included in the erase target block to the erase target block among the memory cell blocks, and removes the memory cell except the erase target block. The erase process is performed for each memory cell block by applying an erase positive voltage to the control gates of all the memory cells included in the block.

In detail, as shown in FIG. 1, the apparatus 1 of the present invention receives an input of a memory cell array 10 divided into two memory cell blocks MB1 and a memory cell block MB2 and an external power supply Vpp. It receives the voltage output from the power supply pad 21 or the charge pump 22 to generate a positive voltage (for example, 8V) for use in the erasing process, and generates a high voltage switch (Sh1, Sh2) and a source well switch. The high voltage control circuit 20 supplied to 50 generates an erasing negative voltage (e.g., -8V) lower than the reference voltage (ground voltage, 0V) used in the erasing process, and generates negative voltage switches Sn1 and Sn2. A row decoder for receiving voltages from the negative voltage control circuit 30, the high voltage switch Sh1, and the negative voltage switch Sn1, and applying a voltage to a word line of the memory cell block MB1 according to a selection state. 4l), the voltage from the high voltage switch (Sh2) and the negative voltage switch (Sn2) La being an output from the memory cell block row decoder (42) for applying a voltage to the word line of (MB2), and a high-voltage control circuit 20, a source strap that is connected to the source of the memory cells (SS ₁ ~SS _x) (Corresponding to a ground line) or a source well switch 50 for applying a voltage to the P-type well region PW. In the present embodiment, the case where the memory cell block MB1 is the erase target block and the memory cell block MB2 is the non-erasure target block holding the write data will be described.

As shown in FIG. 1, the memory cell array 10 includes a well region of a second conductivity type (eg, P type) different from the first conductivity type formed on a semiconductor substrate of the first conductivity type (eg, N type). It is formed in PW. The memory cell array 10 arranges a plurality of memory cells of an electrically rewritable MOS transistor structure in which a charge accumulation layer capable of accumulating charge and a control gate are stacked in a matrix in a row and column direction, and the The control gates of the memory cells are connected to common word lines WL _{11 to} WL _1n and WL _{21 to} WL _2n, respectively, and the drains of the memory cells in the same column are connected to the common bit lines BL _{1 to} BL _Y. At least the source of the memory cells in the same column or the same row is connected to the common source straps SS _{1 to} SS _X (corresponding to the ground line).

3 is a schematic layout diagram showing an example layout of the memory cell array 10. The P-type well region PW is formed in the N-type semiconductor substrate NW, and the memory cell array 10 formed in the same P-type well region PW includes two memory cell blocks MB1 and a memory cell block ( MB2). The memory cell block (MB1) has a word line (WL ₁₁ ~WL _1n) and the N + diffusion region is configured by having a (ND ₁₁ ~ND _1n) and the word line (WL ₁₁ ~WL _1n) and the N + diffusion region (ND ₁₁ ND _1n ) is formed to be orthogonal. Each memory cell of the memory cell block MB1 is formed in an overlapping portion (an oblique line portion in the drawing) of the word lines WL _{11 to} WL _1n and the N + diffusion regions ND _{11 to} ND _1n and has a drain contact. This bit line and the portion without drain contact constitute a source. Similarly, the memory cell block MB2 includes word lines WL _{21 to} WL _2n and N + diffusion regions ND _{21 to} ND _2n , and the word lines WL _{21 to} WL _2n and N + diffusion regions ( ND _{21 to} ND _2n ) are formed to be orthogonal. Each memory cell of the memory cell block MB2 is formed in an overlapping portion (an oblique portion in the drawing) of the word lines WL _{21 to} WL _2n and the N + diffusion regions ND _{21 to} ND _2n , and has a drain contact. This bit line and the portion without drain contact constitute a source.

In FIG. 3, nodes PTAP ₁ and PTAP ₂ that apply voltage to the P well region PW are electrically configured with the same node, and source straps SS _{1 to} SS _x are two memory cell blocks. Shared by As can be seen from the layout diagram shown in Fig. 3, the memory cell array 10 of the apparatus 1 of the present invention does not require the boundary area BO12 shown in Fig. 5, so that the chip area can be reduced. have.

When the erase target block is designated by an external signal and execution of the erase process is instructed, the high voltage control circuit 20 converts the voltage from the charge pump 22 or the power supply pad 21 to erase the positive voltage for the erase process. Is generated and supplied to the high voltage switches Sh1 and Sh2 and the source well switch 50. The high voltage switch Sh1 receives the positive voltage for erasing from the high voltage control circuit 20 during the erasing process, and outputs a reference voltage to the row decoder 4l when the memory cell block MB1 is the block to be erased. When the memory cell block MB1 is the non-erasing target block, the positive voltage for erasing is output. In this embodiment, since the memory cell block MB1 is an erase target block, the high voltage switch Sh1 outputs a reference voltage to the row decoder 4l. Similarly, the high voltage switch Sh2 receives the positive voltage for erasing from the high voltage control circuit 20 during the erasing process, and sets the reference voltage when the memory cell block MB2 is the block to be erased with respect to the row decoder 42. If the memory cell block MB2 is a non-erasing target block, the erase positive voltage is output. In the present embodiment, since the memory cell block MB2 is a non-erasing target block, the high voltage switch Sh2 outputs the positive voltage for erasing to the row decoder 42. During the erase process, the row decoder 42 applies the positive positive voltage supplied from the high voltage switch Sh2 to the word lines WL _{21 to} WL _2n of the memory cell block MB2.

When the erase target block is designated by an external signal and execution of the erase process is instructed, the negative voltage control circuit 30 converts the voltage from the negative voltage charge pump (not shown) to generate an erase negative voltage for the erase process. Then, the negative voltage switch Sn1 and the negative voltage switch Sn2 are supplied. The negative voltage switch Sn1 receives the erasing negative voltage from the negative voltage control circuit 30 during the erasing process, and when the memory cell block MB1 is the erase target block for the row decoder 4l, A voltage is output, and a reference voltage is output when the memory cell block MB1 is a non-erasing target block. In this embodiment, since the memory cell block MB1 is the erase target block, the negative voltage switch Sn1 outputs the erase negative voltage to the row decoder 4l. Similarly, the negative voltage switch Sn2 receives the erase negative voltage from the negative voltage control circuit 30 during the erase process, and erases when the memory cell block MB2 is the erase target block for the row decoder 42. A negative voltage is output, and a reference voltage is output when the memory cell block MB2 is a non-erasing target block. In the present embodiment, since the memory cell block MB2 is a non-erasing target block, the negative voltage switch Sn2 outputs a reference voltage to the row decoder 42.

The row decoder 4l supplies the negative voltage for erasing when the memory cell block MB1 is the erase target block with respect to the word lines WL _{11 to} WL _1n of the memory cell block MB1 during the erase process. When MB1) is the non-erasing block, the positive positive voltage is applied. In the present embodiment, since the memory cell block MB1 is the erase target block, the erase negative voltage supplied from the negative voltage switch Sn1 to the word lines WL _{11 to} WL _1n of the memory cell block MB1. Is authorized.

The row decoder 42 supplies the erase negative voltage to the word lines WL _{21 to} WL _2n of the memory cell block MB2 during the erase process, when the memory cell block MB2 is the erase target block. When MB2 is the non-erasing block, the positive positive voltage is applied. In this embodiment, since the memory cell block MB2 is a non-erasing target block, the positive positive voltage supplied from the high voltage switch Sh2 is applied to the word lines WL _{21 to} WL _2n of the memory cell block MB2. do.

The source well switch 50 receives the positive positive voltage from the high voltage control circuit 20 during the erase process, and applies the supplied positive positive voltage to the P-type well region PW. As a result, both the word lines WL _{21 to} WL _2n of the memory cell block MB2 and the applied voltages of the P-type well region become the positive voltages for erasing, so that no voltage difference occurs. The write data of each memory cell constituting (MB2) is not erased. Similarly, the voltage applied to the word lines WL _{11 to} WL _1n of each memory cell of the memory cell block MB1 serving as the erase target block becomes a negative voltage for erasing, and the voltage applied to the P-type well region PW is erased. Since the voltage becomes a positive voltage, each memory cell constituting the memory cell block MB1 is subjected to a voltage based on a voltage difference between the positive voltage for erasing and the negative voltage for erasing, thereby performing data erasing. In the present embodiment, as shown in Fig. 2, when the positive voltage for erasing is set to 8 V and the negative voltage for erasing is set to -8 V, a voltage of 16 V is applied to each memory cell constituting the memory cell block MB1 to erase data. Is executed.

In addition, the apparatus 1 of the present invention applies a high voltage to the P-type well region PW to the semiconductor substrate NW during an erase process, and simultaneously applies a positive voltage for erasing. This insulates the semiconductor substrate NW from the P-type well region PW.

<2nd embodiment>

A second embodiment of the apparatus of the present invention will be described based on FIG. 6. In this embodiment, a case where the configuration of the memory cell block is different from that in the first embodiment will be described.

First, the structure of the apparatus of this invention is demonstrated based on FIG. 6 is a schematic block diagram showing an example of a partial configuration according to the erasing process of the apparatus of the present invention. 6 shows a case where two memory cell block groups including two memory cell blocks are formed for simplicity.

In the apparatus according to the erase process, a memory cell array (memory cell block group) {1h (h = 0, 1)} in which memory cell blocks are formed in a common well area, and a memory cell block {MBi ( i = 1 to 4)} to the row decoder 4i and the row decoder 4i configured to be capable of switching the voltage applied to the word lines WLi1 to WLin in units of memory cell blocks. Negative voltage switch (Sni) for supplying the negative voltage for erasing based on the &lt; RTI ID = 0.0 &gt;), and source / well switch for selectively applying a positive positive voltage or reference voltage for each well region (PWh) based on the well control signal (SWh) It is comprised by 5h. The well region PW1 of the memory cell array 10 is electrically separated from the well region PW2 of the memory cell array 11. In the memory cell block MBi, drains of memory cells arranged in corresponding columns are connected to common bit lines BL _{1 to} BL _Y between the memory cell blocks. In the present embodiment, since the number of memory cell blocks included in each of the memory cell array 10 and the memory cell array 11 is two, it is commonly used between the memory cell array 10 and the memory cell array 11. Two voltage sources, i.e., decoder power supply Vd1 and decoder power supply Vd2. The number of voltage supply sources is the number of memory cell blocks included in each memory cell block group.

As shown in FIG. 6, the memory cell array 10 includes a memory cell block MB1 and a memory cell block MB2 in a common well region PW1. The row decoder 4l is connected to the memory cell block MB1 of the memory cell array 10, and the row decoder 42 is connected to the memory cell block MB2. Similarly, as shown in FIG. 6, the memory cell array 11 includes a memory cell block MB3 and a memory cell block MB4 in a common well region PW2 and includes a memory of the memory cell array 11. The row decoder 43 is connected to the cell block MB3, and the row decoder 44 is connected to the memory cell block MB4. The internal structure of the memory cell blocks MB1 to MB4 is the same as that of the first embodiment.

The row decoders 4i (i = 1 to 4) are connected to either one of the decoder power supply Vd1 and the decoder power supply Vd2 which respectively supply a reference voltage or a positive voltage for erasing. Specifically, in the present embodiment, the row decoder 4l of the memory cell array 10 and the row decoder 43 of the corresponding memory cell array 11 are connected to the decoder power supply Vd1. Similarly, the row decoder 42 of the memory cell array 10 and the row decoder 44 of the corresponding memory cell array 11 are connected to the decoder power supply Vd2.

As shown in Fig. 6, the row decoders 4i (i = 1 to 4) of the present embodiment have a word line based on the decoder power supply Vdmi, the decode signals Sdi1 to Sdin, and the negative voltage control signal Sci. A voltage switching circuit for switching the voltages applied to the WLi1 to WLin is provided separately for each of the word lines WLi1 to WLin of the memory cell block MBi. More specifically, the voltage switching circuit connected to the word lines WLij (j = 1 to n) includes two stages of inverter circuits formed by connecting drain terminals of the PMOS transistor and the NMOS transistor, The output of the inverter circuit is connected to the word line WLij. The decoder power supply Vdmi is connected to the gate terminal of the PMOS transistor of the inverter circuit of the previous stage, and the decode signal Sdij is connected to the gate terminal of the NMOS transistor. The connection point (output) of the PMOS transistor and the NMOS transistor of the inverter circuit of the preceding stage is connected to the gate terminals of the PMOS transistor and the NMOS transistor of the inverter circuit of the subsequent stage. The source terminal and the back gate terminal of the PMOS transistor of each inverter circuit are connected to the decoder power supply (Vdk (k = 1 when i is odd, k = 2 when i is even)). The source terminal of the NMOS transistor of the inverter circuit of the preceding stage is grounded, and the source terminal and the back gate terminal of the NMOS transistor of the inverter circuit of the rear stage are connected to the negative voltage switch (Sni).

In the present embodiment, the negative voltage switches {Sni (i = 1 to 4)} remove the negative voltage for erasing from the negative power supply Vn when the negative voltage control signal Sci is set to the '0' level. Output for 4i).

The source well switch {5h (h = 0, 1)} is connected to the well region {PWm (m = 1, 2)} from the well power source Vw when the well control signal SWh is set at the '1' level. A positive voltage for erasing is applied. The source well switch 5h includes a source switch connected to the ground lines S1 and S2, respectively, and a source switch control signal ScO is commonly connected to the gate thereof.

Next, an erase process of the apparatus of the present invention in the present embodiment will be described based on FIG. In this case, it is assumed that the memory cell block MB1 is the erase target block and the memory cell block group 10 is the selected memory cell block group.

In the apparatus according to the present embodiment, the reference voltage is applied to the decoder power supply Vd1 and the positive voltage for erasing is supplied to the decoder power supply Vd2 during the erasing process for the memory cell block MB1 that is the erase target block. The erasing positive voltage is applied to the power supply Vw, and the erasing negative voltage is applied to the negative power supply Vn. A positive voltage for erasing is applied to the decoder power supplies Vdm1 and Vdm2, and a reference voltage is applied to the decoder power supply Vdm4.

In the present embodiment, the apparatus of the present invention applies the positive voltage for erasing to the well region PW1 in the memory cell array 10 (selected memory cell block group) including the memory cell block MB1 (the erase target block). All word lines included in the memory cell block MB2 (memory cell block except memory cell block MB1) have the same erase negative voltage in all word lines WL11 to WL1n included in the memory cell block MB1. The erase positive voltage is applied to the WL21 to WL2n, and the erase process is performed for the memory cell block MB1. Further, in the memory cell block group 11 (unselected memory cell block group) that does not include the memory cell block MB1 which is the erase target block, all the words included in the well region PW2 and the memory cell block MB4. A predetermined reference voltage is applied to the lines WL41 to WL4n to bring the word lines WL31 to WL3n of the memory cell block MB3 into a floating state.

More specifically, in the memory cell array 10 which is the selected memory cell block group, the well control signal Sw1 for controlling the source well switch 50 is set at the '1' level, and the well power source is supplied to the well region PW1. A positive positive voltage from (Vw) is applied. In the memory cell block MB1, which is the erase target block, when the negative voltage control signal Sc1 is set to the '0' level, the negative voltage switch Sn1 causes the low decoder 4l to erase the negative sound from the negative power supply Vn. Supply the voltage. When the decode signals Sd11 to Sd1n are set to the '1' level, since the positive voltage for erasing is applied to the decoder power supply Vdm1, the row decoder 4l switches the voltage connected to the word lines WL11 to WL1n. The output of the circuit is switched to the negative voltage for erasing from the negative voltage switch Sn1. As a result, the row decoder 4l applies an erase negative voltage to the word lines WL11 to WL1n to perform the erase process for the memory cell block MB1.

Also, in the memory cell block MB2 formed in the well region PW1 common to the memory cell block MB1, when the negative voltage control signal Sc2 is set at the '1' level, the negative voltage switch Sn2 is a low decoder ( A reference voltage (ground voltage) is outputted to 42). When the decode signals Sd21 to Sd2n are set at the '1' level, since the erase positive voltage is applied to the decoder power supply Vdm2, the row decoder 42 switches the voltage connected to the word lines WL21 to WL2n. The output of the circuit is switched to the positive voltage for erasing from the decoder power supply Vd2. As a result, the row decoder 42 applies the erasing positive voltage to the word lines WL21 to WL2n so that the erasing process is not performed on the memory cell block MB2.

In the memory cell array 11 which is a non-selected memory cell block group, the well control signal SW2 for controlling the source-well switch 51 is set at the '0' level, and a reference voltage is applied to the well region PW2. In the memory cell block MB3, when the negative voltage control signal Sc3 is set at a '1' level, the negative voltage switch Sn3 outputs a reference voltage (ground voltage) to the row decoder 43. When the decode signals Sd31 to Sd3n are set to the '0' level, the row decoder 43 is supplied with the reference voltage from the decoder power supply Vd1 regardless of the voltage applied to the decoder power supply Vdm3. The word lines WL31 to WL3n connected to 43 are in a floating state. In this case, the voltage difference generated between the gate terminals (word lines WL31 to 3n) and the well region PW2 of each memory cell included in the memory cell block MB3 is such that the word line voltage in the floating state is changed from the reference voltage to the PMOS transistor. And does not vary above the threshold voltage of the NMOS transistor, so that it is suppressed to be sufficiently smaller than the voltage difference (the difference between the positive and negative voltages for erasing) necessary for the erase process, and erases the memory cell block MB3. The process is not executed.

Similarly with respect to the memory cell block MB4 formed in the well region PW2 common to the memory cell block MB3, when the negative voltage control signal Sc4 is set at the '1' level, the negative voltage switch Sn4 is set low. The reference voltage (ground voltage) is output to the decoder 44. When the decode signals Sd41 to Sd4n are set to the '0' level, the reference voltage is applied to the decoder power supply Vdm4, so that the row decoder 44 is connected to the word lines WL41 to WL4n. The output is switched to the reference voltage from the negative voltage switch Sn4. The row decoder 44 is also supplied with a positive voltage for erasing from the decoder power supply Vd2. As a result, the row decoder 44 applies a reference voltage to the word lines WL41 to WL4n to prevent the erase process from being performed on the memory cell block MB4.

In this manner, in the memory cell array 10, an erasing process is performed on the memory cell block MB1 by applying an erasing positive voltage to the well region PW1 and an erasing negative voltage to the word lines WL11 to WL1n. The erase process is not performed for the memory cell block MB2 by applying the erase negative voltage to the word lines WL21 to WL2n. In the memory cell array 11, the word lines WL31 to WL3n included in the memory cell block MB3 are in a floating state, and the word lines WL41 to included in the well region PW2 and the memory cell block MB4. The erase process is not performed for the memory cell block MB3 and the memory cell block MB4 by applying a reference voltage to WL4n. That is, the erase process is performed only for the memory cell block MB1 which is the erase target block.

In the present embodiment, a case has been described in which two memory cell block groups (memory cell array 1h (h = 0, 1)) having two memory cell blocks are formed in the apparatus of the present invention. It is not limited to. Each memory cell block group may have two or more memory cell blocks, and the number of memory cell blocks included in each memory cell block group may be different. In addition, in the case where a plurality of memory cell blocks are formed in a common well region as in the present embodiment, as the number of memory cells formed in the common well region increases, the positive voltage for erasing or the like is erased in the well region in the erase process. In order to apply the reference voltage, a power source with high driving capability is required. The number of memory cell block groups and the number of memory cell blocks included in each memory cell block group are determined in consideration of the breakdown voltage and function of the apparatus of the present invention, the driving capability of each power supply, and the like.

In the present invention, since the common decoder power supplies Vd1 and Vd2 are used between the memory cell block groups, the decoder power sources Vd1 and Vd2 are formed corresponding to each of the memory cell block groups. The chip area of the invention device can be suppressed.

<Other embodiment>

(1) In the first embodiment, the case where the memory cell array is divided into two memory cell blocks MB1 and memory cell blocks MB2 has been described. However, the memory cell array includes three or more memory cell blocks, for example. For example, as shown in FIG. 4, the structure may be divided into four memory cell blocks MB1-MB4. Also in this case, as in the first embodiment, the memory cell is applied by applying the positive voltage for erasing to the well region, the negative voltage for erasing to the word line of the block to be erased, and the positive voltage for erasing to the word line of the non-erasing block. Erasing processing in block units can be realized.

(2) Although the case where the semiconductor substrate is N type and the well region is P type has been described in the first and second embodiments, the present invention is not limited thereto, but the semiconductor substrate is P type and the well region is N type. It may be.

(3) In the second embodiment, for the sake of simplicity, a description will be given of a case in which two decoder power supplies Vd1 and decoder power supplies Vd2 are commonly used for all the row decoders 41 to 44 in an erase processing process. However, it is not limited to this.

For example, in the case where it is desired to avoid the word lines of the non-selected memory cell block group from being in a floating state, the apparatus of the present invention forms four decoder power supplies Vd1 to Vd4, as shown in FIG. 4l (l = 1, 3)} is connected to decoder power supplies Vd1 and Vd2, and row decoders 4m (m = 2, 4) are connected to decoder power supplies Vd3 and Vd4. In this case, the row decoder 4l connects the voltage switching circuit, the source terminal of the PMOS transistor constituting the rear inverter circuit, to the decoder power supply Vd1, and the source terminal and back of the PMOS transistor constituting the inverter circuit of the previous stage. The back gate terminal of the PMOS transistor constituting the gate terminal and the inverter circuit of the rear stage is connected to the decoder power supply Vd2. The row decoder 4m connects the voltage switching circuit with the source terminal of the PMOS transistor constituting the rear inverter circuit to the decoder power supply Vd3, and the source terminal and the backgate terminal of the PMOS transistor constituting the inverter circuit of the previous stage, The back gate terminal of the PMOS transistor constituting the later inverter circuit is connected to the decoder power supply Vd4.

1 is a schematic block diagram showing an example of a partial configuration according to an erase process in the first embodiment of a nonvolatile semiconductor memory device according to the present invention.

Fig. 2 is a schematic waveform diagram showing voltage waveforms applied to the well region and each word line in the erase process of the apparatus of the present invention.

3 is a schematic layout diagram showing an example of the layout of a memory cell array mounted in a nonvolatile semiconductor memory device according to the present invention.

4 is a schematic layout diagram showing an example layout of a memory cell array in another embodiment of the nonvolatile semiconductor memory device according to the present invention.

Fig. 5 is a schematic layout diagram showing an example layout of a memory cell array mounted in a nonvolatile semiconductor memory device according to the prior art.

6 is a schematic block diagram showing an example of a partial configuration according to an erase process in the second embodiment of the nonvolatile semiconductor memory device according to the present invention.

7 is a schematic block diagram showing an example of a partial configuration according to an erase process in another embodiment of the nonvolatile semiconductor memory device according to the present invention.

Claims (3)

A memory cell array including a plurality of electrically rewritable MOS transistor structures having a charge accumulation layer capable of accumulating charge and a control gate stacked thereon is a second cell different from the first conductivity type formed on a first conductivity type semiconductor substrate. Is formed in the conductive well region; The memory cell array arranges the memory cells in a matrix in rows and columns, connects the control gates of the memory cells in the same row to common word lines, and shares the drains of the memory cells in the same column in common. A plurality of memory cell blocks, each of which is connected to a bit line of at least one of the plurality of memory lines and is connected to a common ground line. ; Applying a positive positive voltage to the well region; The same erase negative voltage is applied to all word lines included in the erase target block with respect to the erase target block among the plurality of memory cell blocks; A nonvolatile semiconductor memory device characterized in that the erase process is performed for each of the memory cell blocks by applying the erase positive voltage to the control gates of all the memory cells included in the memory cell block except for the erase target block. 2. The memory cell of claim 1, wherein a plurality of the memory cell blocks includes a plurality of memory cell block groups formed in a common well region, and the well regions of the memory cell block groups are adjacent to each of the wells of the adjacent memory cell block groups. Is electrically isolated from the region; In the selected memory cell block group including the erase target block, the erase positive voltage for the well region, the same negative voltage for all word lines included in the erase target block, and the erase target block. Applying the erasing positive voltage to all word lines included in the memory cell block except for; In a non-selected memory cell block group not including the erase target block, a predetermined reference voltage is applied to the well region, and the reference voltage is applied or floated to all word lines included in all the memory cell blocks. ; And the erasing process is performed for the erase target block in the selected memory cell block group. 3. The row decoder of claim 2, further comprising: a row decoder configured to switch voltages applied to word lines of the memory cell blocks in units of the memory cell blocks in the erase process for each of the memory cell blocks; A voltage supply source provided for each of the memory cell blocks of the memory cell block group and switching and supplying the reference voltage or the positive positive voltage for common to the row decoders of one of the memory cell blocks of each memory cell block group; Having; Each of the voltage supply sources outputs the reference voltage when the erase target block is included in any one of the memory cell blocks that commonly supply voltages among the memory cell block groups, and the erase target block is not included. And outputting said positive voltage for erasing.

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