KR100254565B1 - Row decoder circuit of flash memory device having divided word line structure - Google Patents

Abstract

A flash memory device of the present invention comprises: a memory cell array divided into a plurality of sectors; Word lines provided to the respective sectors; A row global decoder provided to the respective groups for selecting word lines of one of the sectors; Each of the sectors comprises: a row partial decoder for supplying a selection voltage to a selected one of the word lines in a write and read mode of operation and for supplying a non-selected voltage to unselected ones; A row block decoder for simultaneously supplying an erase voltage to word lines provided to the sector in an erase operation mode; A row local decoder of switches for connecting one of said row partial decoder and said row block decoder with corresponding word lines, respectively, in response to first and second global word line signals from said row global decoder; and; Each of the switches comprises: a first transistor having a channel formed between a word line corresponding to each of the switches and the row partial decoder and controlled to the first global word line signal; A second transistor formed between a word line corresponding to each of the switches and the row partial decoder and controlled to the second global word line signal; A channel is formed between a word line corresponding to each of the switches and the row block decoder, and includes a third transistor controlled to the first global word line signal.

Description

ROW DECODER CIRCUIT OF A FLASH MEMORY DEVICE WHICH HAS A DIVIDED WORDLINE ARCHITECTURE

The present invention relates to a flash memory device, and more particularly, to a row decoder circuit of a flash memory device having a divided word line architecture.

Flash memory devices have a large number of users who require fast processing speeds because the operating speed is significantly higher in program and read operations compared to nonvolatile semiconductor memory devices capable of electrically erasing and programming operations. It is received. Flash memory devices may be classified into NAND type and NOR type flash memory devices. As is well known to those skilled in the art, the cell array of the NOR flash memory device has a structure in which a plurality of memory cells are arranged in parallel on one bit line, whereas the NAND flash memory device has a structure. The cell array has a structure in which a plurality of memory cells are arranged in series on one bit line.

1, there is shown a cross-sectional view showing the structure of a typical flash memory cell.

As shown in Fig. 1, a flash memory cell has a source 3 and a drain 4 formed of N + impurities with a channel region interposed therebetween on a surface of a P-type semiconductor substrate 2, and 100 kHz on the channel region. A floating gate 6 formed with the following thin insulating film 7 interposed therebetween, and an insulating film (for example, an ONO film) 9 on the floating gate 6. In addition, a control gate 8 is formed. And terminals (Vs), (Vd), (Vg), and (Vb) for applying the voltages required for the program, erase, and read operation models are the source (3), the drain (4), and the control. It is connected to the gate 8 and the said semiconductor substrate 2, respectively.

According to a conventional NOR-type flash memory program operation, the memory cell is programmed by causing hot electron injection to the floating gate 8 in the channel region adjacent to the drain region 4. The electron injection grounds the source region 3 and the P-type semiconductor substrate 2, applies a high voltage (eg, + 10V) to the control gate electrode Vg, and applies the drain region ( This is achieved by applying an appropriate amount of voltage (eg 5V to 6V) to generate hot electrons in 4). When the memory cell is programmed according to this voltage application condition, that is, when negative charge is sufficiently accumulated in the floating gate 6, the accumulated (or trapped) negative charge in the floating gate 6 During a series of read operations, the threshold voltage of the programmed flash memory cell is increased.

Typically, the voltage application condition of the read operation applies a positive voltage (e.g., 1V) to the drain region 4 of the flash memory cell, and applies a predetermined voltage (e.g., to its control gate 8) Power supply voltage, or about 5V), and 0V to its source region 3. When a read operation is performed in accordance with the above conditions, its threshold voltage is increased by the hot electron injection method described above, that is, the programmed flash memory cell is moved from its drain region 4 to its source region 3. Injection of current is prevented. At this time, the programmed flash memory cell is said to be “off”.

Subsequently, according to the erase operation of the flash memory cell, the memory cell is erased by generating F-N tunneling (Fowler-Nordheim tunneling) to the control gate 8 in the semiconductor substrate 2, that is, the bulk region. In general, the FN tunneling applies a negative high voltage (e.g., -10V) to the control gate 8 and generates FN tunneling between the bulk region 2 and the control gate 8. By applying an appropriate amount of voltage (eg 5V). At this time, its drain region 4 is maintained in a high impedance state (e.g., a floating state) in order to maximize the effect of the erase. When voltages corresponding to such an erasing condition are applied to corresponding power terminals Vg, Vd, Vs, and Vb, a strong electric field is formed between the control gate 8 and the bulk region 2. do. This results in the F-N tunneling described above, as a result of which negative charge in the floating gate 6 of the programmed cell is released into its source region 3.

Typically, the F-N tunneling occurs when an electric field of 6-7 MV / cm is formed between the insulating film 7. This is possible because the thin insulating film 7 of 100 kPa or less is formed between the floating gate 6 and the bulk region 2. The discharge (or discharge) of the negative charge from the floating gate 6 to the bulk region 2 by the erase method according to the FN tunneling means that the erase of the erased flash memory cell is performed during a series of read operations. It serves to lower the solder voltage.

In a general flash memory cell array configuration, each bulk area is connected to a plurality of cells together for high integration of the memory device, so that when the erase operation is performed according to the above-described erase method, the plurality of memory cells are simultaneously erased. . The erasing unit is determined according to the area in which each bulk area 2 is separated. {For example, 64K byte: hereinafter referred to as a sector.} During a series of read operations, a flash memory cell whose threshold voltage is lowered by the erase operation is applied with a constant voltage to the control gate 8. In this case, a current path is formed from the drain region 4 to the source region 3. Such flash memory cells are said to be "on." Table 1 shows the voltage levels applied to the respective power supply terminals Vg, Vd, Vs, and Vb during the program, erase, and read operations of the flash memory cell.

TABLE 1

Operation mode Vg Vd Vs Vb program + 10V + 5V to + 6V 0 V 0 V Cattle -10V Floating Floating + 5V Reading + 4.5V + 1V 0 V 0 V

As such, the control gate voltage (i.e., word line voltage) in the NOR flash memory is different for each operation mode, and the importance of the row decoder circuit for adjusting the word line voltage, which is the control gate voltage, is very important. As mentioned above, a row decoder scheme for controlling the word line voltage of a memory cell is entitled "A 3.3V-only 16Mb Flash Memory with Row-Decoding Scheme" at the IEEE International Solid-State Circuits Conference in 1996. Was released. The figures published in the paper are shown in FIGS. 2 and 3, respectively.

Referring to FIG. 2, a memory cell array is comprised of four groups, for example divided into eight sectors, each of which is not shown in the figure. It has 512 rows and 1024 columns. In other words, the storage capability of one sector is 64 kB. Therefore, the storage capacity of the cell array shown in FIG. 2 is 16Mb. Each of the sectors is a basic unit in an erase operation as described above, and its word lines and bit lines are selected independently of other sectors of the same group. A row global decoder for independently selecting word lines of the sectors of the respective groups is provided to the groups, respectively. In addition, each of the sectors has a row local decoder arranged on both sides thereof, and a row partial decoder and a row block decoder arranged thereon. At the bottom is a column selector (Y-selector). The circuit for the row local decoder is shown in FIG. The row local decoders are arranged at both sides of the corresponding sectors in order to secure the pitch of the word lines, and are a result of the high density trend of the semiconductor memory device.

Referring to FIG. 3, a row decoder circuit provided to each sector is composed of a row global decoder 10, a row partial decoder 20, a row local decoder 30, and a row block decoder 40. Among the decoders, the row global decoder 10, the row partial decoder 20, and the row block decoder 40 are composed of a circuit for coding an external address and a level shifter for switching high and low voltages. . And, the row local decoder 30 consists of switches coded by the decoders 10, 20 and 40, one switch comprising two PMOS transistors and two NMOS transistors. It is composed. Accordingly, the word lines of the sectors are connected to the output of the row partial decoder 20 in the read and write operation mode by the output signal of the row global decoder 10, that is, the global word line signal. In the erase operation mode, all word lines of one sector block are connected to the output of the row block decoder 40 by the global word line signal. However, since one switch of the row local decoder as described above is composed of four transistors, it is the biggest burden when laying out, and when pumping a word line, it acts as a load (ie, capacitance).

It is therefore an object of the present invention to provide a row decoder circuit of a highly integrated flash memory device.

It is another object of the present invention to provide a row decoder circuit that can reduce the load capacitance of a word line.

1 is a cross-sectional view showing the structure of a typical flash memory cell;

2 shows a 16 Mb cell array configuration of a flash memory device having a divided word line structure;

3 is a circuit diagram showing a configuration of a row decoder circuit according to the prior art;

4 is a circuit diagram showing a configuration of a row decoder circuit according to an embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

10, 110: row global decoder 20, 120: row partial decoder

30, 130: row local decoder 40, 140: row block decoder

According to one aspect of the present invention for achieving the above object, a memory cell array divided into groups of a plurality of sectors; Word lines provided to the respective sectors; A row global decoder provided to the respective groups for selecting word lines of one of the sectors; Each of the sectors comprises: a row partial decoder for supplying a selection voltage to a selected one of the word lines in a write and read mode of operation and for supplying a non-selected voltage to unselected ones; A row block decoder for simultaneously supplying an erase voltage to word lines provided to the sector in an erase operation mode; A row local decoder of switches for connecting one of said row partial decoder and said row block decoder with corresponding word lines, respectively, in response to first and second global word line signals from said row global decoder; and; Each of the switches comprises: a first transistor having a channel formed between a word line corresponding to each of the switches and the row partial decoder and controlled to the first global word line signal; A second transistor formed between a word line corresponding to each of the switches and the row partial decoder and controlled to the second global word line signal; A channel is formed between a word line corresponding to each of the switches and the row block decoder, and includes a third transistor controlled to the first global word line signal.

In this embodiment, the first transistor is composed of a P-channel MOS transistor.

In this embodiment, the second and third transistors are composed of N-channel MOS transistors.

By such a circuit, the number of switch transistors for connecting word lines to a corresponding decoder according to an operation mode can be reduced.

Hereinafter, reference will be made in detail with reference to FIG. 4 according to an embodiment of the present invention.

4, the novel row decoder circuit of the present invention provides a row local decoder 130. As shown in FIG. The row local decoder 130 may include one PMOS transistor MP1n and two NMOS transistors MN1n to connect corresponding word lines to one of the row partial decoder 120 and the row block decoder 140. Have switches SWn composed of MN2n). Therefore, the burden of layout and capacitance of word lines can be reduced by the row local decoder 130 according to the present invention.

Referring back to FIG. 4, the row decoder circuit according to the present invention includes a row global decoder 110, a row partial decoder 120, a row local decoder 130, and a row block decoder 140. Here, the row global decoder 110, the row partial decoder 120 and the row block decoder 140 are the same as those of the above-described paper, and thus detailed description thereof is omitted here. Here, the ratio of the row global decoder 110 to the word line is 1: n. That is, one row global decoder 110 selects n word lines. Therefore, when 8 × n word lines are provided in one sector, the row global decoder 110 and the corresponding row local decoder 130 may be configured in eight pieces. Self-evident to those who have learned

The row local decoder 130 is selected by the row global decoder 110, as described above, and replaces one of the row partial decoder 120 and the row block decoder 140 with the row local decoder ( Switches SWn (where n is an integer) for connecting with word lines WLn associated with 130. Each of the switches SWn includes one PMOS transistor MP1 and two NMOS transistors MN1 and MN2.

The gate of the PMOS transistor MP1 is connected to a first global word line GWL1 of the row global decoder 110, and its channel is a word line WLn corresponding to the row partial decoder 120. It is formed between. The gate of the NMOS transistor MN1 is connected to a second global word line GWL2 of the row global decoder 110, and its channel is connected to the row partial decoder 120 and the corresponding word line WLn. Formed between). The gate of the NMOS transistor MN2 is connected to the first global word line GWL1, and a channel thereof is formed between the corresponding word line WLn and the row block decoder 140. . Here, the switches SWn are commonly connected to the row block decoder 140 in an erase operation mode, and a selection signal and non-selection from the row partial decoder 120 in a write and read operation mode. Independently transfers non-selection signals to the corresponding word lines (WLn).

The operation of the row decoder circuit according to the present invention is described below. First, during the read and write mode of operation, if the row global decoder 110 is addressed by an external address, the level on the first global word line GWL1 of the decoder 110 becomes a low level. The level on the second global word line GWL2 is at a high level. Thus, the PMOS transistors MP1n and the NMOS transistors MN1n of the switches SWn of the row local decoder 130 are turned on, and the NMOS transistors MN2n are turned off. Thus, the word lines WLn associated with the row local decoder 130 are supplied with select and non-select signals from the row partial decoder 120. That is, the voltage Vwl is applied to the word line selected by the row partial decoder 120, and the voltage of the unselected word lines becomes the ground potential GND.

Next, during the erase operation mode, sectors in one group are addressed by an external address. At this time, the level of the first global word line GWL1 is a high level, and the level of the second global word line GWL2 is a low level. Thus, the PMOS transistors MP1n and the NMOS transistors MN1n of the row local decoders present in the sector are turned off, and the NMOS transistors MN2n are turned on. As a result, the level of all word lines WLn of the addressed sectors becomes the voltage VL.

The values of the voltages Vwl, VH, and VL according to the respective operation modes are shown in Table 2.

TABLE 2

Operation mode READ PROGRAM ERASE Vwl 5 V 10 V 5C VH 5 V 10 V 0 V VL 0 V 0 V -10V

As such, by reducing the number of transistors MP1n, MN1n, and MN2n constituting the switches SWn of the row local decoder 130 than the conventional one, the row local decoder 130 Layout size and load (i.e. capacitance) can be reduced when pumping word lines.

As described above, the size of the layout and the load of word lines can be reduced by reducing the transistors of the row local decoder.

Claims (3)

A memory cell array divided into groups of a plurality of sectors; Word lines provided to the respective sectors; A row global decoder provided to the respective groups for selecting word lines of one of the sectors; The respective sectors, A row partial decoder for supplying a selection voltage to selected ones of the word lines in a write and read mode of operation, and supplying a non-selected voltage to unselected ones; A row block decoder for simultaneously supplying an erase voltage to word lines provided to the sector in an erase operation mode; A row local decoder of switches for connecting one of said row partial decoder and said row block decoder with corresponding word lines, respectively, in response to first and second global word line signals from said row global decoder; and; Each of the switches, A first transistor having a channel formed between a word line corresponding to each of the switches and the row partial decoder, the first transistor being controlled to the first global word line signal; A second transistor formed between a word line corresponding to each of the switches and the row partial decoder and controlled to the second global word line signal; And a third transistor formed between a word line corresponding to each of the switches and the row block decoder, the third transistor being controlled to the first global word line signal. The method of claim 1, And the first transistor is a P-channel MOS transistor. The method of claim 1, And the second and third transistors are composed of N-channel MOS transistors.

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