KR20080024338A - Thin film transistor substrate, manufacturing method thereof and display device having same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate, a method for manufacturing the same, and a display device having the same, wherein the extending direction of the active layer provided in the display area is parallel to the extending direction of the crystallization protrusion provided in the active layer, and the channel of the active layer provided in the peripheral circuit area. A thin film transistor substrate capable of preventing crystallization spots from occurring in the display area by improving the moving direction of the carrier using the inside and the extending direction of the crystallization protrusion provided in the active layer, and improving the performance of the thin film transistor in the peripheral circuit area. And a method of manufacturing the same and a display device having the same.

Description

A thin film transistor substrate, a method of manufacturing the same, and a display device having the same {THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE HAVING THE SAME}

1 is a schematic plan view of a display panel according to an exemplary embodiment of the present invention.

2 is a schematic plan view of a unit pixel in a display area of a display panel according to an exemplary embodiment;

3 is a plan conceptual view of a unit thin film transistor in a peripheral circuit region.

4 to 7 are views for explaining the manufacturing method of the thin film transistor substrate of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: thin film transistor substrate 110, 210: active layer

120: sustain electrode pattern 130: gate line

131 and 231: gate electrode 151 and 251: source electrode

153 and 253 drain electrodes 160 and 260 thin film transistors

180 pixel electrode

The present invention relates to a thin film transistor substrate, a method for manufacturing the same, and a display device having the same. A thin film transistor substrate and a method for manufacturing the same may be prevented by changing the layout of the active layer formed in the display area and the peripheral circuit area. And a display device having the same.

Conventionally, crystallization is performed through a low temperature poly-silicon thin film (LTPS) manufacturing process to fabricate a thin film transistor having high mobility characteristics on a transparent insulating substrate.

In order to manufacture such a low-temperature polycrystalline silicon thin film, polycrystalline or single crystal particles are formed on the substrate by using sequential lateral solidification (SLS) crystallization technology to form large silicon grains. In the case of the low temperature polycrystalline silicon thin film manufactured by the SLS crystallization technology, the crystallization direction of the thin film may be induced in a constant direction.

Therefore, when the low temperature polycrystalline silicon thin film is used as an active layer (channel) of the thin film transistor, the carrier movement direction and the crystallization direction in the active layer are prepared in parallel. This improved the performance (high mobility) of thin film transistors. However, in the case of the silicon thin film crystallized through the SLS crystallization technology, a plurality of crystallization protrusions are formed in a direction substantially perpendicular to the crystallization direction. As mentioned above, since the active layer of the thin film transistor extends in parallel with the crystallization direction, a plurality of crystallization protrusions are disposed in the active layer. At this time, crystallization spots are caused by crystallization protrusions arranged at regular intervals and in number in the plurality of active layers formed on the substrate. In particular, the plurality of active layers provided in the display area of the substrate has a problem that the crystallization spots caused by the crystallization projections are recognized.

Accordingly, the present invention was derived to solve the above problems, and the crystallization unevenness of the display area is visualized by changing the carrier moving direction in the active layer of the thin film transistor of the thin film transistor of the display area and the carrier moving direction in the active layer of the thin film transistor of the peripheral circuit area. It is an object of the present invention to provide a thin film transistor substrate, a method of manufacturing the same, and a display device having the same, which can be prevented, and can improve the driving ratio of the thin film transistor in the peripheral circuit region.

A substrate defined by a display area and a peripheral area according to the present invention, a gate line and a first thin film transistor provided in the display area, and a second thin film transistor provided in the peripheral area, the first gate of the first thin film transistor An electrode extends in one direction, and a second gate electrode of the second thin film transistor provides a thin film transistor substrate extending in a direction crossing the one direction.

Here, each of the first and second thin film transistors includes first and second active layers provided under the gate electrode and having crystallization protrusions extending in the same direction, and an extension direction of the crystallization protrusion is the one direction. It is preferable that it is a direction crossing with. At this time, it is effective that the first and second active layers are low-temperature polycrystalline silicon films crystallized by a sequential lateral solidification (SLS) method.

Of course, it is preferable that the extending direction of the gate line is parallel to the extending direction of the second gate electrode.

Here, it is preferable that a pixel electrode connected to the drain electrode of the first thin film transistor in the display region, and a sustain line overlapping a part of the drain electrode of the first thin film transistor are provided.

In addition, a first thin film transistor including a first active layer and a first gate electrode is formed in a display area of a substrate according to the present invention, and a second thin film transistor including a second active layer and a second gate electrode is provided in a peripheral circuit area. And forming a pixel electrode connected to the first thin film transistor in the display area, wherein the first and second extending directions of the first gate electrode and the second gate electrode cross each other. A method of manufacturing a thin film transistor substrate for forming a second gate electrode is provided.

The method of forming the first and second active layers may include forming an amorphous silicon film on the entire surface of the substrate, and crystallizing the amorphous silicon film through an SLS method to form a low temperature polycrystalline silicon film having a plurality of crystallization protrusions. And patterning the low temperature polycrystalline silicon film.

A display device according to an embodiment of the present invention includes a substrate defined by a display area and a peripheral area, a gate line and a first thin film transistor provided in the display area, and a second thin film transistor provided in the peripheral area. The first gate electrode extends in one direction, and the second gate electrode of the second thin film transistor extends in a direction crossing the one direction, a color filter substrate provided on the thin film transistor substrate, and the thin film transistor. A display device including a liquid crystal layer provided between a substrate and a color filter substrate is provided.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as being on or above another part, not only when each part is directly above or directly above the other part but also another part between each part and another part This includes cases.

1 is a schematic plan view of a display panel according to an exemplary embodiment of the present invention, FIG. 2 is a plan conceptual view of a unit pixel in a display area according to an exemplary embodiment, and FIG. 3 is a plan conceptual view of a unit thin film transistor of a peripheral circuit area. to be.

1 to 3, the display panel according to the present exemplary embodiment includes a color filter substrate 200 and a thin film transistor substrate 100 defined as a display area D and a peripheral circuit area P. Referring to FIG. In this case, a gate line 130, a data line 150, a pixel thin film transistor 160, a pixel electrode 180, and a storage electrode line 132 are provided on the thin film transistor substrate 100 in the display area D. do. On the thin film transistor substrate 100 of the peripheral circuit region P, a peripheral circuit thin film transistor 260 including a gate electrode 231, a source electrode 251, and a drain electrode 253 is provided.

In this case, the pixel thin film transistor 160 and the peripheral circuit thin film transistor 260 are provided under the gate electrodes 131 and 231 to provide a channel through which carriers flow in one direction. At this time, the channel is made of a low temperature polycrystalline silicon film having a plurality of crystallization protrusions (see S in FIGS. 2 and 3) extending in a direction perpendicular to the crystal direction. Accordingly, in the present exemplary embodiment, the pixel thin film transistor 160 is manufactured such that the carrier movement direction of the channel of the pixel thin film transistor 160 and the extension direction of the crystallization protrusion S are parallel to each other. In addition, the peripheral circuit thin film transistor 260 is manufactured such that the carrier movement direction of the channel of the peripheral circuit thin film transistor 260 and the extension direction of the crystallization protrusion S intersect (that is, vertical).

In this embodiment, the case where the extension direction of the crystallization protrusion S extends in the longitudinal direction is considered. Of course, the present invention is not limited thereto, and the extending direction of the crystallization protrusion S may be extended in the horizontal direction. In this case, the extending direction of the crystallization protrusion S on the entire surface of the thin film transistor substrate 100 is preferably the same.

In this case, as shown in FIG. 2, when the extending direction of the crystallization protrusion S extends in the vertical direction in the display area D, the active layer 110 including the channel of the pixel thin film transistor 160 is extended. Pattern the direction vertically. The gate line 130 is patterned to extend in the vertical direction, and the data line 150 is patterned to extend in the horizontal direction perpendicular to the gate line 130. The gate electrode 131 extends from one side of the gate line 130 to the upper side of the channel region. That is, in FIG. 2, the extending direction of the gate line 130, the carrier moving direction of the channel, and the extending direction of the crystallization protrusion S are all parallel. To this end, the direction of the gate line 130 is rotated by 90 degrees as compared with the conventional, and accordingly, the extension direction of the active layer 110 provided with the channel is also rotated by 90 degrees. This is because the gate electrode 131 of the present embodiment is formed in a protrusion shape projecting in the vertical direction from the gate line 130 as shown in FIG. 2 and overlaps the upper side of the channel of the active layer 110.

In this way, the carrier movement direction of the channel in the active layer 110 and the extension direction of the crystallization protrusion S may be the same to prevent crystallization spots caused by the crystallization protrusion S. FIG.

 Of course, the present invention is not limited thereto, and the gate line 130 may extend in the horizontal direction, and the data line 150 may extend in the vertical direction. In this case, a portion of the gate electrode 131 protruding from the gate line 130 may be bent to overlap the channel region of the active layer 110 extending in the vertical direction.

Meanwhile, as shown in FIG. 3, in the peripheral circuit region P, the gate electrode 231 of the thin film transistor 260 for the peripheral circuit is disposed in the same longitudinal direction as the extension direction of the crystallization protrusion S of the active layer 210. The source electrode 251 and the drain electrode 253 are formed on both sides thereof. As a result, the moving direction of carriers in the channel region of the peripheral circuit thin film transistor 260 and the crystal direction of the active layer 210 coincide to improve the moving speed of the carriers in the channel region of the peripheral circuit thin film transistor 260. have.

In an exemplary embodiment, a unit pixel is defined in an intersection area between the gate line 130 and the data line 150 of the display area, and the pixel may have a horizontal length longer than a vertical length, and a vertical length may be horizontal. It can be longer than the length of the direction. In addition, the length in the horizontal direction and the vertical direction may be the same.

Hereinafter, a method of manufacturing a thin film transistor substrate of the present invention will be described with reference to the drawings.

4 to 7 are views for explaining a method for manufacturing a thin film transistor substrate of the present invention.

4 to 7 illustrate separate display regions and peripheral circuit regions, respectively, a plan view of unit pixels of the display region and a cross-sectional view of the LL line, respectively, illustrating a thin film transistor for circuits in the peripheral circuit region. The top view and the cross section which cut the top view with respect to MM line | wire are respectively shown.

Referring to FIG. 4, the active layer 110 and the sustain electrode pattern 120 are formed in the display area D of the thin film transistor substrate 100, and the active layer 210 is formed in the peripheral circuit area P. Referring to FIG.

As the active layers 110 and 210 and the storage electrode pattern 120, a low temperature polycrystalline silicon film is preferably used. In order to use the low temperature polycrystalline silicon film, an amorphous silicon thin film is first deposited on the substrate 100. Thereafter, the amorphous silicon thin film is crystallized through the SLS crystallization method. As described above, a plurality of linear crystallization protrusions S extending in the longitudinal direction of the substrate 100 are formed in the low-temperature polycrystalline silicon film crystallized by the SLS crystallization method. At this time, the spacing between the plurality of crystallization protrusions (S) is about 2 to 3um.

Thereafter, a photosensitive film is coated on the low temperature polycrystalline silicon film, and then a photolithography process using a mask is performed to form a first photoresist mask pattern. An etching process using the first photoresist mask pattern as an etching mask is performed to form the active layer 110 and the sustain electrode pattern 120 of the pixel thin film transistor in the display region D, and the peripheral circuit in the peripheral circuit region P. The active layer 210 of the thin film transistor is formed. Here, the active layer 110 formed in the display area D is formed in a substantially straight shape extending in the extending direction (ie, the vertical direction) of the crystallization protrusion S, and the sustain electrode pattern 120 is formed of the active layer 110. It is manufactured in the shape of a roughly plate extending from the end of). In this case, the width of the linear active layer 110 may be in the range of 1 to 4 μm according to the characteristics of the pixel thin film transistor. Therefore, the crystallization protrusion S may not be disposed in the active layer 110, and one or two crystallization protrusions S may be disposed in the active layer 110. As described above, in the present exemplary embodiment, the active layer 110 of the display area is patterned in the same direction as the extension direction of the crystallization protrusion S, so that the number of crystallization protrusions S provided in the active layer 110 can be reduced, and the plurality of active layers ( The crystallization protrusions S disposed in the 110 may be prevented from being regularly arranged to prevent the occurrence of crystallization stains.

The active layer 210 formed in the peripheral circuit region P is formed in a substantially plate shape. That is, as shown in Fig. 4, the length in the longitudinal direction is longer than the length in the horizontal direction is produced in a substantially rectangular shape. Of course, the present invention is not limited thereto, and the size and shape of the active layer 210 may vary depending on the size of the thin film transistor for peripheral circuits.

After removing the first photoresist mask pattern, the second photoresist mask pattern for opening the region of the sustain electrode pattern 120 of the display area D by applying a photoresist film over the entire structure and performing a photolithography process using a mask is obtained. Form. Impurity ions are implanted into the sustain electrode pattern through an ion implantation process using the second photoresist mask pattern as an ion implantation mask. At this time, the ion implantation step is preferably implanted N-type impurity ions, such as phosphorus (P) or arsenic (As). After the ion implantation process is completed, the second photoresist mask pattern is removed.

Of course, in the above description, the active layers 110 and 210 and the sustain electrode pattern 120 are patterned using two photoresist mask patterns, and impurity ions are implanted into the sustain electrode pattern 120. However, the present invention is not limited thereto and may be performed through a single mask. That is, patterning of the active layers 110 and 210 and the sustain electrode pattern 120 and impurity ion implantation into the sustain electrode pattern 120 may be simultaneously performed through a photoresist mask pattern having a step formed through a slit or a semi-transmissive mask. It may be.

Referring to FIG. 5, the gate insulating layer 121 is formed on the entire surface of the substrate 100 on which the active layers 110 and 210 and the storage electrode pattern 120 are formed. In this case, it is preferable to use an insulating film including a silicon oxide film and / or a silicon nitride film as the gate insulating film 121.

A first conductive film is formed on the gate insulating film 121. It is preferable to use at least any one of Mo, Cu, Al, Ti, Cr, and these alloys for the said 1st conductive film. At this time, the first conductive film may be formed in a single layer structure, or may be formed in a double or more multilayer structure. The first conductive layer is patterned to form the gate electrode 131, the gate line 130, and the storage electrode line 132 of the pixel thin film transistor in the display region D, and the peripheral circuit region P in the peripheral circuit region P. The gate electrode 231 of the thin film transistor is formed. That is, the photosensitive film is apply | coated on the said 1st conductive film, the photolithographic process using a mask is performed, and the photosensitive film mask pattern is formed. Thereafter, an etching process using the photoresist mask pattern as an etching mask is performed to form a gate line 130 in the display area D, a gate electrode 131 protruding from the gate layer 131, and a portion of the active layer 110 overlapping with the gate line 130. The sustain line 132 extends in the same direction as the gate line 130 and overlaps the sustain electrode pattern 120 and a portion thereof, and forms the gate electrode 231 in the peripheral circuit region P. FIG. .

In this case, the gate line 130 extends in the same longitudinal direction as the extending direction of the active layer 110. The gate electrode 131 of the display area D is formed in the form of two protrusions protruding in a horizontal direction from a portion of the gate line 130. Of course, the present invention is not limited thereto, and the pattern of the gate electrode 131 may vary. In this case, the gate electrode 131 overlapping the active layer 110 extends in a direction perpendicular to the extending direction of the crystallization protrusion S. The gate electrode 131 overlaps the active layer 110 with a portion thereof, and a channel of the thin film transistor for a pixel in which a carrier moves (that is, a current flows) in a region where the gate electrode 131 and the active layer 110 overlap. (111). The storage line 132 includes a protrusion in which the storage electrode pattern 120 and a portion thereof overlap. The gate electrode 231 of the peripheral circuit region P is formed in a straight line shape extending in the vertical direction, and is formed across the central region of the active layer 210. That is, the gate electrode 231 overlapping the active layer 210 extends in a direction parallel to the extending direction of the crystallization protrusion S. FIG. In addition, the region of the active layer 210 provided in the peripheral circuit region P and overlapping the gate electrode 231 becomes the channel 211 of the thin film transistor for peripheral circuit in which the carrier moves.

As described above, the gate electrodes 131 and 231 are formed, and then an ion implantation process is performed, so that the source regions 112 and 212 and the drain region 113 and the active regions 110 and 210 on both sides of the gate electrodes 131 and 231 are formed. 213).

The ion implantation process is preferably performed by separating (i.e., using a different mask) a process of implanting N-type impurity ions and a process of implanting P-type impurity ions according to the characteristics (carrier characteristics) of the transistor to be formed. . That is, the region in which the N-type impurity ions are to be implanted is opened using one mask pattern (not shown), and then the N-type impurity ions are implanted into the active layers 110 and 210 on both sides of the gate electrodes 131 and 231. Thereafter, a region in which P-type impurity ions are to be implanted is opened using another mask pattern (not shown), and then P-type impurity ions are implanted into the active layers 110 and 210 on both sides of the gate electrodes 131 and 231. Through this, N-type transistors and P-type transistors may be manufactured on the single substrate 100, respectively. Of course, the present invention is not limited thereto, and an ion barrier layer (not shown) may be formed on the gate electrode 1510 to perform ion implantation using the ion implantation mask, and a plurality of ion implants, that is, high concentration ion implantation and low concentration ion implantation, may be used. Injection may also be performed.

Referring to FIG. 6, an interlayer insulating layer 140 is formed on the entire surface of the substrate 100 on which the gate electrodes 131 and 231 are formed. Subsequently, a source electrode 151 and a drain electrode 153 connected to the source region 112 and the drain region 113, respectively, are formed through the interlayer insulating layer 140 in the display region D to form a thin film for pixels. The transistor 160 is fabricated and the data line 150 connected to the source electrode 151 is formed. In the peripheral circuit region P, a source electrode 251 and a drain electrode 253 connected to the source region 212 and the drain region 213 through the interlayer insulating layer 140 are formed to form a thin film for the peripheral circuit. The transistor 260 is manufactured.

As the interlayer insulating layer 140, an inorganic insulating material including a silicon oxide layer (SiO ₂ ) and / or a silicon nitride layer (SiN _x ) may be used. Of course, an organic insulating material may be used as the interlayer insulating layer 140. The interlayer insulating film 140 may be formed in a single layer or may be formed in a multilayer film.

In this embodiment, a single layer interlayer insulating film 140 is formed on the entire structure, and then a photosensitive film is coated on the interlayer insulating film 140. A photolithography process using a mask is performed to form a photoresist mask pattern that opens the source regions 112 and 212 and the drain regions 113 and 213. Source contact holes 152 and 252 which open portions of the source regions 112 and 212 in each of the display region D and the peripheral circuit region P by performing an etching process using the photoresist mask pattern as an etching mask; Drain contact holes 154 and 254 that open portions of the drain regions 113 and 213 are formed.

A second conductive layer is formed on the entire surface of the substrate 100 on which the interlayer insulating layer 140 is formed, and then patterned to form a linear data line 150 orthogonal to the gate line 130 of the display area D. A source electrode 151 protrudes from the data line 150 to be connected to the source region 112 through the source contact hole 151, and is connected to the drain region 113 through the drain contact hole 154. And a drain electrode 153 overlapping the sustain line 132 with a portion thereof. Source electrodes 251 are formed in both regions of the gate electrode 231 of the peripheral circuit region P to connect with the source region 212 through the source contact hole 252, and the drain contact hole 254 is formed. A drain electrode 253 connected to the drain region 213 is formed through the drain region 213. In the peripheral circuit region P of the present exemplary embodiment, a plate-shaped source electrode 251 and a drain electrode 253 are provided, and the source electrode 251 and the drain electrode 253 have a plurality of source contact holes 252 and drain contacts. The hole 254 is connected to the source region 212 and the drain region 213 of the active layer 210. In this case, in the peripheral circuit thin film transistor 260 of the peripheral circuit region P, the carrier moves from the source electrode 251 to the drain electrode 253. At this time, the carrier is moved in the vertical direction of the crystallization protrusion (S) may improve the mobility of the carrier.

Referring to FIG. 7, the passivation layer 170 is formed on the entire surface of the substrate 100 on which the thin film transistors 160 and 260 are formed, and is connected to the drain electrode 153 on the passivation layer 170 of the display area D. The pixel electrode 180 is formed.

That is, after forming the passivation layer 170, a pixel contact hole 181 exposing a portion of the drain electrode 153 is formed. The passivation layer 170 uses an inorganic insulating material or an organic insulating material. Thereafter, a light-transmissive conductive film including indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire structure. The transmissive conductive layer is patterned to form a pixel electrode 180 connected to the drain electrode 153 through the pixel contact hole 181.

In the above description, a thin film transistor formed on a thin film transistor substrate used in a liquid crystal display has been described as an example. However, the present invention is not limited thereto, and a driving circuit and a pixel driving transistor of various types of flat panel display devices such as OLEDs are described. Can be applied to

In addition, the liquid crystal display panel may be manufactured by bonding and sealing the common electrode substrate to the thin film transistor substrate having the above-described structure and then injecting liquid crystal into the region between the two substrates. In this case, the common electrode substrate is fabricated by forming red, green, and blue color filters on the transparent insulating substrate, and forming a common electrode thereon. In this case, the color filters preferably correspond to pixels of the thin film transistor substrate. In addition, a predetermined spacer may be further formed to maintain a cell gap between the two substrates when the two substrates are bonded to each other. In addition, it is preferable to use sealing members, such as a sealant, for the bonding sealing of two board | substrates.

Of course, the present invention is not limited thereto, and a liquid crystal display may be prepared by preparing a thin film transistor substrate and a common electrode substrate, and then dropping liquid crystal on one substrate, applying a sealing member to the edges of the other substrate, and then sealing the two substrates. .

As described above, the present invention can prevent the crystallization spots caused by the crystallization protrusion by making the direction of extension of the active layer of the thin film transistor in the display area parallel to the direction of the crystallization protrusion provided in the active layer.

In addition, the present invention can improve the performance of the thin film transistor by making the carrier movement direction of the thin film transistor in the peripheral circuit region perpendicular to the direction of the crystallization protrusion provided in the active layer.

Although described with reference to the embodiments, it will be understood by those skilled in the art that the present invention may be modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. .

Claims (8)

A substrate defined by a display area and a peripheral area; A gate line and a first thin film transistor provided in the display area; And A second thin film transistor provided in the peripheral region, The first gate electrode of the first thin film transistor extends in one direction, The second gate electrode of the second thin film transistor extends in a direction crossing the one direction. The method according to claim 1, Each of the first and second thin film transistors includes first and second active layers provided under the gate electrode and having crystallization protrusions extending in the same direction. The extending direction of the crystallization protrusion is a direction crossing the one direction. The method according to claim 2, And the first and second active layers are low temperature polycrystalline silicon films crystallized by a sequential lateral solidification (SLS) method. The method according to claim 1, The thin film transistor substrate of which the extending direction of the gate line is parallel to the extending direction of the second gate electrode. The method according to claim 1, A pixel electrode connected to the drain electrode of the first thin film transistor in the display area; A thin film transistor substrate having a holding line overlapping a drain electrode of the first thin film transistor and a portion thereof. Forming a first thin film transistor having a first active layer and a first gate electrode in a display area of the substrate, and forming a second thin film transistor having a second active layer and a second gate electrode in a peripheral circuit area; Forming a pixel electrode connected to the first thin film transistor in the display area, And forming the first and second gate electrodes such that the extending direction of the first gate electrode and the extending direction of the second gate electrode cross each other. The method according to claim 6, The method of forming the first and second active layers may include forming an amorphous silicon film on the entire surface of the substrate, crystallizing the amorphous silicon film through an SLS method to form a low temperature polycrystalline silicon film having a plurality of crystallization protrusions; A method of manufacturing a thin film transistor substrate comprising patterning a low temperature polycrystalline silicon film. And a substrate defined by a display area and a peripheral area, a gate line and a first thin film transistor provided in the display area, and a second thin film transistor provided in the peripheral area, wherein the first gate electrode of the first thin film transistor is in one direction. Extending to the second gate electrode of the second thin film transistor, the thin film transistor substrate extending in a direction crossing the one direction; A color filter substrate provided on the thin film transistor substrate; And And a liquid crystal layer disposed between the thin film transistor substrate and the color filter substrate.

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