KR20070066432A - Copper wiring formation method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and has an effect of improving reliability such as contact resistance between upper and lower copper wirings, EM (electromigration), and stress (SM).

According to an aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: forming a first interlayer insulating film having a first dual damascene pattern formed on a semiconductor substrate; Forming a first copper wiring inside the first dual damascene pattern; Removing an upper portion of the first interlayer insulating layer by a predetermined thickness to expose both sidewalls of the first copper interconnection; Forming a copper diffusion barrier layer on the first interlayer insulating layer including the first copper interconnection on which both sidewalls are exposed; Forming a second interlayer insulating film having a second dual damascene pattern exposing a portion of the first copper wiring on the copper diffusion preventing film; And forming a second copper wire inside the second dual damascene pattern.

Description

Method of forming copper wiring in semiconductor device

1 is a photograph showing an alignment error between a lower copper metallization and a via plug of a semiconductor device according to the related art.

2A through 2E are cross-sectional views illustrating processes for forming a copper wiring of a semiconductor device in accordance with an embodiment of the present invention.

<Code Description of Main Parts of Drawing>

100 semiconductor substrate 101 first interlayer insulating film

102: first copper wiring 103: diffusion barrier

104: second interlayer insulating film 105: first dual damascene pattern

106: second copper wiring 107: copper diffusion preventing film

108: third interlayer insulating film 109: second dual damascene pattern

110: third copper wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring of a semiconductor device, and more particularly, to a method for forming a copper wiring of a semiconductor device capable of improving reliability such as contact resistance between upper and lower copper wirings, EM (electromigration), and stress (SM). will be.

As high integration and high performance of semiconductor devices are required, the line width of the metal wiring is reduced and the resistance is increased. This increase in resistance increases the operation capacitance of the device by increasing the resistance capacitance (RC) delay time between the metal wirings. Will deteriorate.

Therefore, in order to reduce the RC delay time in a highly integrated, high performance semiconductor device, a copper (Cu) metal wiring having a lower resistivity than an aluminum (Al) metal wiring is applied. However, since copper cannot be patterned with current equipment, copper wiring is formed by forming a dual damascene pattern consisting of via holes and trenches in the insulating film and then filling the dual damascene pattern with copper. .

The dual damascene pattern for forming copper wirings of the semiconductor device may be formed by performing various process methods such as via first scheme to form via holes first and trenches later.

On the other hand, in forming the dual damascene pattern, it is very important to accurately align the via holes and trenches, but no matter how precisely the via holes and trenches are aligned, an alignment error may occur.

1 is a photograph showing an alignment error between a lower copper metallization and a via plug of a semiconductor device according to the related art.

As shown in FIG. 1, when an alignment error occurs between the lower metal wiring and the via plug formed on the upper portion, a parasitic fence (Fence) F is generated. When the parasitic fence F is generated, the contact area between the via plug and the lower metal wiring is reduced.

This phenomenon is caused by the fact that the contact radius between the lower metal wiring and the via hole is reduced to 0.13 μm when the via hole diameter is about 0.16 μm in the process technology of 0.09 μm or less. This increases the problem that the reliability of the process and the electrical characteristics of the device is degraded.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to prevent the occurrence of parasitic fence, and thus, the contact resistance, EM and SM, etc. generated during contact between upper and lower wirings in a copper wiring process. The present invention provides a method for forming a copper wiring of a semiconductor device that can improve reliability.

According to another aspect of the present invention, there is provided a method for forming a copper wiring of a semiconductor device, the method including: forming a first interlayer insulating film having a first dual damascene pattern formed on a semiconductor substrate; Forming a first copper wiring inside the first dual damascene pattern; Removing an upper portion of the first interlayer insulating layer by a predetermined thickness to expose both sidewalls of the first copper interconnection; Forming a copper diffusion barrier layer on the first interlayer insulating layer including the first copper interconnection on which both sidewalls are exposed; Forming a second interlayer insulating film having a second dual damascene pattern exposing a portion of the first copper wiring on the copper diffusion preventing film; And forming a second copper wire inside the second dual damascene pattern.

In addition, the etching process of the first interlayer insulating film is characterized in that the thickness of 50 to 1500Å.

In addition, the etching process of the first interlayer dielectric layer is performed using BOE as an etchant.

The forming of the copper diffusion barrier layer may include forming a copper diffusion barrier layer on the first interlayer insulating layer including the first copper wires on which both sidewalls are exposed; And CMPing the copper diffusion preventing film so that the copper diffusion preventing film remains on the upper portion of the first copper wiring by a predetermined thickness.

The copper diffusion preventing film may be formed to a thickness of 500 to 4000 kPa.

In addition, the thickness of the copper diffusion preventing film remaining on the first copper wiring is characterized in that 200 to 1000Å.

The first and second interlayer insulating films may be formed of any one selected from the group consisting of PE-TEOS, USG, and FSG.

In addition, the copper diffusion prevention film is characterized in that it is formed using SiN or SiC.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating processes for forming a copper wiring of a semiconductor device according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, first, a semiconductor substrate 100 is provided, and a first interlayer insulating film 101 is formed on the semiconductor substrate 100. Subsequently, after forming a trench (not shown) in the first interlayer insulating film 101, a copper film is embedded in the trench to form a first copper wiring 102. At this time, a barrier metal layer (barrier) between the first copper wiring 102 and the first interlayer insulating film 101 in order to prevent the copper component of the first copper wiring 102 from being diffused into the first interlayer insulating film 101. metal layer (not shown).

Subsequently, a diffusion barrier film 103 and a second interlayer insulating film 104 are sequentially deposited on the first interlayer insulating film 101 on which the first copper wiring 102 is formed. The diffusion barrier 103 is deposited using a SiN or SiC to a thickness of about 300 to 1000 Å, and the first and second interlayer insulating films 101 and 104 are formed of SiO ₂ such as PE-TEOS, USG, and FSG. It is preferable to deposit using a film in which fluorine, hydrogen, or the like is locally bonded to SiO ₂ to a thickness of about 6000 to 18000 Pa. Subsequently, a dual damascene process is performed on the diffusion barrier film 103 and the second interlayer insulating film 104 to form a first dual damascene pattern 105 formed of via holes and trenches in the second interlayer insulating film 104. To form.

Next, a barrier metal layer (not shown) is formed on the whole including the first dual damascene pattern 105, and a metal seed layer (not shown) is formed on the barrier metal layer inside the first dual damascene pattern 105. To form.

Thereafter, a copper film is formed on the metal seed layer so as to fill the first dual damascene pattern 105, and then the copper film is chemically polished until the second interlayer insulating film 104 is exposed. ) To form a second copper wiring 106 to fill the first dual damascene pattern 105.

Next, as shown in FIG. 2B, the upper portion of the second interlayer insulating layer 104 is etched by a predetermined thickness to expose both sidewalls of the upper portion of the second copper wiring 106.

The etching process of the second interlayer insulating film 104 may be performed by a wet etching process using an etchant such as BOE (Buffered Oxide Etchant), and the etching thickness of the second interlayer insulating film 104 is about 50 to 1500Å. It is preferable to adjust the thickness. Here, the copper constituting the second copper wiring 106 has a characteristic of having a strong etching resistance with respect to the BOE aqueous solution, and thus is not removed by the etching process.

Then, as shown in FIG. 2C, a copper diffusion preventing film 107 is deposited on the second interlayer insulating film 104 including the second copper wiring 106 with exposed both side walls thereon. The copper diffusion barrier 107 is preferably deposited to a thickness of about 500 to 4000 kPa.

Subsequently, as shown in FIG. 2D, the upper portion of the copper diffusion preventing film 107 is CMP so that the copper diffusion preventing film 107 remains on the second copper wiring 106 by a predetermined thickness. At this time, the thickness of the copper diffusion preventing film 107 remaining on the second copper wiring 106 is preferably 200 to about 1000 kPa.

Next, as shown in FIG. 2E, after the third interlayer insulating film 108 is deposited on the copper diffusion preventing film 107, the third interlayer insulating film 108 and the copper diffusion preventing film 107 are duplexed. The drinking process is performed to form a second dual damascene pattern 109 formed of a via hole and a trench in the third interlayer insulating layer 108. Thereafter, a third copper wiring 110 is formed by burying a copper film in the second dual damascene pattern 109.

As described above, in the present invention, after forming the second copper wiring 106, the upper portion of the second interlayer insulating film 104 is wet-etched by a predetermined thickness, so that both sides of the upper portion of the second copper wiring 106 are formed. A second dual damascene pattern 109 is formed by depositing a copper diffusion barrier 107 over the second interlayer insulating film 104, including the second copper interconnect 106 with exposed walls and both side walls. During the dual damascene process, the copper diffusion barrier 107 of the sidewalls of the second copper wiring 106 may be sufficiently etched. Therefore, as shown in the figure, even if an alignment error occurs between the via hole of the second dual damascene pattern 109 and the second copper wiring 106 below, the third copper wiring 110 and the second copper. It is possible to prevent the fence from being formed between the wirings 107 or to reduce the contact area.

The present invention is not limited to the above-described embodiments, but can be variously modified and changed by those skilled in the art, which should be regarded as included in the spirit and scope of the present invention as defined in the appended claims. something to do.

As described above, according to the method for forming copper wirings of the semiconductor device according to the present invention, the interlayer insulating films on both sides of the lower copper wirings are etched by a predetermined thickness to expose both side walls of the upper upper copper wirings, By depositing a copper diffusion barrier on the interlayer insulating film, including the exposed lower copper wiring, even if alignment errors occur between the via hole of the upper copper wiring and the lower copper wiring during the dual damascene process for forming the upper copper wiring, Since the copper diffusion prevention film of the lower copper wiring sidewall can be sufficiently etched, it is possible to prevent a fence from being formed between the upper copper wiring and the lower copper wiring, or to reduce the contact area.

Therefore, when the upper and lower wirings come into contact with each other, there is an effect of improving the reliability of contact resistance, EM and SM, etc. generated.

Claims (8)

Forming a first interlayer insulating film having a first dual damascene pattern formed on the semiconductor substrate; Forming a first copper wiring inside the first dual damascene pattern; Removing an upper portion of the first interlayer insulating layer by a predetermined thickness to expose both sidewalls of the first copper interconnection; Forming a copper diffusion barrier layer on the first interlayer insulating layer including the first copper interconnection on which both sidewalls are exposed; Forming a second interlayer insulating film having a second dual damascene pattern exposing a portion of the first copper wiring on the copper diffusion preventing film; And Forming a second copper wiring inside the second dual damascene pattern. The method of claim 1, The etching process of the first interlayer insulating film, the copper wiring forming method of a semiconductor device, characterized in that performed by a thickness of 50 to 1500Å. The method of claim 1, The etching process of the first interlayer dielectric layer is performed using BOE as an etchant. The method of claim 1, Forming the copper diffusion preventing film, Forming a copper diffusion barrier layer on the first interlayer insulating layer including the first copper interconnection on which both sidewalls are exposed; And And CMP the copper diffusion preventing film so that the copper diffusion preventing film remains on the first copper wiring by a predetermined thickness. The method of claim 4, wherein The copper diffusion preventing film is formed with a thickness of 500 to 4000 kPa. The method of claim 4, wherein The thickness of the copper diffusion prevention film remaining on the first copper wiring is a copper wiring forming method of a semiconductor device, characterized in that 200 to 1000Å. The method of claim 1, And the first and second interlayer insulating films are formed of any one selected from the group consisting of PE-TEOS, USG, and FSG. The method of claim 1, The copper diffusion preventing film is formed by using SiN or SiC copper wiring forming method of a semiconductor device.

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