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KR100815944B1 - Method for forming copper wiring layer used for semiconductor device - Google Patents

Method for forming copper wiring layer used for semiconductor device Download PDF

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KR100815944B1
KR100815944B1 KR1020060137273A KR20060137273A KR100815944B1 KR 100815944 B1 KR100815944 B1 KR 100815944B1 KR 1020060137273 A KR1020060137273 A KR 1020060137273A KR 20060137273 A KR20060137273 A KR 20060137273A KR 100815944 B1 KR100815944 B1 KR 100815944B1
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silicon nitride
trench
nitride film
oxide film
copper
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이용근
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자에 사용되는 구리 배선층을 형성하는 방법에 관한 것으로서, (A) 반도체 기판에 층간 절연막과 산화막을 도포하는 단계와, (B) 산화막 위에 제1 감광막 패턴을 형성하고, 제1 감광막 패턴을 마스크로 하여 산화막을 선택 식각하여 산화막에 트렌치를 형성하는 단계와, (C) 트렌치의 옆면과 밑면 및 산화막의 상부면을 모두 덮도록 실리콘 질화막을 도포하는 단계와, (D) 실리콘 질화막 위에 제2 감광막 패턴을 형성하고, 제2 감광막 패턴을 마스크로 하여 산화막과 실리콘 질화막을 선택 식각하여 트렌치 내부에 홀을 형성하고, 실리콘 질화막 패턴을 형성하는 단계와, (E) 트렌치와 홀을 모두 채우도록 구리 금속층을 도포하고, 구리 금속층을 표면 연마하여 트렌치와 홀 내부에만 구리 금속이 남도록 구리 금속층을 표면 연마하는 단계를 포함한다. 이렇게 하면, 실리콘 질화막 패턴이 트렌치의 옆면과 밑면을 모두 덮고, 산화막의 상부면을 모두 덮고 있는 이중 다마신 구조의 구리 배선층이 형성된다. 본 발명의 실리콘 질화막 패턴은 구리 금속층을 표면 연마할 때 연마 정지층으로 사용될 수 있을 뿐만 아니라, 구리의 측면 또는 하부 확산을 방지하는 확산 방지층으로도 사용될 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a copper wiring layer for use in a semiconductor device, the method comprising: (A) applying an interlayer insulating film and an oxide film to a semiconductor substrate; (B) forming a first photosensitive film pattern on the oxide film, wherein the first photosensitive film is formed. Selectively etching the oxide film using a pattern as a mask to form a trench in the oxide film, (C) applying a silicon nitride film to cover both side and bottom surfaces of the trench and the top surface of the oxide film, and (D) on the silicon nitride film Forming a second photoresist pattern, selectively etching an oxide film and a silicon nitride film using the second photoresist pattern as a mask to form a hole in the trench, and forming a silicon nitride film pattern, (E) filling both the trench and the hole Applying a copper metal layer, and surface polishing the copper metal layer to surface polish the copper metal layer so that only the copper metal remains inside the trench and the hole. It should. This forms a copper wiring layer having a double damascene structure in which the silicon nitride film pattern covers both side and bottom surfaces of the trench and covers both the top surface of the oxide film. The silicon nitride film pattern of the present invention can be used not only as a polishing stop layer when surface polishing a copper metal layer, but also as a diffusion barrier layer that prevents side or bottom diffusion of copper.

Description

반도체 소자에 사용되는 구리 배선층을 형성하는 방법{Method for Forming Copper Wiring Layers in Semiconductor Devices}Method for Forming Copper Wiring Layers Used in Semiconductor Devices {Method for Forming Copper Wiring Layers in Semiconductor Devices}

도 1a 내지 도 1e는 종래 구리 배선을 형성하는 공정을 보여주는 단면도.1A to 1E are cross-sectional views showing a process of forming a conventional copper wiring.

도 2a 내지 도 2g는 본 발명에 따라 구리 배선을 형성하는 공정을 보여주는 단면도.2A-2G are cross-sectional views illustrating a process of forming copper wirings in accordance with the present invention.

<도면의 주요 부호에 대한 설명><Description of Major Symbols in Drawing>

110: 반도체 기판 120: 층간 절연막110: semiconductor substrate 120: interlayer insulating film

140: 산화막 150: 트렌치(trench)140: oxide film 150: trench

160: 제1 감광막 165: 제2 감광막160: first photosensitive film 165: second photosensitive film

170: SiN 180: 홀170: SiN 180: hole

190: 구리190: copper

본 발명은 반도체 공정 기술에 관한 것으로서, 좀 더 구체적으로는 반도체 소자에 사용되는 구리 배선층을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor processing technology, and more particularly to a method for forming a copper wiring layer used for a semiconductor device.

반도체 집적회로(IC: Integrated Circuit) 소자 기술에서 배선 기술은 IC 소자 내의 회로들을 연결하거나 전원을 공급하고 신호를 전달하는 배선을 형성하는 기술을 말한다. IC 소자의 배선 재료로는 그 동안 알루미늄을 사용하였지만, 반도체 IC 소자의 집적도가 높아지고 동작 속도가 빨라지면서 배선 선폭이 크게 줄어들어 배선 및 콘택 저항이 증가하여 배선에 의한 신호 지연과 전력 손실 문제가 생기고 전기영동(EM: Electromigration) 등의 문제가 생기면서, 구리 배선에 대한 연구가 활발하게 진행되고 있다. 예컨대, 0.13㎛ 급의 로직 소자에서는 대부분 구리 배선과 유전율이 낮은 유전체(low-K dielectric)를 사용하고 있으며, 고집적 메모리 제품에서도 구리 배선의 사용이 점차 늘어나고 있다.In semiconductor integrated circuit (IC) device technology, a wiring technology refers to a technology for forming circuits for connecting circuits or supplying power and transmitting signals within an IC device. Although aluminum has been used as the wiring material for IC devices, the integration of semiconductor IC devices has increased and the operation speed is increased, so the wiring line width is greatly reduced, resulting in increased wiring and contact resistance, resulting in signal delay and power loss problems due to wiring. With the problem of electromigration (EM), research on copper wiring is being actively conducted. For example, most 0.13µm logic devices use copper wiring and low-k dielectrics, and copper wiring is increasingly used in highly integrated memory products.

구리는 알루미늄에 비해 저항이 약 62%로 낮을 뿐만 아니라, EM에 대한 저항성이 커서 고집적 및 고속 소자에 우수한 배선 신뢰성을 얻을 수 있고, 전해도금 특성이 좋고 동일하게 설계한 알루미늄에 비해 수율이 높다. 반면, 구리는 알루미늄과 달리 건식 식각이 어렵기 때문에 층간 절연막에 트렌치(trench)와 홀(hole)을 포함하는 다마신(Damascene) 구조를 형성하는 이중 다마신 공정에 의해 배선을 형성하는 것이 일반적이다.Copper not only has a low resistance of about 62% compared to aluminum, but also has high resistance to EM, thereby obtaining excellent wiring reliability for high-integration and high-speed devices, and having higher electroplating properties and higher yields than identically designed aluminum. On the other hand, since copper is difficult to dry etch unlike aluminum, it is common to form wirings by a dual damascene process in which a damascene structure including trenches and holes is formed in an interlayer insulating film. .

도 1a 내지 도 1e는 종래 구리 배선을 형성하는 공정을 보여주는 단면도이다.1A to 1E are cross-sectional views showing a process of forming a conventional copper wiring.

반도체 기판(10)과 층간 절연막(12) 위에 형성된 산화막(14)에 제1 감광막(photo- resist)을 도포하고 사진식각 기술로 제1 감광막 패턴(16)을 형성한다. 제1 감광막 패턴(16)을 식각 마스크로 하여 산화막(14)을 이방성 식각하여 홀(15)을 산화막(14)에 형성한다(도 1a). 제1 감광막 패턴(16)을 제거한 다음 홀(15) 내 부와 산화막(14) 위에 제2 감광막을 도포하고 사진식각 기술로 제2 감광막 패턴(18)을 형성한다(도 1b).A first photoresist is applied to the oxide film 14 formed on the semiconductor substrate 10 and the interlayer insulating film 12, and the first photoresist pattern 16 is formed by photolithography. The oxide film 14 is anisotropically etched using the first photosensitive film pattern 16 as an etching mask to form holes 15 in the oxide film 14 (FIG. 1A). After removing the first photoresist pattern 16, a second photoresist layer is coated on the inside of the hole 15 and the oxide film 14, and a second photoresist pattern 18 is formed by photolithography (FIG. 1B).

제2 감광막 패턴(18)을 마스크로 하여 산화막(14)을 식각하여 트렌치(19)를 형성한다(도 1c). 트렌치(19)를 형성한 다음에는 잔류 제2 감광막 패턴(18a)을 제거하고 구리 금속층(20)을 도포하고(도 1d), 화학기계적 연마(CMP) 공정을 통해 표면 평탄화하여 구리 배선층(20a)이 이중 다마신(damascene) 구조의 트렌치(19)와 홀(15) 내부에만 남도록 한다(도 1e).Using the second photosensitive film pattern 18 as a mask, the oxide film 14 is etched to form a trench 19 (FIG. 1C). After the trench 19 is formed, the remaining second photoresist layer pattern 18a is removed, the copper metal layer 20 is applied (FIG. 1D), and the surface is planarized through a chemical mechanical polishing (CMP) process to form the copper wiring layer 20a. It remains only inside the trench 19 and the hole 15 of this double damascene structure (FIG. 1E).

이러한 종래 구리 배선 공정에서는 CMP 표면 평탄화 과정에서 산화막(14)의 연성으로 인해 트렌치(19)의 상부 모서리 부근에서 구리 배선의 합선(short)이 생길 수 있다. 또한, 트렌치(19)와 홀(15) 내부에 존재하는 구리가 산화막(14)이나 층간 절연막(12)으로 확산되는 것을 막기 어렵다는 단점이 있다.In the conventional copper wiring process, short circuits of the copper wiring may occur near the upper edge of the trench 19 due to the ductility of the oxide layer 14 during the CMP surface planarization process. In addition, there is a disadvantage in that it is difficult to prevent the copper present in the trench 19 and the hole 15 from diffusing into the oxide film 14 or the interlayer insulating film 12.

본 발명은 이러한 종래 기술의 문제점을 극복하기 위한 것으로, 구리 배선층의 구리가 확산되는 것을 효과적으로 방지하는 것이 목적이다.The present invention is to overcome the problems of the prior art, and an object of the present invention is to effectively prevent the diffusion of copper in the copper wiring layer.

본 발명의 다른 목적은 구리 배선층이 형성되는 트렌치 상단부의 불균일한 프로파일을 개선하고, 트렌치 상부 모서리 부근에서 구리 배선의 합선 현상이 생기지 않도록 하는 것이다.Another object of the present invention is to improve the non-uniform profile of the trench upper portion where the copper interconnect layer is formed, and to avoid the short circuit phenomenon of the copper interconnect near the trench upper edge.

본 발명에 따른 구리 배선 형성 방법은 (A) 반도체 기판에 층간 절연막과 산화막을 도포하는 단계와, (B) 산화막 위에 제1 감광막 패턴을 형성하고, 제1 감 광막 패턴을 마스크로 하여 산화막을 선택 식각하여 산화막에 트렌치를 형성하는 단계와, (C) 트렌치의 옆면과 밑면 및 산화막의 상부면을 모두 덮도록 실리콘 질화막을 도포하는 단계와, (D) 실리콘 질화막 위에 제2 감광막 패턴을 형성하고, 제2 감광막 패턴을 마스크로 하여 산화막과 실리콘 질화막을 선택 식각하여 트렌치 내부에 홀을 형성하고, 실리콘 질화막 패턴을 형성하는 단계와, (E) 트렌치와 홀을 모두 채우도록 구리 금속층을 도포하고, 구리 금속층을 표면 연마하여 트렌치와 홀 내부에만 구리 금속이 남도록 구리 금속층을 표면 연마하는 단계를 포함한다. 이렇게 하면, 실리콘 질화막 패턴이 트렌치의 옆면과 밑면을 모두 덮고, 산화막의 상부면을 모두 덮고 있는 이중 다마신 구조의 구리 배선층이 형성된다. 즉, 종래에는 트렌치를 형성한 후 곧바로 구리 금속층을 형성하는 공정을 진행했는데, 본 발명에서는 트렌치를 형성한 다음 트렌치 내부에 실리콘 질화막을 형성하는 공정을 먼저 진행한다. The copper wiring forming method according to the present invention comprises the steps of (A) applying an interlayer insulating film and an oxide film to a semiconductor substrate, (B) forming a first photosensitive film pattern on the oxide film, and selecting the oxide film using the first photosensitive film pattern as a mask. Etching to form a trench in the oxide film, (C) applying a silicon nitride film to cover both the side and bottom surfaces of the trench and the top surface of the oxide film, (D) forming a second photoresist pattern on the silicon nitride film, Forming a hole in the trench by selectively etching the oxide film and the silicon nitride film using the second photoresist pattern as a mask; (E) applying a copper metal layer to fill both the trench and the hole; Surface polishing the metal layer to surface polish the copper metal layer so that only the copper metal remains inside the trench and the hole. This forms a copper wiring layer having a double damascene structure in which the silicon nitride film pattern covers both side and bottom surfaces of the trench and covers both the top surface of the oxide film. That is, in the related art, a process of forming a copper metal layer is performed immediately after forming the trench, but in the present invention, the process of forming the trench and then forming a silicon nitride film inside the trench is performed first.

본 발명의 실리콘 질화막 패턴은 구리 금속층을 표면 연마할 때 연마 정지층으로 사용될 수 있을 뿐만 아니라, 구리의 측면 또는 하부 확산을 방지하는 확산 방지층으로도 사용될 수 있다. The silicon nitride film pattern of the present invention can be used not only as a polishing stop layer when surface polishing a copper metal layer, but also as a diffusion barrier layer that prevents side or bottom diffusion of copper.

구현예Embodiment

이하 도면을 참조로 본 발명의 구체적인 구현예에 대해 설명한다.Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따라 구리 배선을 형성하는 공정을 보여주는 단면도이다.2A to 2G are cross-sectional views showing a process of forming a copper wiring according to the present invention.

도 2a를 참조하면, 반도체 기판(10) 위에 층간 절연막(120) 및 산화막(140)이 형성된 기판을 준비하고, 제1 감광막을 도포한 다음 이 제1 감광막을 사진 식각하여 제1 감광막 패턴(160)을 형성한다. 제1 감광막 패턴(160)은 트렌치가 형성될 영역은 노출되도록 하며, 나머지 산화막(140)은 제1 감광막 패턴(160)으로 덮이도록 한다. Referring to FIG. 2A, a substrate on which the interlayer insulating layer 120 and the oxide layer 140 are formed is prepared on the semiconductor substrate 10, the first photoresist layer is coated, and the first photoresist layer is photographed to etch the first photoresist layer pattern 160. ). The first photoresist pattern 160 may expose the region where the trench is to be formed, and the remaining oxide layer 140 may be covered by the first photoresist pattern 160.

도 2b는 참조하면, 제1 감광막 패턴(160)에 의해 도출된 산화막(140)의 일부분을 이방성 식각하여 트렌치(150)를 형성한다. 도면을 참조로 한 이 구현예에서는 트렌치(150)가 형성되는 하부 구조가 반도체 기판(10), 층간 절연막(120) 및 산화막(140)이 순차적으로 적층되어 있는 구조인 것으로 설명하였지만, 본 발명이 반드시 이러한 하부 구조에만 적용되는 것은 아니다. 예컨대, 2개 또는 3개 이상의 층간 절연막이 하부 구조에 포함되는 것에도 본 발명을 적용할 수 있다. 층간 절연막(120)은 저유전율의 유전체 예컨대, 유전율이 3.5 정도인 FSG(fluorine-doped silicon glass) 막이거나 실리콘 산화탄화물(SiOC) 막일 수 있다.Referring to FIG. 2B, a portion of the oxide film 140 derived by the first photoresist pattern 160 is anisotropically etched to form the trench 150. Although the lower structure in which the trench 150 is formed in this embodiment with reference to the drawings has been described as a structure in which the semiconductor substrate 10, the interlayer insulating film 120, and the oxide film 140 are sequentially stacked, the present invention It does not necessarily apply only to this infrastructure. For example, the present invention can also be applied to the case where two or three or more interlayer insulating films are included in the underlying structure. The interlayer insulating layer 120 may be a low dielectric constant, for example, a fluorine-doped silicon glass (FSG) film having a dielectric constant of about 3.5 or a silicon oxide carbide (SiOC) film.

도 2c를 참조하면, 트렌치(150)가 형성된 산화막(140) 전면에 실리콘 질화막(170)을 도포한다. 실리콘 질화막(170)은 예컨대, 플라즈마-강화 화학기상증착법(PE-CVD: Plasma Enhanced Chemical Vapor Deposition)으로 형성될 수 있다. 이 경우 실리콘용 가스로 SiH4, Si2H6와 같은 실란(silane) 가스를 사용한다. 유기 실란 가스(organic silane gas)를 사용하여 실리콘 질화막(170)을 형성할 수도 있다. 실리콘용 가스와 함께 질소나 암모니아를 질소 공급원으로 사용할 수 있다. PE- CVD 방법으로 실리콘 질화막(170)을 형성하면, 공정 온도를 산화막(140)을 형성하는 공정 온도와 유사한 온도로 유지할 수 있다.Referring to FIG. 2C, the silicon nitride layer 170 is coated on the entire surface of the oxide layer 140 on which the trench 150 is formed. The silicon nitride film 170 may be formed by, for example, plasma enhanced chemical vapor deposition (PE-CVD). In this case, a silane gas such as SiH 4 and Si 2 H 6 is used as the gas for silicon. The silicon nitride film 170 may be formed using an organic silane gas. Nitrogen or ammonia can be used as the nitrogen source with the gas for silicon. When the silicon nitride film 170 is formed by the PE-CVD method, the process temperature may be maintained at a temperature similar to the process temperature at which the oxide film 140 is formed.

PE-CVD 이외에도 고온 저압 화학기상증착법(hot-wall LPCVD: Low Pressure Chemical Vapor Deposition)으로 실리콘 질화막(170)을 형성하는 것도 가능하다. LPCVD 방법으로 실리콘 질화막(170)을 형성하면, 일정한 표면 평탄도와 좀 더 균질한 실리콘 질화막의 형성이 가능하다.In addition to PE-CVD, it is also possible to form the silicon nitride film 170 by hot-wall LPCVD (Low Pressure Chemical Vapor Deposition). If the silicon nitride film 170 is formed by the LPCVD method, it is possible to form a silicon nitride film with a constant surface flatness and more homogeneity.

도 2d를 참조하면, 앞에서 형성한 실리콘 질화막(170) 위에 제2 감광막을 도포하고 사진 식각 공정으로 제2 감광막을 선택 식각하여 제2 감광막 패턴(165)을 형성한다. 도면에서 보는 것처럼, 제2 감광막 패턴(165)은 홀이 형성될 영역의 실리콘 질화막(170) 부분은 노출되도록 한다.Referring to FIG. 2D, a second photoresist film is coated on the silicon nitride film 170 formed above, and the second photoresist film is selectively etched by a photolithography process to form a second photoresist film pattern 165. As shown in the figure, the second photoresist layer pattern 165 exposes the silicon nitride layer 170 in the region where the hole is to be formed.

도 2e를 참조하면, 제2 감광막 패턴(165)을 식각 마스크로 하여 실리콘 질화막(170)과 산화막(140)을 부분 식각하여 홀(180)을 형성한다. 도 2e에서 부호 '170a'는 홀(180)을 형성하는 과정에서 일부분이 제거되어 남은 실리콘 질화막 패턴(170a)을 가리킨다.Referring to FIG. 2E, the hole 180 is formed by partially etching the silicon nitride layer 170 and the oxide layer 140 using the second photoresist layer pattern 165 as an etching mask. In FIG. 2E, reference numeral 170a indicates a silicon nitride film pattern 170a that is partially removed while forming the hole 180.

도 2f를 참조하면, 트렌치(150)와 홀(180)을 채우고 실리콘 질화막 패턴(170a)을 모두 덮도록 구리 금속층(190)을 도포한다. 구리 금속층(190)은 예컨대, 전기화학 도금법(ECP: Electro Chemical Plating)으로 형성할 수 있다. 구리 금속층(190)을 형성하기 위해서는 씨앗층(seed layer)을 먼저 도포해야 하는데, 구리 씨앗층은 물리기상증착법(PVD: Physical Vapor Deposition)으로 형성할 수 있다. 구리 씨앗층은 구리 금속층(190)을 형성하기 위한 ECP 공정에서 전극의 역할 을 하며 웨이퍼 가장자리의 음극에서 나오는 전류를 웨이퍼 중앙에 위치한 양극으로 전도한다. 이 전류가 구리 전해도금용액에서 구리 이온을 발생시켜 구리 도금이 이루어진다.Referring to FIG. 2F, the copper metal layer 190 is coated to fill the trench 150 and the hole 180 and to cover all of the silicon nitride film pattern 170a. The copper metal layer 190 may be formed by, for example, electro chemical plating (ECP). In order to form the copper metal layer 190, a seed layer must be applied first, and the copper seed layer may be formed by physical vapor deposition (PVD). The copper seed layer serves as an electrode in the ECP process for forming the copper metal layer 190 and conducts current from the cathode at the edge of the wafer to the anode located at the center of the wafer. This current generates copper ions in the copper electroplating solution to form copper plating.

그 다음, 도 2g에 나타낸 것처럼, 구리 금속층(190)을 표면 연마(또는 표면 평탄화)하여 트렌치(150)와 홀(180) 내부에만 구리가 남도록 구리 배선층(190a)을 형성한다. 표면 연마는 화학기계적 연마 공정으로 하는 것이 바람직하다.Next, as shown in FIG. 2G, the copper metal layer 190 is surface polished (or surface planarized) to form a copper wiring layer 190a such that copper remains only in the trench 150 and the hole 180. Surface polishing is preferably a chemical mechanical polishing process.

지금까지 본 발명의 구체적인 구현예를 도면을 참조로 설명하였지만 이것은 본 발명이 속하는 기술분야에서 평균적 지식을 가진 자가 쉽게 이해할 수 있도록 하기 위한 것이고 발명의 기술적 범위를 제한하기 위한 것이 아니다. 따라서 본 발명의 기술적 범위는 특허청구범위에 기재된 사항에 의하여 정하여지며, 도면을 참조로 설명한 구현예는 본 발명의 기술적 사상과 범위 내에서 얼마든지 변형하거나 수정할 수 있다.Although specific embodiments of the present invention have been described with reference to the drawings, this is intended to be easily understood by those skilled in the art and is not intended to limit the technical scope of the present invention. Therefore, the technical scope of the present invention is determined by the matters described in the claims, and the embodiments described with reference to the drawings may be modified or modified as much as possible within the technical spirit and scope of the present invention.

본 발명에 따르면, 구리 금속층(190)을 실리콘 질화막 패턴(170a)을 모두 덮도록 형성되어 있으므로, 구리 배선층(190a)을 형성하기 위하여 구리 금속층(190)을 표면 연마할 때, 경성의 실리콘 질화막 패턴(170a)이 연성의 산화막(140) 위에 존재하기 때문에, 종래의 구리 배선 공정과는 달리 트렌치 상부가 손상되는 것을 방지할 수 있다. 따라서, 트렌치 상단부의 프로파일을 균일하게 유지할 수 있으며, 트렌치 상부 모서리 부근에서 구리 배선의 합선 현상이 생기지 않도록 할 수 있다.According to the present invention, since the copper metal layer 190 is formed to cover all of the silicon nitride film pattern 170a, when the surface of the copper metal layer 190 is polished to form the copper wiring layer 190a, the hard silicon nitride film pattern Since the 170a is present on the flexible oxide film 140, it is possible to prevent the upper portion of the trench from being damaged unlike the conventional copper wiring process. Therefore, the profile of the trench upper end can be kept uniform, and the short circuit of the copper wiring can be prevented from occurring near the trench upper edge.

또한, 실리콘 질화막 패턴(170a)은 트렌치(150)의 옆면과 밑면에 도포되어 있으므로, 구리가 측면이나 하부로 확산되는 것을 막을 수 있으며, 구리 금속층(190)을 표면 연마할 때 별도의 연마 정지층(CMP stopper)을 형성할 필요없이 실리콘 질화막 패턴(170a)을 연마 정지층으로 사용할 수 있다. In addition, since the silicon nitride film pattern 170a is applied to the side and bottom surfaces of the trench 150, the silicon nitride film pattern 170a may be prevented from spreading to the side or the bottom thereof, and a separate polishing stop layer may be used when surface polishing the copper metal layer 190. The silicon nitride film pattern 170a can be used as the polishing stop layer without the need for forming a (CMP stopper).

나아가, 구리의 확산을 방지하기 위한 별도의 확산 방지막을 형성할 필요가 없으므로, 공정이 간단하고 제조 비용을 줄일 수 있다. 구리는 확산 속도가 빠르기 때문에 트랜지스터의 부식 요인이 될 수 있으므로, 구리 배선 공정에서는 확산 방지막에 구리를 가두는 것이 일반적이다. 종래 구리 배선 공정에서는 구리 확산 방지막으로 Ta/TaN 막이나 TiN 막을 주로 사용하였다.Furthermore, since it is not necessary to form a separate diffusion barrier for preventing the diffusion of copper, the process is simple and the manufacturing cost can be reduced. Since copper may be a corrosion factor of a transistor because of its fast diffusion rate, it is common to trap copper in the diffusion barrier in the copper wiring process. In the conventional copper wiring process, a Ta / TaN film or a TiN film is mainly used as the copper diffusion preventing film.

Claims (5)

반도체 소자에 사용되는 구리 배선층을 형성하는 방법으로서,As a method of forming the copper wiring layer used for a semiconductor element, 반도체 기판에 층간 절연막과 산화막을 도포하는 단계와,Applying an interlayer insulating film and an oxide film to the semiconductor substrate, 상기 산화막 위에 제1 감광막 패턴을 형성하고, 제1 감광막 패턴을 마스크로 하여 산화막을 선택 식각하여 산화막에 트렌치를 형성하는 단계와,Forming a first photoresist pattern on the oxide film, and selectively etching the oxide film using the first photoresist pattern as a mask to form a trench in the oxide film; 상기 트렌치의 옆면과 밑면 및 상기 산화막의 상부면을 모두 덮도록 실리콘 질화막을 도포하는 단계와,Applying a silicon nitride film to cover both the side and bottom surfaces of the trench and the top surface of the oxide film; 상기 실리콘 질화막 위에 제2 감광막 패턴을 형성하고, 제2 감광막 패턴을 마스크로 하여 산화막과 실리콘 질화막을 선택 식각하여 상기 트렌치 내부에 홀을 형성하고, 실리콘 질화막 패턴을 형성하는 단계와,Forming a second photoresist pattern on the silicon nitride film, selectively etching an oxide film and a silicon nitride film using the second photoresist pattern as a mask to form holes in the trench, and forming a silicon nitride film pattern; 상기 트렌치와 홀을 모두 채우도록 구리 금속층을 도포하고, 구리 금속층을 표면 연마하여 트렌치와 홀 내부에만 구리 금속이 남도록 구리 금속층을 표면 연마하는 단계를 포함하는 구리 배선층 형성 방법.Applying a copper metal layer to fill both the trench and the hole, and surface polishing the copper metal layer to surface polish the copper metal layer so that only the copper metal remains inside the trench and the hole. 제1항에서,In claim 1, 상기 구리 금속층을 표면 연마하는 단계는 상기 실리콘 질화막 패턴을 연마 정지층으로 하여 구리 금속층을 표면 연마하는 단계인 것을 특징으로 하는 구리 배선층 형성 방법.The surface polishing of the copper metal layer is a step of surface polishing the copper metal layer using the silicon nitride film pattern as the polishing stop layer. 제1항 또는 제2항에서,The method of claim 1 or 2, 상기 실리콘 질화막은 플라즈마-강화 화학기상증착법으로 도포되는 것을 특징으로 하는 구리 배선 형성 방법.And the silicon nitride film is applied by plasma-enhanced chemical vapor deposition. 제1항 또는 제2항에서,The method of claim 1 or 2, 상기 실리콘 질화막은 고온 저압 화학기상증착법으로 도포되는 것을 특징으로 하는 구리 배선 형성 방법.The silicon nitride film is a copper wiring forming method, characterized in that the coating is applied by a high temperature low pressure chemical vapor deposition method. 제1항 또는 제2항에서,The method of claim 1 or 2, 상기 실리콘 질화막 패턴은 트렌치의 옆면과 밑면을 모두 덮고 있는 것을 특징으로 하는 구리 배선 형성 방법.And the silicon nitride film pattern covers both side and bottom surfaces of the trench.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059542A (en) * 1999-12-30 2001-07-06 박종섭 Method for forming metal line of semiconductor device
KR20040058991A (en) * 2002-12-27 2004-07-05 주식회사 하이닉스반도체 Method of forming capacitor of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059542A (en) * 1999-12-30 2001-07-06 박종섭 Method for forming metal line of semiconductor device
KR20040058991A (en) * 2002-12-27 2004-07-05 주식회사 하이닉스반도체 Method of forming capacitor of semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
한국특허공개공보 1020010059542호
한국특허공개공보 1020040058991호

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