KR20060112772A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

In the method of manufacturing a semiconductor device, a preliminary buffer layer having a first thickness is formed on a substrate. By etching the surface portion of the preliminary buffer layer, a buffer layer having a second thickness smaller than the first thickness is formed. The hard mask pattern formed on the buffer layer is used as an etching mask to form a buffer layer pattern and a trench for device isolation. A field insulating pattern filling the space between the trench, the buffer layer pattern, and the hard mask pattern is formed. By etching the hard mask pattern and the buffer layer pattern, an opening having a shape having a lower width than the upper width is formed. A dielectric film is formed on the bottom surface of the opening, and a conductive layer pattern is formed on the dielectric film to fill the opening. According to such a method, since the thickness of a buffer layer can be reduced, the profile of a conductive layer pattern can be improved and a coupling ratio can be improved.

Description

Method of manufacturing a semiconductor device

1 and 2 are cross-sectional views illustrating a method of forming a buffer layer according to an embodiment of the present invention.

3 is a graph showing the average thickness of each polysilicon layer per lot when the polysilicon layer is deposited on the semiconductor substrate at a target thickness of 180 GPa.

4A to 4E are graphics showing thickness distribution and etch dispersion appearing in all regions of a substrate when the polysilicon layer formed on the substrate is etched by a wet etching process using an NSC-1 solution.

5 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, following FIG. 2.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 100a device isolation region

100b: active region 102: pad oxide film

104: preliminary buffer layer 104a: buffer layer

106 middle temperature oxide film 108 mask layer

110: photoresist pattern 112: first opening

114: Trench 116: Field Oxidation Pattern

118a: second upper opening 118b: second lower opening

118: second opening 119: second inclination

120: first dielectric film 122: first conductive layer pattern

124: second dielectric film 126: second conductive layer

The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device having a floating gate made of self-aligned polysilicon (SAP).

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have relatively fast data input and output, while volatile memory devices lose data over time, and ROM Although data input and output is relatively slow, such as read only memory, it can be classified as a non-volatile memory device that can store data permanently. In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable and programmable ROM (EEPROM) or flash memory capable of electrically inputting / outputting data. The flash memory device has a structure for electrically controlling input and output of data by using F-N tunneling or channel hot electron injection.

In recent years, as the critical dimension (hereinafter referred to as "CD") of the floating gate of the flash memory is rapidly reduced to improve the integration of the semiconductor device, alignment misalignment and coupling ratio of the photolithography process are reduced. The failure of the semiconductor device due to the decrease of) has been an issue.

Accordingly, by forming the floating gate in the SAP process, some alignment problems could be solved. As an example of the flash memory device, according to US Pat. No. 6,465,293, a method of manufacturing a flash memory cell includes providing a semiconductor substrate on which an isolation layer is formed, and forming an oxide layer on the isolation layer and the semiconductor substrate. Forming an oxide pattern by patterning the oxide layer so that the semiconductor substrate of the portion where the floating gate is to be formed is exposed; sequentially forming a tunnel oxide layer and a first polysilicon layer on an entire upper surface thereof; Planarizing the first polysilicon layer until the tunnel oxide layer is exposed to form a floating gate, etching the tunnel oxide layer and the oxide pattern of the exposed portion by a predetermined thickness, and then depositing a dielectric layer on the entire upper surface Forming a second polysilicon layer, a tungsten silicide layer and a lower layer on the dielectric layer; Forming a control mask sequentially and then patterning to form a control gate; and implanting impurity ions into exposed semiconductor substrates on both sides of the floating gate to form a junction region.

According to US Pat. No. 6,465,293, the floating gate can be self-aligned by the oxide pattern that partially exposes the semiconductor substrate.

The flash memory device is programmed by applying an appropriate voltage to the control gate to insert or draw electrons into the floating gate. In this case, the dielectric layer serves to transfer a voltage applied to the control gate to the floating gate. In particular, the voltage delivered to the floating gate exhibits excellent electrical characteristics when no loss occurs.

The voltage delivered to the floating gate can sufficiently reduce the occurrence of losses by improving the coupling ratio. Here, the coupling coefficient R is expressed as in Equation 1 below.

R = C _ONO / (C _ONO + C _TO )

(Wherein, C _ONO represents the capacitance of the dielectric film and C _TO represents the capacitance of the tunnel oxide film pattern.)

The capacitance C of the dielectric film is expressed by Equation 2 below.

C = (ε × A) / T

(Wherein ε represents the dielectric constant of the dielectric film, A represents the area of the dielectric film, and T represents the thickness of the dielectric film.)

As can be seen from the above equations, the coupling ratio of the flash memory is deteriorated because the CD of the floating gate is reduced, thereby reducing the area A of the dielectric film formed on the floating gate.

As a method of improving the coupling ratio, there is a method of expanding the area of the dielectric film, a method of reducing the thickness of the dielectric film, and the like.

Examples of a method of increasing the area of the dielectric film to improve the coupling ratio are disclosed in Japanese Patent Laid-Open No. 2002-26151 and Japanese Patent Laid-Open No. 1997-102554. In particular, as disclosed in Japanese Patent Laid-Open No. 2002-26151, the floating gate may be formed in a “T” shape to expand the area of the dielectric film formed thereon.

As such, the coupling ratio reduction problem may be partially solved by expanding the effective area of the dielectric layer through a method of modifying the structure of the floating gate. However, since there are many additional processes for modifying the gate structure, there is an economic limit to apply the present in reality. Accordingly, various methods for obtaining the desired coupling ratio without significantly modifying the structure of the floating gate are still being studied.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device for extending the effective area of a dielectric film.

A semiconductor device manufacturing method according to an aspect of the present invention for achieving the above object is to form a preliminary buffer layer having a first thickness on a substrate, and by etching the surface portion of the preliminary buffer layer than the first thickness Forming a buffer layer having a small second thickness, forming a hard mask pattern on the buffer layer, and continuously anisotropically etching a portion of the buffer layer and a portion of the substrate using the hard mask pattern as an etching mask. Forming a trench for separating the buffer layer pattern and the device, forming a field insulation pattern filling the space between the trench, the buffer layer pattern, and the hard mask pattern, and etching the hard mask pattern and the buffer layer pattern. Thereby forming an opening having a shape having a lower width than the upper width, Forming a dielectric layer on a bottom surface of the opening and forming a conductive layer pattern filling the opening on the dielectric layer.

The forming of the opening may include etching the hard mask pattern to form an upper opening having a first slope with respect to the substrate, and etching the buffer layer pattern exposed on the bottom surface of the upper opening to be gentler than the first slope. And forming a lower opening communicating with the upper opening with a second slope having a slope.

According to one embodiment of the invention, the first thickness is 200 kPa to 1,000 kPa, and the second thickness is preferably 100 kPa to 200 kPa. The preliminary buffer layer may be etched through a wet etching process using a mixture of NH ₄ OH, H ₂ O _2, and H ₂ O.

In addition, after the upper opening is formed, a process of partially etching the field insulation pattern may be further performed so that the width of the upper opening is expanded.

After forming the conductive layer pattern, partially removing an upper portion of the field insulation pattern to partially expose the side surface of the conductive layer pattern, an upper surface of the field insulation pattern, an upper surface of the conductive layer pattern, and The method may further include forming a second dielectric layer on side surfaces of the exposed conductive layer pattern and forming a second conductive layer pattern on the second dielectric layer.

According to the present invention as described above, by forming a buffer layer of 200 mW or less, the profile of the conductive layer pattern can be improved. Therefore, the effective area of the dielectric film can be easily expanded to improve the coupling ratio of the semiconductor device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1, 2 and 5 to 13 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

1 is a cross-sectional view illustrating a pad oxide film and a preliminary buffer layer formed on a semiconductor substrate.

Referring to FIG. 1, a pad oxide layer 102 is formed on a semiconductor substrate 100 such as a silicon wafer. A preliminary buffer layer 104 having a first thickness is formed on the pad oxide layer 102.

The preliminary buffer layer 104 is a preliminary layer for forming a buffer layer to define a portion where a floating gate is formed, and then remove it to form an opening having a narrower width than a top thereof. That is, since the portion where the buffer layer is formed is etched, the lower portion of the opening becomes narrower than the upper portion, so that the lower width of the opening becomes narrower.

In this embodiment, a method of forming a buffer layer having a low thickness from the preliminary buffer layer is used to reduce the height of the gentle inclined portion below the opening. This will be described later in more detail. Here, the technique of reducing the height of the gentle inclined portion can be very useful for improving the coupling ratio by extending the effective area of the dielectric film in a flash memory device having a design rule of 90 nm or less.

Referring back to FIG. 1, the pad oxide layer 102 may be formed at about 70 kPa to about 130 kPa through a thermal oxidation process, a chemical vapor deposition (CVD) process, or the like. The pad oxide layer 102 may be performed at a temperature of about 750 ° C. to 900 ° C. for surface treatment of the semiconductor substrate 100.

The preliminary buffer layer 104 is preferably formed of a material having an etching characteristic different from that of the silicon oxide film and subsequently a silicon nitride film formed on a buffer layer (not shown). In particular, the preliminary buffer layer 104 is made of polysilicon. The preliminary buffer layer 104 is uniformly formed to a thickness of about 200 kPa to 1,000 kPa using a chemical vapor deposition process. In particular, the thickness of the preliminary buffer layer 104 is preferably about 200 kPa to about 300 kPa.

FIG. 2 is a cross-sectional view illustrating a buffer layer formed from the preliminary buffer layer illustrated in FIG. 1.

Referring to FIG. 2, the surface portion of the preliminary buffer layer 104 is etched to form a buffer layer 104a having a thickness smaller than that of the preliminary buffer layer 104. The process of etching the surface portion of the preliminary buffer layer 104 includes a wet etching process. As the wet etchant used in the wet etching process, an etchant known as a standard cleaning solution (SC-1) or a new standard cleaning solution (NSC-1) may be used. Wherein SC-1 comprises NH ₄ OH, H ₂ O ₂ and H ₂ O having a molar ratio of about 3-10: 1: 60-200, wherein NSC-1 has a molar ratio of about 4: 1: 95 NH ₄ OH, H ₂ O ₂ and H ₂ O having; In particular, it is preferable to use the NSC-1 solution to uniformly etch the preliminary buffer layer 104 formed of polysilicon over the entire area of the substrate.

In addition, when the thickness of the buffer layer 104a is 200 GPa or more, the effective area of the dielectric film is not sufficient, so that it is not easy to improve the coupling ratio. In addition, when the thickness of the buffer layer 104a made of polysilicon is less than 100 μs, the silicon nitride film formed on the buffer layer 104a may not sufficiently function as an etch buffer layer. Therefore, the thickness of the buffer layer 104a finally formed by the etching process using the NSC-1 is preferably about 100 kPa to about 200 kPa.

Hereinafter, the experiments for verifying the validity of the step of forming the buffer layer 104a described above will be described in detail with reference to FIGS. 3 and 4A to 4E.

First, without forming the preliminary buffer layer 104, a method of depositing the buffer layer 104a at a thickness of about 100 kPa to 200 kPa using a chemical vapor deposition process can be considered.

FIG. 3 is a graph for illustrating an average thickness distribution of polysilicon layers shown by lots when a polysilicon layer is formed on a semiconductor substrate with a target thickness of 180 kPa using a chemical vapor deposition apparatus. Here, the thickness measurement method was a nine-point measurement method (Center, Right, Left, Top, Top Right, Top Left, Bottom, Bottom Left, Bottom right).

Referring to FIG. 3, when the chemical vapor deposition process is performed with a target thickness of the polysilicon layer of 180 kPa, the average thickness for each lot is shown to be 170 kPa to 200 kPa. In other words, the difference between the maximum and minimum values of the average thickness of the lot is 30 ms. Since the measure of dispersion is just this range, according to the above experiments, the thickness distribution of the polysilicon layer is not desirable (the thickness difference between the wafers of each lot is not taken into account).

As such, when the thickness distribution of the polysilicon layer is poor, it is difficult to remove the polysilicon layer afterwards. The reason is that in order to completely remove the polysilicon layer, the etching amount should be controlled by targeting the polysilicon layer having the largest thickness over the entire area of the semiconductor substrate.

Therefore, by first depositing the preliminary buffer layer 104 and then wet etching the surface thereof, the buffer layer 104a having a thickness of 200 kPa or less can be formed while the thickness is easily spread.

The second experiment is a wet etching method using NSC-1 to show the formation of a polysilicon layer having excellent thickness distribution. Tables 1 and 2 below are tables showing experimental results of etching the polysilicon layer while varying the etching time using the NSC-1 as in the present embodiment. The experiment was performed by first depositing more than 2000 microseconds of polysilicon on a bare silicon wafer used as a semiconductor substrate, and then placing the wafer in the NSC-1 solution using a conventional wet etching station. The polysilicon layer is etched by immersion for 1 second and 1100 seconds.

Table 1

Average thickness Standard deviation Range Polysilicon deposition 2033 (first thickness) 2.27 7.57 NSC-1 150 " 1927 (second thickness) 1.82 6.72 NSC-1 1100 " 1272 (third thickness) 10.33 36.36

TABLE 2

Average etching rate (Å) Standard deviation Range NSC-1 150 " 103 1.17 6.20 NSC-1 1100 " 657 9.91 37.54

Referring to Tables 1 and 2, in order to accurately measure the etch rate of the NSC-1, a polysilicon layer was sufficiently formed on the substrate to a thickness of 2000 GPa or more. In this case, the standard deviation is 2.27 ms and the range is 7.57 ms. This is illustrated well in FIG. 4A which shows the color (first thickness) distribution of the polysilicon layer in color.

First, the second thickness measured after immersing the substrate in NSC-1 solution for 150 seconds was 1927 Å, which was also good with a standard deviation of 1.82 Å and a range of 6.72 도 (see FIG. 4B). Here, the average etch rate for NSC-1 150 sec was 103 ms, the etch standard deviation was 1.17 ms, and the etching range was 6.20 ms. This is illustrated in FIG. 4C, which shows the color dispersion of polysilicon over 150 seconds of the NSC-1 solution.

On the other hand, after submerging the substrate having the second thickness in the NSC-1 solution for 1100 seconds again, the measured third thickness was 1272Å, with a standard deviation of 10.33Å and a range of 36.36Å. Even after considering the standard deviation of 1.17 ms and the range of 6.20 ms that the second thickness had, the thickness distribution was very poor as a result of etching with NSC-1 for 1100 seconds (see FIG. 4D). Referring to FIG. 4E, the average etch rate for the NSC-1 1100 sec for the semiconductor substrate is 657 kV, the standard deviation is 9.91 kV, and the range is 37.54 kV.

In the above experiments, in order to show the experimental results, the polysilicon layer was first deposited by about 2000 kPa. In general, when the polysilicon is deposited by 300 kPa or more by chemical vapor deposition, the thickness distribution is similar to the above result. .

According to the above experimental results, first, when the polysilicon layer is deposited to about 300 GPa or more, and then etched with NSC-1 solution for about 150 seconds, it is possible to easily form a polysilicon layer having a thickness of about 200 GPa and having excellent thickness distribution. have.

Subsequently, FIG. 5 is a cross-sectional view for describing a mesophilic oxide film, a mask layer, and a photoresist pattern formed on the buffer layer shown in FIG. 2.

Referring to FIG. 5, a middle temperature oxide film 106 is formed on the buffer layer 104a. The middle temperature oxide film 106 may be formed of silicon oxide, and may be formed by a low pressure chemical vapor deposition (hereinafter referred to as "LP-CVD") method using SiH ₄ and NO ₂ gas. . The middle temperature oxide film 106 may be formed to a thickness of about 40 kPa to about 50 kPa.

Subsequently, a mask layer 108 is formed on the middle temperature oxide film 106. The mask layer 108 may be formed of silicon nitride, and may be formed through an LP-CVD process or a plasma enhanced chemical vapor deposition process using SiH ₂ Cl ₂ gas, SiH ₄ gas, NH ₃ gas, or the like. It may be formed to a thickness of about 1,000 to 2,000Å.

A photoresist pattern 110 is formed on the mask layer 108 to expose a portion of the surface of the mask layer 108 through a photolithography process.

FIG. 6 is a cross-sectional view for describing a mask pattern formed from the mask layer illustrated in FIG. 5.

Referring to FIG. 6, the mask layer 108, the buffer layer 104a, and the pad oxide layer 102 are sequentially etched through an etching process using the photoresist pattern 110 as an etch mask. A mask pattern 108a, a medium temperature oxide film pattern 106a, a buffer layer pattern 104b, and a pad oxide film pattern 102a are formed in the semiconductor substrate 100 to expose the device isolation region 100a.

Examples of the etching process include a dry etching process using a plasma and a reactive ion etching process. After the photoresist pattern 110 is formed, the mask pattern 108a is removed through an ashing process and a stripping process. In detail, the mask pattern 108a defines a first opening 112 that exposes the device isolation region 100a on the semiconductor substrate 100.

FIG. 7 is a cross-sectional view illustrating a trench formed in a semiconductor substrate using the mask pattern illustrated in FIG. 6, and FIG. 8 is a cross-sectional view illustrating a field insulation pattern filling a trench shown in FIG. 7.

7 and 8, the device isolation region 100a of the semiconductor substrate 100 is etched by performing an etching process using the mask pattern 108a as an etching mask to cross the semiconductor substrate 100. The trench 114 is formed in the first direction. The trench 114 may be formed to have a depth of about 1,000Å to 5,000Å. Preferably, it may be formed to have a depth of about 2,300Å.

Meanwhile, according to the above, after the first opening 112 is formed using the photoresist pattern 110, the trench 114 is formed using the mask pattern 108a. The first opening 112 and the trench 114 may be formed in-situ in the same process chamber using the pattern 110.

During the etching process to form the trench 114, heat to the inner surfaces of the trench 114 to heal silicon damage caused by high energy ion bombardment and to prevent leakage current generation. Oxidation treatment can be performed. By the thermal oxidation process, a trench oxide layer (not shown) having a thickness of about 50 GPa to 250 GPa is formed on the inner surfaces of the trench 114.

In addition, to prevent diffusion of impurities such as carbon or hydrogen from a subsequently formed film, for example, a field insulating film (not shown), into the active region 100b defined by the trench 114, on the trench oxide film. The liner nitride film (not shown) may be formed to a thickness of about 50 kPa to about 100 kPa.

A field insulating layer is formed on the semiconductor substrate 100 on which the trench 114 is formed to fill the trench 114 and the first opening 112. The field insulating layer may be formed of silicon oxide. Examples of the silicon oxide may include undoped silicate glass (USG), tetra-ethyl-ortho-silicate (TEOS), or high density plasma (HDP) oxide. Preferably, HDP oxides formed using SiH ₄ , O ₂ and Ar gases as plasma sources may be used.

Subsequently, the upper portion of the field insulating film is removed to expose the surface of the mask pattern 108a through a planarization process such as a chemical mechanical polishing (CMP) process, thereby functioning as a device isolation film in the trench 114. The field insulation pattern 116 defining the active region 100b of the substrate 100 is completed.

9 and 10 are cross-sectional views for describing a second opening that exposes an active region defined by the field insulation pattern illustrated in FIG. 8.

In the method of manufacturing a gate structure of a flash memory device according to the present embodiment, a conductive layer pattern serving as a floating gate is formed in the second opening 118 formed on the active region 100b by a damascene method. do. The second opening 118 is an opening formed separately from the first opening 112 formed on the isolation region 100a of FIG. 7 described above.

The second opening 118 formed according to the present embodiment has a gentle inclination at a portion where the side surface and the base surface contact each other. Accordingly, the first conductive layer pattern 122 using the second opening 118 as a formwork also has a gentle inclination at a portion where the base surface and the side surface contact each other.

In particular, through Figs. 9 and 10 will be described a mechanism in which the height of the portion where the gentle slope is formed is mainly determined by the buffer layer pattern height (thickness).

Referring to FIG. 9, the mask pattern 108a and the middle temperature oxide layer pattern 106a are removed to form a second upper opening 118a exposing the buffer layer pattern 104b. At this time, the side surface of the second upper opening 118a preferably has a first inclination of about 70 ° to 90 °. The second upper opening 118a may be formed through a dry etching process or a wet etching process, and is defined by the side surface of the field insulation pattern 116 and the top surface of the buffer layer pattern 104b.

For example, the mask pattern 108a may be removed through a wet etching process using an etching solution containing phosphoric acid and a diluted hydrofluoric acid solution, and the middle temperature oxide film pattern may be removed through a wet etching process using SC-1. 106a) can be removed.

The etching process may etch a surface portion of the field insulating pattern 116 in contact with the mask pattern 108a and the mid temperature oxide layer pattern 106a. This is typically because the etching process uses an overetching method to completely remove the mask pattern 108a and the middle temperature oxide layer pattern 106a. Accordingly, the width of the second upper opening may be extended by the amount of the etched field insulation pattern 116 as shown.

Referring to FIG. 10, the buffer layer pattern 104b and the pad oxide layer pattern 102a are removed to expose the active region 100b of the semiconductor substrate 100 and communicate with the second upper opening 118a. The lower opening 118b is formed. In detail, the buffer layer pattern 104b and the pad oxide layer pattern 102a may be removed through a dry etching process or a wet etching process. For example, the buffer layer pattern 104b may be removed through a wet etching process using nitric acid, hydrofluoric acid, and acetic acid, and the pad oxide layer pattern 102a may be removed through a wet etching process using SC1.

Thus, the second lower opening 118b is defined by the side surface of the field insulating pattern 116 and the upper surface of the active region 100b of the semiconductor substrate 100. That is, a second opening 118 is formed from the second upper and lower openings 119a and 118b communicating with each other.

Here, the side surface of the second lower opening 118b has a second slope having a gentler slope than the first slope. Preferably, the second inclination is formed at about 40 ° to about 70 °. Therefore, the second opening 118 has a shape in which the lower width is narrower than the upper width.

Specifically, the surface portion of the field insulating pattern 116 may be somewhat etched during the etching process, but the amount of the field insulating pattern 116 is etched is the mask pattern 108a and the mesophilic oxide pattern 106a. ) Is insignificant compared to the amount etched during the removal process. Therefore, the width of the second opening 118 is formed to be narrower than the width of the upper cross section of the second opening 118 parallel to the base surface. That is, the second opening 118 has a second inclined portion 119 extending from the bottom edge of the second upper opening 118a to the bottom surface of the second opening 118b.

As can be seen from the above, the height at which the second inclined portion 119 is formed is mainly determined by the height (thickness) of the buffer layer pattern 104b, and as the buffer layer pattern 104b has a low thickness, 2, the height of the inclined portion 119 may be reduced.

Meanwhile, according to the present exemplary embodiment, the second opening 118 may include a first etching step of the mask pattern 108a and the middle temperature oxide pattern 106a, and the buffer layer pattern 104b and the pad oxide layer pattern. It is formed through a two step removal process of the second etching step of 102a.

This is because the buffer layer pattern 104b serves as a buffer for the primary etching using a strong etchant, thereby preventing the bottom edge of the second opening 118 from sinking. When the depression occurs, the first dielectric film (not shown), which is subsequently formed on the bottom surface of the second opening 118, may not grow to a uniform thickness, and thus, the distribution of the threshold voltage may deteriorate thereafter. Can be. In order to prevent this, it is preferable to form the buffer layer 104a between the pad oxide film 102 and the intermediate temperature oxide film 106. In addition, by forming the buffer layer 104a as described above, the profile of the floating gate pattern formed in the second opening 118 may be improved, thereby improving the characteristics of the device. The profile of the floating gate pattern will be described below.

Next, FIG. 11 is a cross-sectional view for describing a first dielectric layer and a floating gate formed on the active region and field insulation patterns illustrated in FIG. 10.

Referring to FIG. 11, a first dielectric layer 120 functioning as a tunnel oxide layer is formed on the active region 100b of the semiconductor substrate 100 exposed through the second opening 118. As the first dielectric layer 120, a silicon oxide layer formed through a thermal oxidation process may be used. Other examples of the first dielectric layer 120 include a fluorine-doped silicon oxide film, a carbon-doped silicon oxide film, and a low-k material film.

The low dielectric constant material film may include polyallyl ether resin, cyclic fluorine resin, siloxane copolymer, polyallyl fluoride resin, polypentafluorostyrene, polytetrafluorostyrene resin, fluorinated polyimide resin, polynaphthalene fluoride, and polyside resin. It may be made of an organic polymer such as. The organic polymer may be formed by processes such as plasma enhanced-CVD (PE-CVD), atmospheric pressure-CVD (AP-CVD), spin coating, and the like.

A first conductive layer is formed on the first dielectric layer 120 and the field insulating pattern 116 to sufficiently fill the second opening 118. The first conductive layer may be formed through an LP-CVD process, and may be doped with a conventional doping method such as impurity diffusion, ion implantation, or in situ doping.

The first conductive layer is planarized to form a first conductive layer pattern 122 serving as a floating gate in the second opening 118. Specifically, the first conductive layer pattern 122 is formed in the second opening 118 by performing a planarization process such as a chemical mechanical polishing process so that the top surface of the field insulation pattern 116 is exposed.

As a result, a second inclined portion 119 is formed along the shape of the second opening 118 at the lower edge of the first conductive layer pattern 122. As a result, the first conductive layer pattern 122 has a profile having a lower width than that of the upper portion. The second inclined portion 119 affects the effective area of the second dielectric film in a subsequent process. This will be described in detail with reference to FIG. 12.

FIG. 12 is a cross-sectional view for describing a second dielectric film formed on the conductive layer pattern illustrated in FIG. 11.

Referring to FIG. 12, an upper portion of the field insulation pattern 116 is partially removed to partially expose the side surface of the first conductive layer pattern 122. The removal may be carried out through conventional isotropic or anisotropic etching process. For example, a wet etching method using a diluted hydrofluoric acid solution may be used as an upper portion of the field insulation pattern 116, and an etching process using the diluted hydrofluoric acid solution may be controlled by a preset etching time.

Partial removal of the field insulation pattern 116 is performed to improve the coupling ratio of the semiconductor device, eg, flash memory device, completed through subsequent steps. In other words, the second dielectric layer 124 formed on the surface of the first conductive layer pattern 122 by exposing a side surface of the first conductive layer pattern 122 by partially removing the upper portion of the field insulating pattern 116. Coupling ratio can be improved by extending the effective area of

At this time, the second dielectric layer 124 is hard to be deposited on the second inclined portion 119 formed on the side surface of the first conductive layer pattern 122. Accordingly, in order to increase the effective area of the second dielectric layer 124, the height D of the portion where the gentle inclination is formed in the first conductive layer pattern 122 is lowered, and the field insulation pattern 116 is formed in the first dielectric layer 124. It is preferable to remove as much as possible from the range which does not expose the two inclined portions 119. The etching process for this may be controlled by the concentration of the etching solution, the etching time and the etching temperature.

Subsequently, a second dielectric layer 124 is formed on the first conductive layer pattern 122 and the remaining portion of the field insulating pattern 116. As the second dielectric film 124, a composite dielectric film made of oxide / nitride / oxide (ONO), a high dielectric material film made of a high dielectric constant material, or the like may be employed.

The composite dielectric film may be formed by an LP-CVD process, and the high-k material film may be formed of Y ₂ O ₃ , HfO ₂ , ZrO ₂ , Nb ₂ O ₅ , BaTiO ₃ , SrTiO ₃ , and the like, and atomic layer deposition It may be formed by an atomic layer deposition (ALD) process or a CVD process.

As described above, the height D of the second inclined portion 119 is mainly determined by the thickness of the buffer layer 104a. Therefore, according to the present embodiment, since the buffer layer 104a can be formed to have a low thickness of about 100 kPa to about 200 kPa while having excellent dispersion, the effective area of the second dielectric film 124 can be further expanded. have.

FIG. 13 is a cross-sectional view for describing a second dielectric layer and a control gate layer formed on the floating gate illustrated in FIG. 12.

Referring to FIG. 13, doped polysilicon or tungsten silicide (WSi _X ), titanium silicide (TiSi _X ), cobalt silicide (CoSi _X ), and tantalum silicide (TaSi _X ) are formed on the second dielectric layer 124. A control gate layer including a second conductive layer 126 made of a metal silicide such as) is formed.

The second conductive layer 126 is patterned to form a control gate (not shown) extending in a second direction substantially perpendicular to the first direction on the second dielectric layer 124. In addition, the second dielectric layer 124, the first conductive layer pattern 122, and the first dielectric layer 120 are sequentially patterned to form a floating gate (not shown) from the first conductive layer pattern 122. Complete the gate structure of the device.

Although not shown, source / drain regions (not shown) are formed on the surface of the active region 100b of the semiconductor substrate 100 facing each other in the first direction with respect to the gate structure through an impurity doping process. A semiconductor device such as the flash memory device can be completed.

According to the present invention as described above, when the preliminary buffer layer is deposited to 300 Å or more, and then etched back using a wet etching process using NSC-1, a buffer layer having a low thickness of 200 Å or less can be formed with excellent thickness dispersion. have. Therefore, by adding only an etch back process, it is possible to form a floating gate having a profile that can effectively increase the effective area of the dielectric film formed between the floating gate and the control gate.

Further, by maximizing the effective area of the dielectric film, the coupling ratio of the flash memory device can be improved to improve the reliability of the semiconductor device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (9)

Forming a preliminary buffer layer having a first thickness on the substrate; Etching a surface portion of the preliminary buffer layer to form a buffer layer having a second thickness smaller than the first thickness; Forming a hard mask pattern on the buffer layer; Forming a trench for buffer layer pattern and device isolation by continuously anisotropically etching a portion of the buffer layer and a portion of the substrate using the hard mask pattern as an etch mask; Forming a field insulating pattern filling a gap between the trench, a buffer layer pattern, and a hard mask pattern; Etching the hard mask pattern and the buffer layer pattern to form an opening having a shape having a lower width than an upper width; Forming a dielectric film on the bottom surface of the opening; And And forming a conductive layer pattern filling the opening on the dielectric layer. The method of claim 1, wherein the preliminary buffer layer comprises polysilicon. The method of manufacturing a semiconductor device according to claim 1, wherein the first thickness is 200 kPa to 1,000 kPa. The method of manufacturing a semiconductor device according to claim 1, wherein the second thickness is 100 kPa to 200 kPa. The method of claim 1, wherein the preliminary buffer layer is etched through a wet etching process using a mixture of NH ₄ OH, H ₂ O _2, and H ₂ O. 6. The method of claim 1, wherein the forming of the opening comprises: Etching the hard mask pattern to form an upper opening having a first slope with respect to the substrate; And And etching the buffer layer pattern exposed on the bottom surface of the upper opening to form a lower opening communicating with the upper opening with a second slope having a gentler slope than the first slope. Method of preparation. The method of claim 6, wherein after forming the upper opening, And partially etching the field insulating pattern so that the width of the upper opening is expanded. The method of claim 1, wherein after forming the conductive layer pattern, And partially removing an upper portion of the field insulation pattern so that a side surface of the conductive layer pattern is partially exposed. The method of claim 8, wherein after partially removing an upper portion of the field insulation pattern, Forming a second dielectric film on an upper surface of the field insulation pattern, an upper surface of the conductive layer pattern, and a side surface of the exposed conductive layer pattern; And And forming a second conductive layer pattern on the second dielectric film.

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