KR100590396B1 - Manufacturing Method of Flash Memory Cells - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, wherein the width of a protrusion formed on an upper portion of a trench type isolation layer is narrowed to secure a wider area where a floating gate is to be formed, and the floating gate may be formed of a high concentration of By forming a stacked structure, the flash can increase the coupling ratio of the floating gate and simultaneously improve the interface characteristics of the floating gate and the tunnel oxide layer as well as the interface characteristics of the floating gate and the dielectric layer, thereby improving process reliability and device electrical characteristics. A method of manufacturing a memory cell is disclosed.

Flash Memory, Floating Gate, Interface Characteristics, Grain Boundary, Coupling Ratio

Description

Method of manufacturing a flash memory cell             

1A to 1M are cross-sectional views of devices for explaining a method of manufacturing a flash memory cell according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 102 pad oxide film

103: pad nitride film 104: trench

105: sacrificial oxide film 106: rounding oxide film

107: liner oxide film 108: insulating material

109: device isolation film 109a: protrusion

110 tunnel oxide film 111 first silicon layer

112: second silicon layer 113: lower oxide film

114 nitride film 115 upper oxide film

116: dielectric film 117: third silicon layer

118: silicide layer 119: control gate                 

120: floating gate

The present invention relates to a method of manufacturing a flash memory cell, and more particularly, to a method of manufacturing a flash memory cell capable of increasing the coupling ratio of the floating gate and improving the interfacial characteristics above and below the floating gate.

In all semiconductor device manufacturing processes, an element isolation film is formed in an element isolation region in order to electrically isolate each element formed on a semiconductor substrate. Conventionally, a device isolation film is formed by a local oxidation (LOCOS) process, but as the degree of integration of devices increases, the device isolation film is recently formed by etching a semiconductor substrate to a predetermined depth to form a trench, and then filling an insulating material in the trench. Form. Such an isolation layer is called a trench isolation layer.

In general, a trench type isolation layer is formed by forming a pad oxide layer and a pad nitride layer exposing a device isolation region on a semiconductor substrate, followed by etching the semiconductor substrate in the device isolation region, and then filling an insulating material layer. Even after the oxide film is removed, the insulating material layer embedded between the pad nitride film and the pad oxide film remains as it is. As a result, the device isolation layer formed of the insulating material layer is formed in the form of being embedded in the trench, and at the same time, the upper portion of the device isolation layer is formed to protrude higher than the surface of the semiconductor substrate.

In manufacturing a flash memory cell, when the device isolation layer is formed of the trench type device isolation layer described above, a first polysilicon layer mask and an etch for isolation of the floating gate may be used. In the mask patterning process, uniformity is degraded due to variation of the mask critical dimension (CD), making it difficult to form a uniform floating gate and changing the coupling ratio (Coupling). Problems such as program / erase fail occur due to ratio variation.

If the floating gate is not formed uniformly, the difference in the coupling ratio is intensified for each cell, and thus over erase may occur in some cells when the cell is programmed or erased. In addition, when the cell is manufactured with a low coupling ratio, the operation speed of the device is lowered, and operation of the device due to a low voltage is impossible, thereby lowering the electrical characteristics of the device.

In addition, when the device isolation layer is formed by a shallow trench isolation (STI) or a nitride spacer-local oxidation (NS-LOCOS) process, a recessed shape that is commonly generated at the boundary between the device isolation layer and the active region is used in a subsequent etching process. Due to the moat of the electrical characteristics of the device may be degraded or failure may occur.

In addition, when the floating gate is formed of doped polysilicon, it may be formed in the grain boundary region of the exposed portion of the doped polysilicon layer before the dielectric film (eg, the ONO film) is formed. Uneven oxide film is formed due to abnormal oxidation by segregated dopants. For this reason, when the dielectric film is formed, a phenomenon in which the thickness of the dielectric film changes locally occurs, and the amount of charge trapped in the grain boundary increases, which causes a problem of deteriorating the operating characteristics of the device.

Therefore, in order to solve the above problems, the present invention narrows the width of the protrusion formed on the trench isolation layer to secure a wider area for forming the floating gate, and stacks the floating gate with a high concentration of polysilicon layer and amorphous silicon layer. By forming the structure, the flash memory can improve the reliability of the process and the electrical characteristics of the device by simultaneously improving the interfacial characteristics of the floating gate and the dielectric layer as well as the interfacial characteristics of the floating gate and the tunnel oxide layer while increasing the coupling ratio of the floating gate. It is an object of the present invention to provide a method for manufacturing a cell.

A method of manufacturing a flash memory cell according to the present invention comprises the steps of forming a device isolation film protruding higher than the surface of the semiconductor substrate in the device isolation region of the semiconductor substrate and having a protrusion narrower than the width of the device isolation region; Forming a doped polysilicon layer and an undoped amorphous silicon layer on top of the whole, performing chemical mechanical polishing to expose the surface of the protrusion of the device isolation layer, and forming the protrusion of the device isolation layer. And removing the dielectric layer, the polysilicon layer for the control gate and the silicide layer on the entire surface, and patterning the silicide layer, the polysilicon layer for the control gate and the dielectric layer by an etching process using a control gate mask, and then etching the self alignment. Patterning doped polysilicon layer and amorphous silicon layer by process Characterized in that it comprises a step.

In the above, the height of the protrusion of the device isolation layer is characterized in that 1500 to 2000Å.

The doped silicon layer is formed in a concave structure in which a trench is formed in the center by a step generated by the protrusion of the device isolation layer, and the amorphous silicon layer is formed only in the trench, which is a concave portion of the doped polysilicon layer by chemical mechanical polishing And the impurities contained in the dope polysilicon layer are diffused into the undoped amorphous silicon layer during the subsequent thermal process.

On the other hand, the doped polysilicon layer is formed by LP-CVD so that impurities of 3.0E20 to 4.5E20 atoms / cc are doped using either SiH ₄ or Si ₂ H ₆ and PH ₃ gas as the source gas. It is characterized in that it is formed to a thickness of 500 to 800 Pa at a temperature of 580 to 620 ℃ and a low pressure of 0.1 to 3 Torr.

In addition, the undoped amorphous silicon layer is formed by the LP-CVD method using any one of SiH ₄ or Si ₂ H ₆ as the source gas at a temperature of 480 to 530 ℃ and a low pressure of 0.1 to 3 Torr, It is characterized by being formed to a thickness of 500 to 1000 내지.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

1A to 1M are cross-sectional views of devices for explaining a method of manufacturing a flash memory cell according to the present invention.

Referring to FIG. 1A, the pad oxide film 102 and the pad nitride film 103 are sequentially formed in order to suppress occurrence of crystal defects on the entire upper portion of the semiconductor substrate 101 and to perform surface treatment.

The pad oxide film 102 is formed to a thickness of 70 to 100 Pa, and is formed by a dry oxidation method or a wet oxidation method in a temperature range of 750 to 900 ° C. The pad nitride film 103 may be formed to a thickness of 2500 to 3200 GPa and may be formed using the LP-CVD method. At this time, the thickness of the pad nitride film 103 is not limited to the above conditions, and when the pad nitride film is removed after forming the device isolation film by performing a chemical mechanical polishing process as a final step in a subsequent step, the upper portion of the device isolation film is a semiconductor substrate. The thickness of the pad nitride film 103 may be determined according to process conditions so as to protrude as much as possible above the surface of 101.

In addition, a cleaning process may be performed before forming the pad oxide film 102. At this time, the cleaning process is sequentially performed with a hydrofluoric acid (DHF) and SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) solution H ₂ O: HF mixed in a ratio of 50: 1 to 100: 1 BOE (Buffered Oxide Etchant) and SC-1 diluted with H ₂ O at a ratio of 1: 100 to 1: 300 or mixed solution containing NH ₄ F: HF at 4: 1 to 7: 1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) The solution is carried out sequentially.

Referring to FIG. 1B, the pad nitride layer 103 and the pad oxide layer 102 are sequentially etched in an etching process using an element isolation mask to expose the device isolation region of the semiconductor substrate 101. As a result, the pad oxide film 102 and the pad nitride film 103 exposing the device isolation region of the semiconductor substrate 101 are formed in a stacked structure.

Thereafter, the exposed region of the semiconductor substrate 101 is etched to form the trench 104 at a predetermined depth. In this case, the pad nitride film 103 may have an etched surface perpendicular to each other, and the trench 104 may have a sidewall having an inclination angle of 80 to 90 degrees.

Referring to FIG. 1C, when the trench 104 is formed, in order to remove the etching damage generated on the sidewalls and the bottom surface of the trench 104 by an etching process in the process of forming the trench 104 in the semiconductor substrate 101. A sidewall sacrificial oxidation process is performed.

As a result, the surface of the damaged semiconductor substrate 101 on the sidewall and bottom of the trench 104 is oxidized to form the sacrificial oxide film 105. The side wall sacrificial oxidation process is carried out in a dry oxidation method at a temperature of 1000 to 1150 ℃, so that the semiconductor substrate 101 is oxidized about 150 to 300Å.

Referring to FIG. 1D, after the sacrificial oxide film (105 in FIG. 1C) formed by the sidewall sacrificial oxidation process is removed to a target thickness to remove the sacrificial oxide film, the bottom and top edges of the trench 104 are rounded. In order to perform the sidewall oxidation process. As a result, the semiconductor substrate 100 on the sidewalls and the bottom surface of the trench 104 is partially oxidized to form the rounding oxide film 106, thereby changing the trench 104 into a jar shape. On the other hand, while forming the rounded oxide film 106 by the sidewall oxidation process, the thickness of the pad oxide film 102 is also increased.

In this way, increasing the thickness of the pad oxide film 102 by the sidewall oxidation process is performed by the oxide film etching margin on the device formation region excluding the device isolation region in the cleaning process performed to narrow the protruding upper width of the device isolation layer in a subsequent process. To secure it. In addition, the upper edge of the device isolation layer may be etched by the cleaning process to prevent generation of recessed motes at the interface of the semiconductor substrate 101.

The sidewall oxidation process is performed such that the semiconductor substrate 101 is oxidized by about 300 to 450 Pa by a wet oxidation method at a temperature of 750 to 850 ° C.

After the sacrificial oxide film is removed, the cleaning process may be performed before the sidewall oxidation process is performed. At this time, the cleaning process is sequentially performed by the hydrofluoric acid (DHF) and SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) solution H ₂ O: HF mixed in a ratio of 50: 1 to 100: 1 BOE (Buffered Oxide Etchant) and SC- diluted with H ₄ O at a ratio of 1: 100 to 1: 300, or a mixed solution of NH ₄ F: HF in a ratio of 4: 1 to 7: 1. 1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) The solution is carried out using sequentially.

Referring to FIG. 1E, a liner oxide layer 107 is formed on the entire top including the sidewalls and the bottom of the trench 104. The liner oxide 107 improves the adhesion characteristics of the insulating material layer in the trench 104 region when the trench 104 is buried with the insulating material layer to form the device isolation layer in a subsequent process, and is subjected to the subsequent etching process. As a result, it is formed in order to prevent the occurrence of a moat formed by denting an interface between the device isolation layer and the semiconductor substrate. The liner oxide film 107 is formed of a hot temperature oxide (HTO) thin film made of DCS (SiH ₂ Cl ₂ ) as a source, and is formed to a thickness of 100 to 120 Pa. After the liner oxide film 107 is formed, annealing is performed for 20 to 30 minutes in a nitrogen (N ₂ ) gas atmosphere at a temperature of 1000 to 1100 ° C. to densify the liner oxide film 107 and improve film quality.

Referring to FIG. 1F, an insulating material layer is formed over the entire space such that the space between the pad oxide film 102 and the pad nitride film 103 and the trench 104 (FIG. 1E) are completely filled. In this case, the insulating material layer may be formed of a high density plasma (HDP) oxide film 108, and may be formed to a thickness of 5000 to 10000 Pa.                     

Thereafter, chemical mechanical polishing is performed to remove the high density plasma oxide film on the pad nitride film 103. After chemical mechanical polishing, a cleaning process using BOE or HF is performed to remove the oxide film that may remain on the exposed surface of the pad nitride film 103. As a result, the device isolation film 109 including the rounding oxide film 106, the liner oxide film 107, and the high density plasma oxide film 108 is formed.

Meanwhile, the height of the device isolation film 109 protruding onto the surface of the semiconductor substrate 101 after the pad nitride film 103 is completely removed in a subsequent process is determined according to the thickness of the pad nitride film 103 remaining after chemical mechanical polishing. do. Therefore, when the high-density plasma oxide film is removed during the chemical mechanical polishing and the pad nitride film 103 is exposed and the upper portion of the pad nitride film 103 is excessively removed, it protrudes higher than the surface of the semiconductor substrate 101. The height of the device isolation layer 109 is lowered. This also affects the height of the polysilicon layer for the floating gate to be formed in a subsequent process. Therefore, the process conditions of the chemical mechanical polishing process are controlled so that the protruding upper portion of the device isolation layer 109 is not lowered. Preferably, the protruding upper portion of the element isolation layer 109 is removed while the pad nitride layer 103 is removed. Process conditions are controlled such that the height is 1500 to 2000 mm 3.

Referring to FIG. 1G, the pad nitride film (103 in FIG. 1F) is removed. The pad nitride film is removed using phosphoric acid (H ₃ PO ₄ ). As a result, the upper portion of the device isolation film 109 protrudes 109a, and the surface of the pad oxide film 102 is exposed in the device formation region.

Referring to FIG. 1H, an etching process is performed to narrow the width of the protrusion 109a of the device isolation layer.

In this case, when the etching process is performed, the pad oxide layer 102 formed on the upper and side surfaces of the protrusion 109a of the device isolation layer and the upper portion of the semiconductor substrate 101 is etched at the same ratio, and the protrusion 109a of the device isolation layer has a target width. Adjust the time of the etching process until Meanwhile, the etching process is performed such that the protrusion 109a of the device isolation layer remains at a height of 1500 to 2000 GPa. This etching process sequentially dilutes hydrofluoric acid (DHF) and SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) solution with H ₂ O: HF mixed at a ratio of 50: 1 to 100: 1. Use it.

As a result, the edge of the device isolation film 109 is flattened to a height substantially similar to the surface of the semiconductor substrate 101, and the protrusion 109a of the device isolation film 109 protruding higher than the surface of the semiconductor substrate 101 has a wide width. Narrows. In this case, as the width of the protrusion 109a is narrowed, the spacing of the floating gate finally formed may be further narrowed, thereby improving the coupling ratio and the integration degree of the floating gate.

By forming the device isolation layer 109 in the above-described manner, an area in which the pattern can be formed wider than the active region of the semiconductor substrate 101 can be secured in the upper portion of the semiconductor substrate 101.

Subsequently, although not shown in the drawing, the pad oxide film 102 remaining on the semiconductor substrate 101 is removed by a cleaning process using an HF solution, and then 750 to 750 on the active substrate where the device is to be formed. A screen oxide (not shown) having a thickness of 50 to 70 kPa is formed by wet or dry oxidation at a temperature of 900 ° C. Once the screen oxide film is formed, a well (not shown) is formed in the semiconductor substrate 101 in the active region through an ion implantation process, and a threshold voltage adjusting layer (not shown) for adjusting the threshold voltage of a device such as a transistor or a flash memory cell is illustrated. Or not) is formed at a predetermined depth of the semiconductor substrate 101.

Referring to FIG. 1I, after the screen oxide layer (not shown) is removed, the tunnel oxide layer 110 and the first silicon layer 111 are sequentially formed on the active region of the semiconductor substrate 101. In this case, a step caused by the protrusion 109a of the device isolation layer is generated in the first silicon layer 111.

In the above, the screen oxide film is a dilute hydrofluoric acid (DHF) and SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O) solution in which H ₂ O: HF is mixed in a ratio of 50: 1 to 100: 1 Remove sequentially.

Meanwhile, the tunnel oxide film 110 is formed by a wet oxidation process at a temperature of 750 to 800 ° C., and then annealed for 20 to 30 minutes in a nitrogen atmosphere at a temperature of 900 to 910 ° C. to form the semiconductor substrate 101 and the tunnel oxide film ( Minimize the interface defect density. In addition, the first silicon layer 111 for forming the floating gate is formed of a polysilicon layer doped with a high concentration of impurities. In more detail, LP-CVD (Low Pressure Chemical Vapor Deposition) so that impurities of 3.0E20 to 4.5E20 atoms / cc are doped using either SiH ₄ or Si ₂ H ₆ and PH ₃ gas as the source gas. Form by law. In addition, the first silicon layer 111 is formed at a temperature of 580 to 620 ° C. and a low pressure of 0.1 to 3 Torr so as to minimize grain size so that the electric field is not concentrated in one place.

Referring to FIG. 1J, a second silicon layer 112 is formed on the first silicon layer 111. In this case, the second silicon layer 112 is formed to a thickness sufficient to completely fill the gap between the first silicon layer 111 having a step. Before the second silicon layer 112 is formed, a cleaning process may be performed to remove the native oxide film formed on the surface of the first silicon layer 111.

In the above, the second silicon layer 112 for forming the floating gate is formed of an amorphous silicon layer. In more detail, at a temperature of 480 to 530 ° C. and a low pressure of 0.1 to 3 Torr, any one of SiH ₄ or Si ₂ H ₆ is formed by LP-CVD using a source gas, and has a thickness of 500 to 1000 kPa. To form. At this time, the second silicon layer 112 is formed without impurities, but impurities implanted at a high concentration into the first silicon layer 111 in a subsequent thermal process are diffused into the second silicon layer 112 to form a second layer. The silicon layer 112 also becomes conductive. Even when impurities of the first silicon layer 111 are diffused into the second silicon layer 112, since the impurities are injected into the first silicon layer 111 at a high concentration, the impurity concentration or conduction characteristics of the first silicon layer 111 may be reduced. The problem does not occur.

Referring to FIG. 1K, chemical mechanical polishing is performed to expose the surface of the protrusion 109a of the device isolation layer 109. As a result, the first silicon layer 111 is isolated by the protrusion 109a of the device isolation layer, and the second silicon layer 112 is also isolated by the protrusion 109a of the device isolation layer, and between the protrusions 109a of the device isolation layer. The first and second silicon layers 111 and 112 are formed in a stacked structure. In more detail, the first silicon layer 111 is formed in a concave structure in which a trench is formed in the center by a step generated by the protrusion 109a of the device isolation layer, and the second silicon layer 112 is Only the trench, which is the concave portion of the first silicon layer 111, remains. In this case, the chemical mechanical polishing process is performed such that the stacked structure including the first and second silicon layers 111 and 112 remains between the protrusions 109a of the device isolation layer to a thickness of 1000 to 1400 kPa.

Referring to FIG. 1L, the upper surface of the device isolation layer 109a protruding higher than the surface of the semiconductor substrate 101 is exposed. The exposed protrusion 109a of the device isolation layer is removed in a cleaning process. The cleaning process is performed using HF or BOE. As a result, the side surface of the first silicon layer 111 that is in contact with the protrusion 109a of the device isolation layer 109 is exposed, thereby increasing the exposed area of the first silicon layer 111. Coupling ratios can be further improved.

Referring to FIG. 1M, the dielectric film 116, the third silicon layer 117 for the control gate, and the silicide layer 118 are sequentially formed on the entire top.

In the above, the dielectric film 116 may be formed in an ONO structure in which a lower oxide film (SiO ₂ ; 113), a silicon nitride film (Si ₃ N ₄ ; 114), and an upper oxide film (SiO ₂ ; 115) are sequentially stacked. have. In addition, the silicide layer 118 may be formed of a tungsten silicide (WSix) layer.

In this case, the lower and upper oxide films 113 and 115 are formed of hot temperature oxide (HTO) formed by using DCS (SiH ₂ Cl ₂ ) and N ₂ O gas having excellent internal pressure and TDDB (Time Dependent Dielectric Breakdown) characteristics as a source gas. Film), and the silicon nitride film 114 is formed by LP-CVD using DCS (SiH ₂ Cl ₂ ) and NH ₃ gas at a temperature of 650 to 800 ° C. and a low pressure of 1 to 3 Torr. After the dielectric film 116 is formed in the ONO structure, steam anneal may be performed by wet oxidation at a temperature of 750 to 800 ° C. in order to improve the interfacial properties between the films. On the other hand, the lower oxide film 113, the silicon nitride film 114 and the upper oxide film 115 are deposited to a thickness that matches the characteristics of the device, each process is carried out without time delay (no time delay) contaminated by natural oxide film or impurities Prevent it. At this time, preferably, the lower oxide film 113 is formed to a thickness of 35 to 60 GPa, the silicon nitride film 114 is formed to a thickness of 50 to 65 GPa, and the upper oxide film 115 is formed to a thickness of 35 to 60 GPa. In addition, the steam annealing is carried out so that the oxidation target thickness is 150 to 300 kPa based on Si w / f (Monitoring wafer).

Subsequently, although not shown in the drawing, an antireflection film (not shown) formed of SiOxNy or Si ₃ N ₄ is formed on the silicide layer 118 and then the antireflection film and silicide layer 118 are formed by an etching process using a control gate mask. ), The third silicon layer 117 and the dielectric film 116 are patterned to form the control gate 119 including the third silicon layer 117 and the silicide layer 118. Thereafter, the first and second silicon layers 111 and 112 are patterned by a self-aligned etching process using a patterned anti-reflection film to form the floating gate 120 formed of the first and second silicon layers 111 and 112. . In this way, a flash memory cell is manufactured.

According to the present invention, the following effects can be obtained through the above-described method for manufacturing a flash memory cell.

First, since only one device isolation mask is used to define the device isolation region in the process of forming the device isolation layer, the difficulty of the process may be reduced and the process cost may be reduced.

Second, active critical dimensions can be minimized by forming a device isolation layer as a trench type device isolation layer.

Third, the thickness of the pad oxide layer may be increased in the process of performing the sidewall oxidation process to round the upper and bottom sidewalls of the trench, thereby preventing the occurrence of the moat on the edge of the device isolation layer when the pad nitride layer is removed. In this case, a small sized device can be easily implemented, and a uniform floating gate can be formed on the substrate by minimizing the critical dimension variation.

Fourth, by forming a uniform floating gate to prevent the coupling ratio from changing, maintaining a uniform value can improve device characteristics.

Fifth, by forming a floating gate in a stacked structure of a dope polysilicon layer and an undoped amorphous silicon layer, the grain size is minimized at the interface with the tunnel oxide film, and the grain boundary is formed at the interface with the dielectric film. By minimizing the grain boundary portion, the dielectric film can be uniformly formed and the BV stabilization effect can be obtained.

Sixth, the inclination of the trench upper edge formed during the sidewall oxidation process can reduce the capacitance of the tunnel oxide layer by reducing the active critical dimension to maximize the coupling ratio.

Seventh, it is easy to adjust process conditions such as the thickness of the pad nitride film, the height and width of the protrusion of the device isolation layer, and the polishing thickness of the chemical mechanical polishing process, thereby securing a process margin such as adjusting the surface area of the floating gate.

Eighth, it is possible to easily manufacture high density flash memory cells of 0.13um or more, while securing process margins using existing equipment and processes without adding complicated processes or expensive equipment.

Claims (8)

Forming a device isolation layer in the device isolation region of the semiconductor substrate, the device isolation layer having a protrusion protruding higher than the surface of the semiconductor substrate and narrower than the width of the device isolation region; Forming a tunnel oxide film over the entire surface; Sequentially forming a doped polysilicon layer and an undoped amorphous silicon layer over the whole; Performing chemical mechanical polishing to expose the surface of the protrusion of the device isolation layer; Removing the protrusion of the device isolation layer; After forming a dielectric film, a control gate polysilicon layer and a silicide layer on the whole, patterning the silicide layer, the control gate polysilicon layer and the dielectric film by an etching process using a control gate mask, and a self-aligned etching process And patterning the doped polysilicon layer and the amorphous silicon layer. The method of claim 1, The height of the protruding portion of the device isolation layer is 1500 to 2000Å, characterized in that the flash memory cell manufacturing method. The method of claim 1, The doped silicon layer is formed in a concave structure in which a trench is formed in the center by a step generated by the protrusion of the device isolation layer, and the amorphous silicon layer is formed of the doped polysilicon layer by the chemical mechanical polishing. A method of manufacturing a flash memory cell, characterized in that it remains only in the trench, which is a recess. The method of claim 1, The impurity contained in the doped polysilicon layer is diffused into the undoped amorphous silicon layer in a subsequent thermal process. The method according to any one of claims 1, 3 and 4, The doped polysilicon layer is formed by LP-CVD so that impurities of 3.0E20 to 4.5E20 atoms / cc are doped using either SiH ₄ or Si ₂ H ₆ and PH ₃ gas as the source gas. Method of manufacturing a flash memory cell. The method of claim 5, wherein And the doped polysilicon layer is formed to a thickness of 500 to 800 kPa at a temperature of 580 to 620 ° C. and a low pressure of 0.1 to 3 Torr. The method according to any one of claims 1, 3 and 4, The undoped amorphous silicon layer is flash memory, characterized in that formed by the LP-CVD method using any one of SiH ₄ or Si ₂ H ₆ as a source gas at a temperature of 480 to 530 ℃ and low pressure of 0.1 to 3 Torr Method of making a cell. The method of claim 7, wherein And the undoped amorphous silicon layer is formed to a thickness of 500 to 1000 microseconds.

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