KR20060074990A - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention is to provide a method of manufacturing a semiconductor device suitable for preventing the occurrence of a bridge between the bit line contact by the gap formed at the interface of the layer of the oxide layer when forming the bit line contact hole through the laminated oxide film, the semiconductor of the present invention for this A device manufacturing method includes forming a first oxide film and a second oxide film on a semiconductor substrate by laminating them; Etching the stacked first and second oxide layers to form bit line contact holes through which the semiconductor substrate is exposed; Forming a nitride film spacer on sidewalls of the bit line contact holes; And cleaning the bit line contact hole in which the nitride layer spacer is formed with a BOE solution.

Bitline contact hole, line width adjustment, bridge, wet chemical

Description

 Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}             

1A to 1D are process cross-sectional views and TEM photographs illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2E are cross-sectional views and TEM photographs showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 device isolation film

23: gate insulating film 24: gate conductive film

25 gate hard mask 26 spacer

27: first interlayer insulating film 28: landing plug

29: second interlayer insulating film 30: spacer nitride film

31: Barrier Metal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a method of forming a bit line contact hole, and more particularly, a semiconductor device in which bit line contact holes formed in a peripheral region are intended to prevent adjacent holes and bridges from occurring. It relates to a manufacturing method.

DRAM (Dynamic Random Access Memory), etc. in the semiconductor memory collection is largely divided into a cell region including a plurality of unit cells composed of 1T1C (one transistor and one capacitor) and a peripheral region including other unit elements. .

For example, a bitline is a line connected to the source side of a cell transistor to actually transmit data. On the cell region side, a source / drain junction region on the side of a gate electrode (eg, a wordline) for electrical connection of such a bitline. An electrical connection between the bitline sense amplifier and the bitline is provided on the periphery side, including a bitline sense amplifier for sensing and amplifying the cell data transmitted through the bitline and a cell contact plug contacted to the bit contact. A contact is required for the connection.

1A to 1D are cross-sectional views and TEM photographs of a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a device isolation film 12 is formed on the semiconductor substrate 11 to locally separate the field region and the active region. The gate insulating layer 13 is formed on the semiconductor substrate 11 in the cell region. The gate conductive film 14 and the gate hard mask 15 are stacked and a gate pattern G1 having a spacer 16 on the sidewall thereof is formed.

The gate insulating film 13, the gate conductive film 14, and the gate hard mask 15 are stacked on the semiconductor substrate 11 in the peripheral region, and the gate pattern G2 having the spacers 16 is formed on the sidewall thereof. .

In the cell region, a landing plug 18 connected to the semiconductor substrate 11 through the first interlayer insulating layer 17 and flattened with the gate hard mask 15 is formed.

A second interlayer insulating film 19 is formed on the landing plug 18 and the first interlayer insulating film 17.

Subsequently, as shown in FIG. 1B, a first bit line contact hole is formed in the cell region to selectively etch the second interlayer insulating layer 19 to expose the landing plug 18. In the peripheral region, a second interlayer insulating layer is formed. A second bit line contact hole is formed to selectively etch 19 and the first interlayer insulating film 17 to expose a portion of the substrate. Subsequently, when performing the cleaning process before depositing the barrier metal, a BOE solution for etching a small amount of the oxide film is used, and the first and second layers are laminated by the wet etching of the wet chemicals. The gap A is caused by etching between the interlayer insulating layers 17 and 19.

Subsequently, as shown in FIG. 1C, the barrier metal 20 is deposited along the profile of the BCL2. The gap A generated during side etching by the wet chemical is filled with the barrier metal 20 having a relatively good sidewall step coverage. This may cause bridges with adjacent bit line contact holes and cause a fatal operation of the DRAM since leakage current (Leakage Current) may cause an increase in the bit line contact resistance.

FIG. 1D is a TEM photograph in which a gap is generated between the stacked oxide layers 17 and 19 due to the wet chemical of the BOE solution during cleaning.

As described above, after forming the second bit line contact hole in the peripheral region, there is a gap between the interlayer insulating layers stacked by the wet chemical during the cleaning process before depositing the barrier metal, thereby forming a gap between adjacent bit line contacts. A bridge is occurring.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and is a semiconductor device suitable for preventing the occurrence of bridges between bit line contacts due to the occurrence of gaps at the interface of the stacked oxide layers when forming the bit line contact holes penetrating the laminated oxide films. It is an object to provide a manufacturing method.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: stacking a first oxide film and a second oxide film on a semiconductor substrate, and etching the stacked first and second oxide films. Forming an exposed bit line contact hole, forming a nitride spacer on a sidewall of the bit line contact hole, and cleaning the bit line contact hole on which the nitride film spacer is formed with a BOE solution.                     

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, an element isolation film 22 is formed on the semiconductor substrate 21 on which various elements for forming a semiconductor element are formed, which locally separates a field region and an active region.

Subsequently, a gate insulating film 23, a gate conductive film 24, and a gate hard mask 25 are stacked on the semiconductor substrate 21, and a gate pattern G1 having a spacer 26 is formed on the sidewall thereof.

In the method for forming the gate pattern G1, the gate conductive layer 24 and the gate hard mask 25 are sequentially deposited on the gate insulating layer 23, and then a mask pattern for forming the gate pattern is formed through a photolithography process. The gate pattern G1 having a stacked structure of the gate hard mask 25, the gate conductive film 24, and the gate insulating film 23 by etching the gate conductive film 24 and the gate hard mask 25 using the mask pattern as an etch mask. ).

The gate conductive layer 24 includes a single or combined structure of polysilicon, tungsten, tungsten silicide, Ti, TiN, and the like, and the gate hard mask 25 includes an insulating layer based on a nitride layer or an oxide layer.

Subsequently, an insulating film is deposited along the profile of the gate pattern G1 in the form of a nitride film or an oxide film alone or in combination, and then an etch back process is performed to form spacers 26 on the sidewalls of the gate pattern. The spacer 26 is formed to prevent the gate pattern G1 from being attacked in a subsequent etching process.

Subsequently, the gate insulating film 23, the gate conductive film 24, and the gate hard mask 25 are stacked on the semiconductor substrate 21 in the peripheral region, and the gate pattern G2 having the spacers 26 is formed on the sidewall thereof. It is.

Subsequently, a first interlayer insulating film 27 is formed over the cell region and the peripheral region. The first interlayer insulating film 27 includes an oxide-based insulating film or an organic or inorganic low-k dielectric film.

When the first interlayer insulating film 27 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, a BOSG (Boro-Phopho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and TEOS (Tetra-Ethyl-Ortho-Silicate) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film, or APL (Advanced Planarization Layer) film, etc. It is available.

Subsequently, in order to secure a subsequent photolithography process margin, the upper portion of the first interlayer insulating layer 27 is planarized by using a CMP or an entire surface etching process.

Subsequently, a mask pattern (not shown) for forming a landing plug is formed on the planarized first interlayer insulating layer 27, and the first interlayer insulating layer 27 is etched using the mask pattern as an etch mask to form a gate pattern G1 in the cell region. After exposing the semiconductor substrate 21 between the layers, the mask pattern is removed and the plug forming conductive film is formed on the entire surface, and then the planarization process is performed to expose the gate hard mask 25 to separate the plug 28. Isolation.

Subsequently, a second interlayer insulating film 29 is deposited on the landing plug 28 and the first interlayer insulating film 27, and then the upper portion of the second interlayer insulating film 29 is planarized. The second interlayer insulating film 29 uses the same material as the material of the first interlayer insulating film 27.

Subsequently, as shown in FIG. 2B, the second interlayer dielectric layer 29 is selectively etched in the cell region to form a first bit line contact hole exposing the landing plug 28, and in the peripheral region, the second interlayer dielectric layer 29 is formed. The 29 and the first interlayer insulating layer 27 are selectively etched to form second bit line contact holes exposing a portion of the semiconductor substrate 21.

After forming the second bit line contact hole, cleaning is performed to remove the photoresist residue (not shown) used during the second bit line contact hole etching without etching the interlayer insulating films 27 and 29.

Subsequently, a spacer nitride film 30 is deposited along the sidewalls of the second bit line contact hole subjected to the cleaning process. For uniform deposition, a nitride film (Nitride) by LPCVD, which has a high step coverage and a compact structure, is used.

By depositing the spacer nitride layer 30 in the second bit line contact hole, it is possible to prevent defects due to wet chemical penetration during the subsequent second bit line contact hole cleaning process without exposing the second bit line contact hole sidewalls. The spacer nitride film 30 is formed to a thickness of 10 kPa to 100 kPa.

Subsequently, as shown in FIG. 2C, the spacer is etched back with a blanket to remove the spacer nitride layer 30 at the bottom of the second bit line contact hole. Due to the characteristic of the dry etching having the directionality, the nitride layer 30 of the bottom surface of the second bit line contact hole may be removed without removing the spacer nitride layer 30a of the sidewall of the second bit line contact hole.

Subsequently, FIG. 2D is a TEM photograph after the process of FIG. 2C, and protects the interface B of the interlayer insulating films 27 and 29 on the side surfaces of the second bit line contact holes except the bottom surface of the second bit line contact holes. It can be seen that the spacer nitride film 30 is deposited.

Subsequently, as shown in FIG. 2E, the spacer nitride film 30 blocks the interface between the first and second interlayer insulating films 27 and 29 when the cleaning is performed, thereby preventing the penetration of the wet chemical to prevent the wet chemical from being penetrated by the side wet etching. Prevents bridges between neighboring bitline contacts.

Subsequently, barrier metal 31 is deposited along the resulting profile. Barrier metal (31) between the Ti film, TiN film, TiSi use alone, or a combined structure such as a _second film and to thin the deposition thickness of barrier metal 31 and since the bit line is embedded in the contact hole conducting film Minimize contact resistance.

As described above, by depositing a spacer nitride film inside the second bit line contact hole, it is possible to prevent the bridge between the bit line contacts causing a fatal fail in DRAM operation.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a spacer nitride film is formed in the bit line contact hole in the peripheral area, thereby preventing defects occurring between adjacent bit line contact holes through sidewalls, thereby improving the yield of the semiconductor device.

Claims (3)

Stacking a first oxide film and a second oxide film on the semiconductor substrate; Etching the stacked first and second oxide layers to form bit line contact holes through which the semiconductor substrate is exposed; Forming a nitride film spacer on sidewalls of the bit line contact holes; And Cleaning the bit line contact hole in which the nitride film spacer is formed with a BOE solution Semiconductor device manufacturing method comprising a. The method of claim 1, The nitride film spacers are formed by LPCVD. The method of claim 1, The nitride film spacer is a semiconductor device manufacturing method for forming a thickness of 10 ~ 100Å.

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