KR20060023004A - Method of forming contact plug of semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device capable of suppressing the attack of the oxide film due to the difference in the polishing selectivity of the oxide film and the nitride film in the contact plug forming process aligned between the conductive patterns having a spacer having a multi-structure spacer including the oxide film and the resulting defects. In order to provide a method for forming a contact plug, the present invention includes: forming a plurality of neighboring conductive patterns having a hard mask thereon on a substrate on which a conductive film is formed; Forming a spacer having a spacer nitride film / buffer oxide film / sealing nitride film structure along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on the etch stop film; Performing a planarization process on a target to which the upper portion of the conductive pattern is exposed; a gap is generated due to excessive removal of the buffer oxide film due to a difference in polishing selectivity between the spacer nitride film, the buffer oxide film, and the sealing nitride film; Forming a filling nitride film by atomic layer deposition to sufficiently fill the gap; Selectively etching the peeling nitride film, the spacer nitride film, the buffer oxide film, and the sealing nitride film to form a contact hole exposing the conductive film; And forming a contact plug connected to the conductive layer through the contact hole by performing a planarization process to a target to which the upper portion of the conductive pattern is exposed.

SAC, contact hole, plug, peeling nitride film, sealing nitride film, buffer oxide film, spacer nitride film, spacer, atomic layer deposition (ALD).

Description

FIELD OF CONTACT PLUG FORMATION OF SEMICONDUCTOR DEVICES             

1A to 1C are cross-sectional views illustrating a cell contact forming process according to the prior art.

Figure 2 is a SEM photograph showing a cross section of the process of Figure 1c is completed.

FIG. 3 is a SEM photograph showing a cross section of a semiconductor device in which an electrical short is generated between a plug and a gate conductive film by a SAC fail. FIG.

4A to 4E are cross-sectional views illustrating a cell contact plug forming process according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

400: substrate 401: field insulating film

402 active region 403 gate insulating film

404: gate conductive film 405: gate hard mask

406: sealing nitride film 407: buffer oxide film

408 spacer nitride film 409 interlayer insulating film

412: peeling nitride film 415: contact plug                 

S: spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of preventing SAC fail when forming a contact hole using a Self Align Contact (SAC) process. It is about.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rules decrease in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 80nm is required. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 80 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). There is a need for additional requirements of suppression of deformation of the resulting photoresist. Accordingly, in the fabrication of semiconductor devices of 80 nm or less, the development of process conditions for simultaneously satisfying the existing requirements and the new requirements of pattern deformation prevention has become a major problem in terms of etching.

Meanwhile, as the high integration of semiconductor devices is accelerated, various elements of the semiconductor devices have a stacked structure, and thus, a contact plug (or pad) concept has been introduced.

In addition, in order to form such a contact, it is difficult to etch between structures having a high aspect ratio. In this case, an SAC process for obtaining an etching profile using an etching selectivity between two materials, for example, an oxide film and a nitride film, has been introduced.

For the SAC process, CF and CHF-based gases are used, and an etch stop film and a spacer using a nitride film are required to prevent an attack on the conductive pattern below.

For example, in the case of a gate electrode, spacers of nitride layers are formed on upper and side surfaces thereof, and spacers are used in a structure in which a plurality of nitride layers are stacked as the aspect ratio increases, and due to stress generation between the nitride layers or between the nitride layer and the substrate. A buffer oxide film is used between nitride films in consideration of cracks and the like and reliability of the device. A representative example thereof is a spacer having a triple structure of a nitride film / oxide film / nitride film. In order to prevent cell contact attack, an etch stop layer based on a nitride film is further formed on the triple structure.

Hereinafter, a cell contact process using a gate electrode structure having a spacer and an etch stop layer having the above-described structure will be described. FIGS. 1A to 1C are cross-sectional views illustrating a cell contact forming process according to the prior art.

First, as shown in FIG. 1A, a gate hard mask 104 / gate conduction is formed on a semiconductor substrate 100 on which various elements for forming a semiconductor device, for example, a field insulating film 101 and a well (not shown), are formed. Gate electrode patterns G1 to G4 in which the film 103 / gate insulating film 102 are stacked are formed.

The gate insulating film 102 uses a conventional oxide-based material film such as a silicon oxide film, and the gate conductive film 103 typically uses polysilicon, W, WN, WSi _x, or a combination thereof.

The gate hard mask 104 is used to protect the gate conductive layer 103 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for subsequent contact formation, and the etching speed is significantly different from that of the interlayer insulating layer. Use For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region 105 such as a source / drain junction is formed in the substrate 100 between the gate electrode patterns G1 to G4.

A spacer S having a nitride film / oxide film / nitride film structure of the sealing nitride film 106, the buffer oxide film 107, and the spacer nitride film 108 is formed along the profile in which the gate electrode patterns G1 to G5 are formed.

Subsequently, in the etching process using the subsequent SAC method on the entire surface where the spacer nitride film 108 is formed, the etch stop serves as an etch stop to prevent attack of the underlying structures such as the spacer nitride film 108 and the gate electrode patterns G1 to G5. A film 109 is formed. In this case, the etch stop layer 109 may be formed along the profile of the spacer nitride layer 108, and a nitride layer-based material layer may be used as the etch stop layer 109.

Next, as illustrated in FIG. 1B, an oxide-based interlayer insulating film 110 is formed on the entire structure where the etch stop film 109 is formed.

When the interlayer insulating film 110 is used as an oxide-based material film, a BSG (Boro-Silicate-Glass) film, BPSG (Boro-Phopho-Silicate-Glass) film, PSG (Phospho-Silicate-Glass) film, TEOS (Tetra) -Ethyl-Ortho-Silicate (HDP) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film, or APL (Advanced Planarization Layer) film, etc. have.

Subsequently, a photoresist pattern 111 for forming a cell contact plug is formed on the interlayer insulating layer 110. An anti-reflection film is usually used between the photoresist pattern 111 and the layer below it, but is omitted here for the sake of simplicity.

Subsequently, the interlayer insulating film 110, the etch stop film 109, and the spacer S and the gate insulating film 102 are etched using the photoresist pattern 111 as an etch mask to form a gap between the adjacent gate electrode patterns G1 to G4. A contact hole 112 is formed to expose the impurity diffusion region 105.                         

Subsequently, the photoresist pattern 111 is removed through an ashing process. When an organic material is used as the antireflection film, the photoresist pattern 111 is removed like the photoresist pattern 111 in this ashing process.

Subsequently, as shown in FIG. 1C, a plug forming conductive material is deposited on the entire surface where the contact hole 112 is formed to sufficiently fill the contact hole 112, and then planarize to a target to which the gate hard mask 104 is exposed. The process may be performed to form a plug 113 electrically connected to the impurity diffusion region 105 through the contact hole 112 and having the gate hard mask 104 and the top flat.

During the planarization, a chemical mechanical polishing (CMP) process is used.

On the other hand, since the spacer S has a nitride / oxide / nitride structure, even when the same polishing condition is applied in the CMP process for the isolation of the plug 113, the attack is performed as shown by reference numeral 114 in the buffer oxide film 107. Occurs

FIG. 2 is a SEM photograph showing a cross section of a process in which the process of FIG. 1C is completed.

2, it can be seen that the recess 114 occurs in the buffer oxide layer 107 during the CMP process.

This phenomenon can be confirmed that occurs even when using a slurry having a high selectivity in the CMP process, in particular, the defect is accelerated in the hydrofluoric acid-based wet cleaning step after the CMP process.

Meanwhile, the recess 113 causes an attack to the spacer S, the gate hard mask 104, and even the gate conductive layer 103 along the recessed portion in a subsequent process.

FIG. 3 is a SEM photograph showing a cross section of a semiconductor device in which an electrical short is generated between a plug and a gate conductive film by a SAC fail.

Referring to FIG. 3, as the gate hard mark 104 is lost due to the SAC fail, the gate conductive layer 103 is exposed to short-circuit the plug P with 'X'.

The present invention has been proposed to solve the above problems of the prior art, an oxide film due to the difference in the polishing selectivity of the oxide film and the nitride film in the contact plug forming process aligned between the conductive pattern having a spacer having a multi-structure spacer including the oxide film It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device capable of suppressing the attack and the occurrence of defects.

In order to achieve the above object, the present invention comprises the steps of: forming a plurality of neighboring conductive patterns having a hard mask on the substrate on the conductive film is formed; Forming a spacer having a spacer nitride film / buffer oxide film / sealing nitride film structure along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on the etch stop film; Performing a planarization process on the target to expose the upper portion of the conductive pattern—a gap is generated because the buffer oxide film is excessively removed due to a difference in polishing selectivity between the spacer nitride film, the buffer oxide film, and the sealing nitride film; Forming a filling nitride film by atomic layer deposition to sufficiently fill the gap; Selectively etching the peeling nitride film, the spacer nitride film, the buffer oxide film, and the sealing nitride film to form a contact hole exposing the conductive film; And forming a contact plug connected to the conductive layer through the contact hole by performing a planarization process to a target to which the upper portion of the conductive pattern is exposed.

According to the present invention, in the structure using a spacer nitride / buffer oxide / sealing nitride structure spacer after formation of a conductive pattern (eg, a gate electrode pattern), a planarization process is performed to form an interlayer insulating film on the spacer and expose the upper portion of the subsequent conductive pattern. Is carried out. At this time, an attack to the buffer oxide film occurs due to the difference in the polishing selectivity between the oxide film and the nitride film, which causes a gap in the upper portion of the buffer oxide film.

Subsequently, a filling nitride film is formed using an atomic layer deposition (ALD) method so as to fill the gap formed on the buffer oxide film.

Thereafter, contact holes are formed through a conventional SAC etching process, a plug material is deposited, and plug isolation through planarization is performed.

On the other hand, since the upper portion of the buffer oxide film is filled with the filling nitride film, all of the spacers form a nitride film series. Therefore, it is possible to suppress the occurrence of attack in a specific portion of the spacer due to the difference in the polishing selectivity.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4A to 4E are cross-sectional views illustrating a cell contact plug forming process according to an exemplary embodiment of the present invention, with reference to this, a cell contact plug forming process according to an exemplary embodiment of the present invention will be described.

First, as shown in FIG. 4A, a field insulating film 401 is locally formed on a semiconductor substrate 400 on which various elements for forming a semiconductor device are formed, thereby forming a field region consisting of the field insulating film 401 and an active region which is another region. (402) is defined.

Subsequently, a well (not shown) or the like is formed, and then the gate electrode patterns G1 to G4 having the gate hard mask 405 / gate conductive film 404 / gate insulating film 403 stacked on the substrate 400 are formed. To form.

The gate insulating film 403 uses a conventional oxide-based material film such as a silicon oxide film, and the gate conductive film 404 typically uses polysilicon, W, WN, WSi _x, or a combination thereof.

The gate hard mask 405 is to protect the gate conductive layer 404 in the process of forming the contact hole by etching the interlayer insulating layer during the etching process for the subsequent contact formation, and the etching rate is significantly different from that of the interlayer insulating layer. Use substance. For example, when an oxide-based layer is used as the interlayer insulating film, a nitride-based material such as silicon nitride film (SiN) or a silicon oxynitride film (SiON) is used, and when a polymer-based low dielectric film is used as the interlayer insulating film, an oxide-based material is used. do.

An impurity diffusion region (not shown) such as a source / drain junction is formed in the substrate 400 between the gate electrode patterns G1 to G4. The impurity diffusion region may be formed only by an ion implantation process performed in the cell region before the formation of the spacers after the formation of the gate electrode patterns G1 to G4, and after the formation of the gate electrode patterns G1 to G4 and after the formation of the spacers in the peripheral region. As a result, it may be formed through ion implantation so as to be aligned with the gate electrode patterns G1 to G4 and the spacer.

A spacer S having a nitride film / oxide film / nitride film structure of the sealing nitride film 406, the buffer oxide film 407, and the spacer nitride film 408 is formed along the profile in which the gate electrode patterns G1 to G4 are formed.

The sealing nitride film 406 and the spacer nitride film 408 include an insulating nitride film such as a silicon oxynitride film or a silicon nitride film.

Subsequently, an etch stop layer is formed on the entire surface where the spacer nitride layer 408 is formed in order to prevent attack of underlying structures such as the gate electrode patterns G1 to G4 in an etching process using a subsequent SAC method. In this case, the etch stop film is preferably formed along the profile of the spacer nitride film 408, and a material film based on a nitride film is used.                     

In addition, the etching stop film forming step is omitted here.

Here, the spacer nitride layer 408 is deposited by using a plasma enhanced chemical vapor deposition (PECVD) method so that the spacer nitride layer 408 is removed during SAC etching, and the sealing nitride layer 406 is formed in comparison with the spacer nitride layer 508. When the density is high, a low pressure chemical vapor deposition (LPCVD) method is used.

Here, the spacer nitride film 408 may include a multilayer nitride film structure.

Subsequently, as shown in FIG. 4B, an oxide-based interlayer insulating film 409 is formed on the entire structure where the spacer nitride film 408 is formed.

When the interlayer insulating film 409 is used as an oxide film, a BSG film, a BPSG film, a PSG film, a TEOS film, an HDP oxide film, an SOG film, or an APL film is used. In addition to the oxide film, an inorganic or organic low dielectric constant is used. Membrane can be used.

Subsequently, in order to reduce the etching target during the SAC etching process, the planarization process is performed to the target to which the gate hard mask 405 is exposed at the portion where the subsequent SAC etching process is to be performed.

In the planarization, CMP is used, or before the CMP process, an etch back process using plasma is performed first, followed by the CMP process 410.

At this time, an attack occurs in the buffer oxide film 407 due to the difference in the polishing selectivity between the buffer oxide film 407 and the sealing nitride film 406 / spacer nitride film 408, resulting in a gap as indicated by reference numeral 411. In the cleaning process performed after polishing, the gap 411 is further expanded.                     

Subsequently, as shown in FIG. 4C, the filling nitride film 412 is deposited in the ALD method, which is a deposition method having excellent coating property, to fill, ie, fill the gap 411.

Since the filling nitride film 412 uses an ALD method, the filling nitride film 412 has excellent filling characteristics for the gap 411. Since the filling nitride film 412 must simultaneously serve as a kind of sacrificial hard mask in a subsequent SAC etching process, the filling nitride film 412 may be deposited at a temperature of about 100 ° C. to 500 ° C. to have a film quality having etching resistance.

Meanwhile, a separate hard mask may be formed on the filling nitride film 412.

Subsequently, a photoresist such as an F ₂ exposure source or an ArF exposure source, for example, COMA or acrylate, which is a photoresist for an ArF exposure source, is applied to the filling nitride film 412 to a suitable thickness by a spin coating method, and the like. A predetermined portion of the photoresist is selectively exposed using a predetermined reticle (not shown) for defining the width of the contact plug, such as an F ₂ exposure source or an ArF exposure source, and is exposed by an exposure process through a developing process, or After the unexposed portion is left, the photoresist pattern 413 which is a cell contact open mask is formed by removing the etch residue and the like through a post-cleaning process or the like.

Here, the photoresist pattern 413 may be in the form of a hole type, bar type or tee type.

The photoresist pattern 413 is used for the purpose of preventing undesired patterns from being formed by diffused reflection due to high light reflectivity of the lower portion, that is, the peeling nitride film 412, during exposure for pattern formation, and to improve adhesion between the underlying structure and the photoresist. ) And a peeling nitride film 412 may be formed an anti-reflection film (not shown). In this case, the antireflection film mainly uses an organic-based material having similar etching characteristics to that of the photoresist, and may be omitted depending on a process.

As shown in FIG. 4D, the photoresist pattern 413 is etched using an etching mask, and then the filling nitride film 412, the interlayer insulating film 409, the spacer nitride film 408, the buffer oxide film 407, and the sealing nitride film 406 are sequentially etched. As a result, a contact hole 414 exposing the substrate 400, that is, the impurity diffusion region, between the adjacent gate electrode patterns G1 to G4 is formed.

At this time, the recipe of the conventional SAC etching process is applied, such as fluorine-based plasma, such as C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ or C ₅ F ₁₀ CxFy (x, y is 1 to 10) as a stock angle gas, and a gas for generating a polymer in the SAC process, that is, a gas such as CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ is added thereto. Inert gas such as He, Ne, Ar, or Xe is used as a carrier gas.

At this time, the spacer nitride film 408, the peeling nitride film 412, the buffer oxide film 407, and the sealing nitride film 406 are removed from the side of the gate electrode patterns G1 to G4 where the contact holes 414 are formed to remain in a spacer shape. .

In the SAC etching process, the combination of the above-described etching gas and temperature, pressure, power, etc. are changed according to each material.

Subsequently, the photoresist pattern 413 is removed to apply a conventional photoresist strip process.

Subsequently, wet cleaning is performed using a cleaning solution such as BOE to secure the CD on the bottom of the contact hole and to remove the etching by-products remaining after the process such as SAC and front etching. When washing, BOE or hydrofluoric acid is used. In the case of hydrofluoric acid, it is preferable to use dilute hydrochloric acid having a ratio of 50: 1 to 500: 1.

As shown in FIG. 4E, a plug forming conductive film is deposited on the entire surface of the substrate 400 on which the contact hole 414 is formed to sufficiently fill the contact hole 414.

Here, the most commonly used material for forming a conductive film for plug formation is polysilicon, and may be formed by laminating with barrier metal layers such as Ti and TiN, and metal such as tungsten may be used instead of polysilicon.

Subsequently, a CMP or an entire surface etching process may be performed to form a cell contact plug 415 electrically connected to the substrate 400 through the contact hole 414 and planarized and isolated from the gate hard mask 405.

Subsequently, a washing process is performed to remove by-products remaining after the planarization process.

At this time, since the upper part of the three layers constituting the spacer S is made of a nitride film series such as the filling nitride film 412, the spacer nitride film 408, the sealing nitride film 406, and the like, the difference in the polishing selectivity when polishing is almost generated. I never do that.

As a result, the generation of a gap due to the attack of the buffer oxide film 407 induced by the difference in the polishing selectivity is suppressed, and the attack does not occur along the gap even in the subsequent cleaning process.                     

Meanwhile, in the above-described embodiment, the cell contact plug forming process is taken as an example, but it may be applied to a bit line contact plug or a storage node contact plug forming process.

Therefore, in the storage node contact plug forming process, the lower impurity diffusion region may be replaced by a cell contact plug or a contact pad, and the gate electrode pattern may be replaced by a bit line.

In addition, the present invention described above may be applied to any contact forming process that exposes the lower conductive patterns, such as a contact process for forming metal wiring.

According to the present invention as described above, in the structure using the spacer nitride film / buffer oxide film / sealing nitride film spacer after the conductive pattern is formed, the planarization process is performed by forming an interlayer insulating film on the spacer and exposing the upper portion of the subsequent conductive pattern. As a result, an attack to the buffer oxide film occurs due to the difference in the polishing selectivity between the oxide film and the nitride film. As a result, the filling nitride film is formed by using the ALD method to fill the gap formed in the upper portion of the buffer oxide film. It was found through the examples that it is possible to suppress the occurrence of attack in a specific portion of the spacer due to.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above can reduce the occurrence of defects due to the attack of the spacer when the contact plug is formed, thereby improving the yield of the semiconductor device.

Claims (7)

Forming a plurality of neighboring conductive patterns having a hard mask on the substrate on which the conductive film is formed; Forming a spacer having a spacer nitride film / buffer oxide film / sealing nitride film structure along the profile in which the conductive pattern is formed; Forming an interlayer insulating film on the etch stop film; Performing a planarization process on a target to which the upper portion of the conductive pattern is exposed; a gap is generated due to excessive removal of the buffer oxide film due to a difference in polishing selectivity between the spacer nitride film, the buffer oxide film, and the sealing nitride film; Forming a filling nitride film by atomic layer deposition to sufficiently fill the gap; Selectively etching the peeling nitride film, the spacer nitride film, the buffer oxide film, and the sealing nitride film to form a contact hole exposing the conductive film; And Forming a contact plug connected to the conductive layer through the contact hole by performing a planarization process to a target to which the upper portion of the conductive pattern is exposed. Contact plug forming method of a semiconductor device comprising a. The method of claim 1, And a chemical mechanical polishing process in the step of performing the planarization process. The method of claim 2, And performing an etch back process by plasma prior to the chemical mechanical polishing process in the step of performing the planarization process. The method of claim 1, Forming the filling nitride film is a contact plug forming method of a semiconductor device, characterized in that carried out at a temperature of 100 ℃ to 500 ℃. The method of claim 1, In the forming of the contact hole, CxFy (x, y is 1 to 10) as a stock corner gas, and a gas for generating a polymer, ie, one of CH ₂ F ₂ , C ₃ HF _5, or CHF ₃ , is added thereto. When the inert gas of any one of He, Ne, Ar, or Xe as a carrier gas. The method of claim 1, Forming a photoresist pattern, using a photolithography process using an ArF or F ₂ exposure source. The method of claim 1, The plurality of conductive patterns may include at least one of a gate electrode pattern, a bit line, and a metal wiring.

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