KR20050070240A - Poly silicon thin film transistor and the fabrication method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a bottom gate type polycrystalline silicon thin film transistor having good crystallization characteristics and a manufacturing method thereof.

The present invention provides a method for forming an insulating film that can reduce the gate electrode step by forming a gate insulating film in double after the formation of the gate electrode in a bottom gate type thin film transistor, and does not remove the photoresist used in the photo process for forming the gate metal pattern. In this case, the first insulating film is deposited and the second insulating film is deposited while the photoresist is removed to form a double gate insulating film, thereby reducing the step difference caused by the gate electrode, thereby improving crystallization characteristics.

In addition, since the step by the gate electrode is reduced by the insulating film forming process according to the present invention, the outflow of defects is reduced, thereby reducing the cost and improving the manufacturing yield.

Description

Polysilicon thin film transistor and the fabrication method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a bottom gate type polycrystalline silicon thin film transistor having good crystallization characteristics and a manufacturing method thereof.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among them, a liquid crystal display having excellent color reproducibility, etc. displays are actively being developed.

In general, a liquid crystal display device is formed by arranging two substrates having electrodes formed on one surface thereof so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

Liquid crystal displays may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner has excellent resolution and video performance. It is most noticed.

The lower substrate of the liquid crystal display includes a thin film transistor that is a switching element. In general, amorphous silicon (a-Si: H) is mainly used as an active region for the thin film transistor. This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature.

On the other hand, recently, liquid crystal display devices employing thin film transistors using polycrystalline silicon (poly-Si) have been researched and developed. Since the polycrystalline silicon has a field effect mobility of about 100 to 200 times larger than that of the amorphous silicon, the response speed is fast and the stability of temperature and light is excellent. In addition, since the driving circuit can be formed on the same substrate, the manufacturing cost of the liquid crystal display device can be reduced.

Various methods of forming polycrystalline silicon having such advantages are known. Generally, amorphous silicon is formed by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition to form polycrystalline silicon. After depositing the crystallization method, it is widely used.

As a method of forming polycrystalline silicon using amorphous silicon, a laser annealing method of growing an amorphous silicon thin film by applying an excimer laser while heating the substrate temperature to about 250 ° C., and depositing a metal on the amorphous silicon to form a metal Metal induced crystallization (MIC) method for forming polycrystalline silicon with seeds, and solid phase crystallization (SPC) method for forming amorphous silicon by heat treatment for a long time at high temperature.

In addition, a method of forming a thin film transistor element includes a top gate type in which the gate of the thin film transistor element is positioned above the channel and the source / drain, and the gate of the TFT element is disposed below the channel and the source / drain. There is a bottom gate type formed to be located, and a double gate type formed to be positioned above and below.

Hereinafter, a bottom gate type thin film transistor using polycrystalline silicon will be described with reference to the accompanying drawings.

1 is a view schematically illustrating a part of a bottom gate type thin film transistor using a conventional polycrystalline silicon.

As shown in FIG. 1, a buffer layer 114 is formed over the entire surface of the insulating substrate 100, a gate electrode 120 is formed on the buffer layer 114, and the gate electrode 120 is formed on the insulating substrate 100. ) Is formed on the gate insulating film 118, and the amorphous silicon thin film 116 is formed on the gate insulating film 118.

The amorphous silicon thin film 116 is deposited on the entire surface of the substrate 100 to a thickness of about 300 kW to 1000 kW using plasma chemical vapor deposition (PECVD).

And, it undergoes a process of hydrogen evolution (hydrogen evolution) at 400 ℃ ~ 500 ℃.

The reason for this dehydrogenation process is to remove the hydrogen (H) added in the process of depositing the amorphous silicon thin film 116 by plasma chemical vapor deposition, and then the film ablation in the laser annealing process. This is to prevent the phenomenon.

Subsequently, the dehydrogenated amorphous silicon thin film 116 is crystallized by a laser heat treatment process.

At this time, in the bottom gate structure as described above, if the thickness of the gate metal 120 is thick, there is a problem that disconnection occurs in the gate step portion A in the process of crystallizing the laser after depositing amorphous silicon.

The reason is that the amorphous silicon is disconnected due to the agglomeration phenomenon due to the step curvature of the gate metal during melting and crystallization by the laser.

In addition, due to the step difference of the gate metal forming the gate electrode during the crystallization process, abnormal crystallization occurs in the gate step portion, thereby deteriorating the characteristics of the device.

In addition, there is a problem that it is difficult to set the process conditions during the high temperature process or the laser heat treatment for proceeding the crystallization process.

According to the present invention, a double gate insulating film is formed by depositing an insulating film in a bottom gate type thin film transistor using polycrystalline silicon without removing a photoresist used in a photo process for forming a gate metal pattern and depositing an insulating film with a photoresist removed. It is an object of the present invention to provide a polycrystalline silicon thin film transistor which improves crystallization characteristics by reducing the step difference caused by the gate electrode.

In order to achieve the above object, a polycrystalline silicon thin film transistor according to the present invention comprises: a gate electrode formed on a substrate; A first gate insulating film formed on a side of the gate electrode; A second gate insulating film formed on the first gate insulating film and a gate metal pattern; A polycrystalline semiconductor layer constituting an active layer, an LDD layer, a source region, and a drain region at a position corresponding to the gate electrode on the second gate insulating layer; And a source electrode and a drain electrode connected to the source region and the drain region on the polycrystalline semiconductor layer.

The first and second gate insulating layers may be formed of silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

The first gate insulating layer may be lower than a thickness of the gate metal pattern.

And an interlayer insulating film between the polycrystalline semiconductor layer and the source and drain electrodes.

In addition, a method of manufacturing a polycrystalline silicon thin film transistor according to the present invention for achieving the above object comprises the steps of forming a gate electrode on a substrate; Forming a first gate insulating film on the side of the gate electrode; Forming a second gate insulating film on the first gate insulating film and the gate metal pattern; Forming a polycrystalline semiconductor layer in an active region on said second gate insulating film; Doping an impurity on the polycrystalline semiconductor layer to form an active layer, an LDD layer, a source region, and a drain region; And forming a source electrode and a drain electrode electrically connected to the source region and the drain region.

Forming the first gate insulating film, forming a first gate insulating material on a photoresist pattern formed on the gate electrode; The method may further include exposing the gate electrode by removing the photoresist pattern.

After the forming of the polycrystalline semiconductor layer, further comprising forming an interlayer insulating film for forming a contact hole on the polycrystalline semiconductor layer.

The first and second gate insulating layers may be formed of silicon nitride (SiNx) and silicon oxide (SiO ₂ ).

Hereinafter, a bottom gate type polycrystalline silicon thin film transistor will be described with reference to the accompanying drawings.

2 is a plan view of a bottom gate type thin film transistor using polycrystalline silicon according to the present invention.

As shown in FIG. 2, a plurality of gate wirings 211 arranged in parallel on a transparent substrate and a plurality of parallel data wirings 212 orthogonal thereto are formed in a matrix to define pixel regions. The thin film transistor including the semiconductor layer 216, the gate electrode 220, the source electrode, and the drain electrodes 226 and 228 is disposed at the intersection point of the wiring, and the pixel electrode 234 electrically connected to the thin film transistor. .

In this case, the semiconductor layer 216 is electrically connected to the source and drain electrodes 226 and 228 by the first and second semiconductor layer contact holes 222a and 222b, and is drained by the drain contact hole 230. The electrode 228 and the pixel electrode 234 are electrically connected to each other.

Here, the semiconductor layer 216 is made of polycrystalline silicon (p-si) that is coated on the substrate with amorphous silicon (a-si) and then polycrystallized by laser annealing or the like.

3 is a cross-sectional view taken along line II ′ of FIG. 2 and schematically illustrates a portion of a pixel region of an array substrate having a bottom gate type thin film transistor according to the present invention.

As shown in FIG. 3, a buffer layer 214 is formed over the entire surface of the insulating substrate 200, a gate electrode 220 is formed over the buffer layer 214, and the gate electrode 220 is formed on the insulating substrate 200. A first gate insulating film 218 formed on side surfaces of the first gate insulating film 218, a second gate insulating film 219 covering the first gate insulating film 218 and the gate electrode 220, and the first and second gate insulating films 218 and 219. ), A semiconductor layer 216 is formed.

The first gate insulating layer 218 and the second gate insulating layer 219 are sequentially stacked and made of the same material.

The manufacturing process of the thin film transistor having the above structure will be briefly described as follows.

4A to 4J are process flowcharts illustrating a part of a process of manufacturing a bottom gate type thin film transistor according to the present invention.

First, as shown in FIG. 4A, a buffer layer 310 is formed on a transparent insulating substrate 300, and a metal such as chromium (Cr), aluminum (Al), and molybdenum (Mo) is formed on the buffer layer 310. The gate metal 320a is formed to have a thickness of about 200 nm.

As shown in FIG. 4B, a photoresist 330a is formed on the gate metal 320a.

The photoresist 330a is exposed and developed in a predetermined pattern to form a photoresist pattern 330b as shown in FIG. 4C.

Subsequently, as illustrated in FIG. 4D, the gate metal 320a is etched using the photoresist pattern 330b as a mask to form the gate electrode 320b.

As shown in FIG. 4E, the first gate insulating layer 341 is deposited on the gate electrode 320b to deposit the first gate insulating layer 341 on the photoresist pattern 330b.

The first gate insulating layer 341 is made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ), and is formed to be lower than the thickness of the gate electrode 320b.

Here, the first gate insulating layer 341 is to solve the step difference between the gate electrode 320b and the first gate insulating layer 341 is formed on the side of the gate electrode 320b.

Subsequently, as shown in FIG. 4F, the first gate insulating layer 341 formed on the photoresist pattern 330b by removing the photoresist pattern 330b formed on the gate electrode 320b. Lift-off.

4G, a second gate insulating film 342 is deposited on the entire surface of the first gate insulating film 341.

As described above, the second gate insulating film 342 deposited on the entire surface is formed on the first gate insulating film 341 and the gate electrode 320b as a whole, and the level of the step is reduced by the first gate insulating film 341 so that the relative level is relatively low. Is deposited flat.

Subsequently, the first and second gate insulating layers 341 and 342 are sequentially deposited, and then a semiconductor layer is formed.

Specifically, amorphous silicon (a-Si) 350a is deposited on the substrate 300 on which the first and second gate insulating layers 341 and 342 are formed, and then dehydrogenated. After that, polycrystalline silicon is formed through a laser crystallization step, and the semiconductor layer 350b is formed using the polycrystalline silicon as shown in FIG. 4H. Preferably, the amorphous silicon is deposited to about 550 mm thick.

In the laser crystallization step, a laser annealing method of growing an amorphous silicon thin film by applying an excimer laser while heating the substrate temperature to about 250 ° C., and solid phase crystallization formed by long-term heat treatment of amorphous silicon at a high temperature. SPC) and the like, and metal-induced crystallization (MIC), which deposits metal on amorphous silicon to form polycrystalline silicon as a seed.

In this case, since the curvature of the stepped portion of the edge due to the thickness of the gate electrode 320b is hardly formed, the semiconductor layer 350b may be formed by crystallization without disconnection.

Thereafter, as shown in FIG. 4I, a polycrystalline silicon thin film transistor is completed through a process of doping the semiconductor layer 350b with impurities.

Specifically, a photoresist pattern is formed on the substrate 300 on which the semiconductor layer 350b is formed, and low concentration ion implantation regions are formed on a surface of the polycrystalline semiconductor layer by using the photoresist pattern as a mask. do.

Next, a photoresist pattern is formed to cover the low concentration ion implantation region and a portion of the region, and a high concentration ion implantation is performed by using the photoresist pattern as a mask, so that an active region not doped with impurities and a source doped with a high concentration of impurities and An LDD region is formed between the drain region and the active region and the source and drain regions and is lightly doped with impurities.

After removing the photoresist pattern, the doped ions in the source and drain regions are activated using a laser.

As shown in FIG. 4I, an interlayer insulating film 324 including first and second semiconductor layer contact holes 322a and 322b is formed on the semiconductor layer 350b and formed thereon.

The source and drain electrodes 326 and 328 respectively connected to the first and second semiconductor layer contact holes 322a and 322b formed in the interlayer insulating layer 324 are spaced apart from each other by a predetermined distance.

4J, a passivation layer 332 including a drain contact hole 330 is formed on the source and drain electrodes 326 and 328, and the drain is formed on the passivation layer 332. The pixel electrode 334 is electrically connected to the drain electrode 328 through the contact hole 330.

Herein, the present invention has been described in detail with reference to the bottom gate type thin film transistor in which the gate electrode 320b is formed. have.

Although the present invention has been described in detail through specific examples, this is for explaining the present invention in detail, and the polycrystalline silicon thin film transistor according to the present invention and a method of manufacturing the same are not limited thereto, and it is within the technical spirit of the present invention. It is apparent that modifications and improvements are possible by those skilled in the art.

In the bottom gate type thin film transistor using polycrystalline silicon, the gate insulating film formed on the gate electrode is doubled to reduce the step difference caused by the gate electrode, thereby obtaining excellent crystallization characteristics during the crystallization process, thereby improving product quality. It works.

In addition, since the step difference caused by the gate electrode is reduced by the insulating film forming process according to the present invention, defect leakage is reduced, thereby reducing costs and improving manufacturing yield.

1 is a schematic view of a portion of a bottom gate type thin film transistor using a conventional polycrystalline silicon.

2 is a plan view of a bottom gate type thin film transistor using polycrystalline silicon according to the present invention;

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

4A to 4J are process flowcharts showing a part of a process of manufacturing a bottom gate type thin film transistor according to the present invention.

<Description of Signs of Major Parts of Drawings>

200, 300: substrate 211: gate wiring

212: data wirings 214, 310: buffer layer

216 and 350b semiconductor layer 218 and 341 first gate insulating film

219 and 342: second gate insulating film 220 and 320 b: gate electrode

224 and 324 interlayer insulating films 222a and 222b first and second semiconductor layer contact holes

226, 326: source electrode 228, 328: drain electrode

230: drain contact holes 232, 323: protective layer

234, 334: pixel electrode 320a: gate metal

330a: photoresist 330b: photoresist pattern

350a: amorphous silicon

Claims (8)

A gate electrode formed on the substrate; A first gate insulating film formed on a side of the gate electrode; A second gate insulating film formed on the first gate insulating film and a gate metal pattern; A polycrystalline semiconductor layer constituting an active layer, an LDD layer, a source region, and a drain region at a position corresponding to the gate electrode on the second gate insulating layer; And a source electrode and a drain electrode connected to a source region and a drain region on the polycrystalline semiconductor layer. The method of claim 1, The first and second gate insulating layers may include a silicon nitride film (SiNx) and a silicon oxide film (SiO ₂ ). The method of claim 1, And the first gate insulating layer is lower than a thickness of the gate metal pattern. The method of claim 1, And an interlayer insulating film between the polycrystalline semiconductor layer and the source and drain electrodes. Forming a gate electrode on the substrate; Forming a first gate insulating film on the side of the gate electrode; Forming a second gate insulating film on the first gate insulating film and the gate metal pattern; Forming a polycrystalline semiconductor layer in an active region on said second gate insulating film; Doping an impurity on the polycrystalline semiconductor layer to form an active layer, an LDD layer, a source region, and a drain region; And forming a source electrode and a drain electrode electrically connected to the source region, the drain region, and the method of manufacturing a polycrystalline silicon thin film transistor. The method of claim 5, In the step of forming the first gate insulating film, Forming a first gate insulating material on the photoresist pattern formed on the gate electrode; And removing the photoresist pattern to expose a gate electrode. The method of claim 5, After forming the polycrystalline semiconductor layer, And forming an interlayer insulating film forming a contact hole on the polycrystalline semiconductor layer. The method of claim 5, The first and second gate insulating films may be formed of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ).