KR20060133711A - Method of manufacturing thin film transistor substrate for liquid crystal display device - Google Patents

Abstract

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, comprising forming an active layer on a substrate, forming a gate electrode on the active layer, performing ion implantation for a source / drain, and then forming an interlayer insulating film thereon. In addition, a contact hole is formed through the interlayer insulating layer to expose a portion of the lower active layer and the gate electrode line. Then, the implanted impurity ions are activated through a heat treatment process using a furnace, and the contact hole is buried to fill the source electrode and the drain electrode. And a passivation film is deposited at a high temperature after the formation of the gate pad, thereby reducing the contact resistance of the thin film transistor substrate for a liquid crystal display device.

Description

Method for manufacturing thin film transistor substrate for liquid crystal display device {METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY}

1A is a plan view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

1B is a cross-sectional view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

2 to 10 are cross-sectional views taken along line A-A, line B-B, and line C-C to illustrate the method of manufacturing the thin film transistor substrate according to the present embodiment.

11 is a graph showing the results of measuring contact resistance of a thin film transistor according to the present invention;

<Explanation of symbols for the main parts of the drawings>

100 substrate 110 active layer

120: gate electrode 140: sustain electrode line

150: gate line 170: data line

180 source electrode 190 drain electrode

200: passivation film 220: pixel electrode

230: gate pad 240: data pad

250: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, and to a method for shortening the manufacturing process of a thin film transistor substrate.

In general, a liquid crystal display (LCD) includes a thin film transistor substrate including a pixel electrode, a storage capacitor, and a thin film transistor (TFT) for switching each pixel, and a common electrode substrate including a common electrode, etc. And liquid crystal sealed between the two substrates. Here, the liquid crystal display displays an image by applying a voltage between two substrates to drive the liquid crystal and controlling the transmittance of light.

The thin film transistor of the liquid crystal display device is formed using amorphous silicon or polycrystalline silicon as a semiconductor layer. A thin film transistor made of amorphous silicon has an advantage of having stable characteristics due to excellent uniformity of the amorphous silicon film. However, the amorphous silicon thin film transistor has a disadvantage in that the response speed of the device is slow because of low charge mobility. Accordingly, the amorphous silicon thin film transistor has a disadvantage in that it is difficult to be applied to a driving device of a high resolution display panel, a gate, or a data driver that requires fast response speed.

Meanwhile, the thin film transistor made of polycrystalline silicon is suitable for a high resolution display panel requiring high response speed because of high charge mobility, and has an advantage of embedding peripheral driving circuits in the display panel. Accordingly, liquid crystal displays using polycrystalline silicon thin film transistors have emerged.

The polycrystalline silicon thin film transistor is manufactured by a top gate method in which a gate electrode is formed on an active layer. That is, a gate electrode was formed on the active layer, impurity ions were implanted into both sides of the gate electrode, and an excimer laser was irradiated onto the active layer into which the impurity ions were implanted to activate impurities. However, the laser process is a major cause of cost increase because of the difficult and complicated maintenance and expensive equipment as well as the equipment. In addition, there is a problem that the characteristics of the ion-implanted active layer becomes nonuniform due to energy variation during laser irradiation.

In addition, the gate electrode of the thin film transistor is connected to an external power source through a separate metal pad. However, there is a problem in that the contact resistance of the region where the gate and the metal pad contact each other is very large. That is, when the gate is manufactured using Al, the contact resistance between the gate and the metal pad is very high in the order of 1E5 or more due to the Al oxide film formed on the gate in the air, which causes a driving failure of the device. Therefore, conventionally, to solve this problem, a metal pad was formed, and then a heat treatment process for additional metal activation was performed to reduce the resistance between the gate and the metal pad. However, as a separate heat treatment process is added as described above, the manufacturing process of the device becomes complicated, resulting in a problem in that the production cost and the productivity decrease.

Accordingly, the present invention was derived to solve the above problems, and after the formation of the gate, source and drain contact holes, it is possible to activate the impurity ions implanted in the active layer by performing a heat treatment process using a furnace, at a high temperature It is an object of the present invention to provide a method for manufacturing a thin film transistor substrate for a liquid crystal display device capable of forming a passivation film to reduce the contact resistance between the gate and the pad.

Forming an active layer on the substrate according to the present invention, forming a gate insulating film covering the active layer and forming a gate pattern including a gate electrode and a gate line thereon, and forming an interlayer insulating film on the gate pattern. Forming a source contact hole and a drain contact hole through the interlayer insulating layer to expose the active layer, a lower gate contact hole exposing a portion of the gate line, and performing a heat treatment process using an furnace. A source electrode connected to the active layer through the source contact hole, a drain electrode connected to the active layer through the drain contact hole, a lower gate pad connected to the gate line through the lower gate contact hole, and the gate line Forming a data line formed to intersect with and defining a pixel area And forming a passivation film at a temperature at which the metal atoms of the lower gate pad can be diffused.

After the forming of the gate pattern, the method may further include implanting impurity ions to form a channel region, a source region, and a drain region of the active layer.

The heat treatment process using the furnace is preferably carried out for about 30 to 120 minutes at a temperature within the range of 350 to 550 degrees under an N ₂ gas atmosphere.

Forming the active layer on the substrate preferably includes patterning amorphous silicon on the substrate and crystallizing the patterned amorphous silicon using a laser.

The temperature at which the above-described metal atoms can be diffused is preferably 300 to 500 degrees Celsius or more.

After forming the passivation layer, a passivation layer is formed on the passivation layer, the pixel contact hole exposing the drain electrode through the passivation layer, the upper gate pad contact hole exposing the lower gate pad, and the data line. Forming a data contact hole exposing a portion of the pixel electrode; a pixel electrode formed in the pixel area and connected to the drain electrode through the pixel contact hole, and an upper part connected to the lower gate pad through the upper gate pad contact hole The method may further include forming a data pad connected to the data line through a gate pad and the data contact hole.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as being on or above another part, not only when each part is directly above or directly above the other part but also another part between each part and another part This includes cases.

1A is a plan view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 1B is a cross-sectional view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 1A is a cross-sectional view taken along lines AA, BB, and CC to illustrate a method of manufacturing a thin film transistor substrate according to an example.

1A to 10, the thin film transistor substrate for a liquid crystal display according to the present embodiment transmits a gate signal on the transparent insulating substrate 100 and extends in a first direction and has a predetermined interval in a second direction. A plurality of gate lines 150 arranged, a plurality of data lines 170 formed to intersect the gate lines 150, and pixel electrodes formed in a pixel region defined by the gate lines 150 and the data lines 170. A plurality of thin film transistors 250 formed in a matrix form at the intersections of the 220, the gate line 150, and the data line 170, and the storage capacitor formed in an overlapping portion of the pixel electrode 220 and the storage line 140. 142.

Here, it is preferable that the pixel region formed surrounded by two adjacent gate lines 150 and the data lines 170 has a rectangular shape on a layout.

In addition, the thin film transistor 250 may include a gate electrode 120 connected to the gate line 150, a source electrode 180 connected to the data line 170, and a drain electrode 190 connected to the pixel electrode 220. Include. The gate electrode 120 overlaps the channel region of the active layer 110 with the gate insulating layer 122 interposed therebetween. The source electrode 180 is insulated from the gate electrode 120 through the interlayer insulating layer 160, and is connected to the source region 111 and the source contact hole 181 of the active layer 110 into which ions are implanted. The drain electrode 190 is insulated from the gate electrode 120 through the interlayer insulating layer 160, and is connected to the drain region 112 and the drain contact hole 191 of the active layer 110 into which ions are implanted.

In this case, the ions implanted into the active layer 110 vary according to the characteristics of the thin film transistor 250. For example, when the thin film transistor 250 has N channels, a high concentration of n + ions are implanted into the active layer 110, and when a thin film transistor 250 has a P channel, high concentrations of p + ions are implanted into the active layer 110. As such, the implanted ions may be selectively controlled according to the characteristics of the transistor. At this time, the active layer 110 implanted with ions becomes the source region 111 and the drain region 112, and the region where the impurity ions are not implanted becomes the channel region 115. Furthermore, in the present embodiment, the channel region 115 and the source and the source and the channel and the source and drain regions 111 and 112 are prevented in order to prevent a phenomenon such as punch current. And a lightly doped drain 113 and 114 into which low concentrations of n- or p- ions are implanted between the drain regions 111 and 112.

The thin film transistor 250 operates according to a predetermined signal of the gate line 150 to apply a video signal, that is, a pixel signal, of the data line 170 to the liquid crystal cell.

The gate line 150 mainly extends in the horizontal direction, and a portion of the gate line 150 protrudes upward and / or downward to form the gate electrode 120 of the thin film transistor 250 described above. A gate pad 24 for connecting to an external circuit is formed at the end of the gate line 150.

The data line 170 mainly extends in the vertical direction, and a part of the data line 170 protrudes to form the source electrode 180 of the thin film transistor 250 described above. The data pad 230 is formed at the end of the data line 170.

The pixel electrode 220 is connected to the drain electrode 190 of the thin film transistor 250 through the pixel contact hole 221 penetrating the passivation layers 200 and 210. Meanwhile, an electric field is formed between the pixel electrode 220 formed in the pixel region and the common electrode (not shown) according to the pixel signal applied through the thin film transistor 150, and the liquid crystal molecules rotate by the dielectric anisotropy by the electric field. do. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules so that the target image can be realized.

The storage capacitor 142 includes a storage line 140, and a pixel electrode 220 overlapping the storage line 140 with the interlayer insulating layer 160 and the passivation layers 200 and 210 interposed therebetween. The sustain capacitor 142 allows the pixel signal charged in the pixel electrode 220 to be stably maintained until the next pixel signal is charged.

Hereinafter, a method of manufacturing a thin film transistor substrate for a liquid crystal display device according to an exemplary embodiment of the present invention described above will be described with reference to the drawings.

Referring to FIG. 2, a buffer layer 102 is formed on the light-transmissive insulating substrate 100, and an active layer 110 is formed on the buffer layer 102.

Here, the insulating substrate 100 may be made of glass, quartz, sapphire, or the like, or may be a transparent plastic plate.

On the insulating substrate 100, the buffer film 102 is formed by using an inorganic insulating material containing SiO ₂ or SiN _x through CVD, PVD, or sputtering, and using amorphous silicon. It is preferable to form an active film on 102. Thereafter, a photoresist film is coated on the active layer, and a photoresist pattern is formed through a photolithography process using a mask. The photoresist pattern is formed in a shape that exposes a region other than the region where the active layer 110 is to be formed. It is preferable to form the active layer 110 by performing an etching process using the photoresist pattern as an etching mask to remove the active layer in the exposed region.

Thereafter, the amorphous silicon film of the active layer 110 is crystallized through a crystallization process using a laser to form a polycrystalline silicon film. That is, the excimer laser is irradiated onto the active layer 110 to crystallize through crystal growth and crystal growth. After the active layer 110 of polycrystalline silicon is formed, the photoresist pattern is removed through a predetermined strip process.

In addition, a predetermined barrier layer (not shown) may be further formed on the active layer 110 to serve as an etch barrier layer during the formation of the source and drain contact holes.

Referring to FIG. 3, a gate insulating film 122, a gate conductive film 124, and an ion barrier film 126 are formed over the entire structure.

In the above, it is preferable to use an insulating material such as SiO ₂ as the gate insulating film 122. As the gate conductive film 124, Al alloys such as Mo, Cu, Al, Ti, Cr, Mo alloys, AlNd, Cu alloys are formed in a single layer structure, or Ar / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu Alloy / Mo, Cu The alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy, Mo alloy / Al alloy and the like can be formed of a multi-layer or more multi-layer structure. The ion barrier film 126 is preferably formed using chromium.

4 and 5, the ion barrier layer 126 and the gate conductive layer 124 are patterned to form a gate pattern including the gate electrode 120 and the gate line 150, the sustain line 140, and the lower portion. The pad electrode 151 is formed and ion implantation is performed to form the channel region 115, the low concentration ion implantation regions 113 and 114, the source region 112, and the drain 112 region in the active layer 110.

In the above patterning process, a photoresist film is coated on the ion barrier film 126 as shown in FIG. 4, and a photoresist pattern is formed through a photolithography process using a mask. An ion barrier layer 126 is patterned by performing an etching process using the photoresist pattern as an etching mask. In this case, it is effective to form the ion barrier layer 126 in a pattern longer than the gate electrode 120 by a predetermined length to form a low concentration ion implantation region. Thereafter, an etching process using the patterned ion barrier layer 126 as an etching mask is performed to etch the gate conductive layer 124 to form the gate electrode 120, the gate line 120, the storage line 140, and the lower pad electrode. 151 is formed. In this case, the gate conductive layer 124 may be excessively etched to form a width of the gate electrode 120 positioned below the ion barrier layer 126 to be smaller than that of the ion barrier layer 126.

Next, as illustrated in FIG. 4, a high concentration ion implantation process using the ion barrier layer 126 as an ion implantation mask is performed to form the source region 111 and the drain region in the active layer 110 on both sides of the gate electrode 120. 112 and channel region 115 are formed. As shown in FIG. 5, the ion barrier layer 126 is removed and then a low concentration ion implantation process is performed to form a lower region of the sidewall of the gate electrode 120, that is, between the source region 111 and the channel region 115 and the drain region 112. ) And the low concentration ion implantation regions 113 and 114, respectively, between the channel region 115 and the channel region 115. The impurity implanted above may use N-type impurity ions or P-type impurity ions according to carrier characteristics in the device. In addition, when forming N type and P type simultaneously, it is effective to use different ion implantation masks.

Referring to FIG. 6, the interlayer insulating layer 160 is formed on the entire surface of the substrate 100 on which the gate electrode 120, the storage line 140, the lower pad electrode 151, the source region 111, and the drain region 112 are formed. And remove a portion of the interlayer insulating layer 160 on the source region 111, the drain region 112, and the lower pad electrode 151 to form the contact holes 152, 181, and 191, and then perform a heat treatment process. Conduct.

It is preferable to use an inorganic insulating material including SiO ₂ or SiN _x as the interlayer insulating layer 160. The interlayer insulating film 160 may be formed as a single layer or may be formed as a multilayer film. After the interlayer insulating film 160 is formed on the entire structure, a photosensitive film is coated on the interlayer insulating film 160. A photolithography process using a mask is performed to form a photoresist pattern that opens the source region 111, the drain region 112, and the lower pad electrode 151 region. A source contact hole 181 that opens a portion of the source region 111 by performing an etching process using the photoresist pattern as an etching mask, a drain contact hole 191 that opens a portion of the drain region 112, and a lower portion A lower pad electrode contact hole 152 that opens a portion of the pad electrode 151 is formed.

After that, the heat treatment process using the furnace is performed. At this time, the heat treatment process is preferably carried out for about 30 to 120 minutes at a temperature within the range of 350 to 550 degrees Celsius. More preferably, the heat treatment is performed for about 50 to 100 minutes at a temperature of 400 to 500 degrees.

In the present embodiment, a heat treatment process using a furnace is performed by loading a substrate 100 having the source contact hole 181, the drain contact hole 191, and the lower pad electrode contact hole 152 inside the furnace. The heat treatment process may be performed by raising an internal temperature within the above range, and the source contact hole 181, the drain contact hole 191, and the lower pad electrode contact hole 152 inside the furnace raised to the temperature. The heat treatment process may be performed by loading the formed substrate 100.

As described above, the impurity ions implanted into the source region 111, the drain region 112, and the low concentration ion implantation regions 113 and 114 of the active layer 110 are activated. In addition, the thickness of the natural oxide layer formed on the lower pad electrode 151 opened by the lower pad electrode contact hole 152 may be reduced through the heat treatment process. To this end, the heat treatment process using the furnace may be performed in an N ₂ atmosphere to reduce the thickness of the oxide film by changing the oxide film formed on the lower pad electrode to a nitride film.

Referring to FIG. 7, a conductive film is formed on the interlayer insulating film 160 on which the contact holes 152, 181, and 191 are formed to fill the contact holes 152, 181, and 191, and pattern the conductive film on the interlayer insulating film 160. The data line 170, the source electrode 180, the drain electrode 190, the lower gate pad 153, and the lower data pad 172 are formed.

A predetermined conductive film is formed on the interlayer insulating film 160, and the inside of the contact holes 152, 181, and 191 formed in the interlayer insulating film 160 are filled with the conductive film. After the photosensitive film is coated on the conductive film, a photolithography process using a mask is performed to form a photosensitive film pattern. In this case, regions except for the data line 170, the source electrode 180, the drain electrode 190, the lower gate pad 153, and the lower data pad 172 are opened through the photoresist pattern. Thereafter, an etching process using the photoresist pattern as an etch mask is performed to form a straight data line 170 orthogonal to the gate line 120, and extends from one end of the data line 170 to close the source contact hole 181. A source electrode 180 connected to the source region 111 is formed through the drain electrode hole 191, a drain electrode 190 connected to the drain region 112 is formed through the drain contact hole 191, and a lower pad electrode contact hole 152 is formed. The lower gate pad 153 connected to the lower pad electrode 151 is formed through the lower pad electrode, and the lower data pad 172 is formed at the end of the data line 170.

Here, the conductive film may be formed of a single layer structure of Al alloys such as Mo, Cu, Al, Ti, Cr, Mo alloys, AlNd, Cu alloys, Ar / Cr, Al / Mo, Al (Nd) / Al, Al (Nd) / Cr, Mo / Al (Nd) / Mo, Cu / Mo, Ti / Al (Nd) / Ti, Mo / Al, Mo / Ti / Al (Nd), Cu Alloy / Mo, Cu Alloy / Al, Cu alloy / Mo alloy, Cu alloy / Al alloy, Al / Mo alloy, Mo alloy / Al, Al alloy / Mo alloy, Mo alloy / Al alloy and the like can be formed in a multi-layered multi-layer structure.

Referring to FIG. 8, a high temperature passivation layer 200 is formed on the interlayer insulating layer 160 on which the electrodes 180 and 190 and the pads 153 and 172 are formed.

The passivation layer 200 is formed on the entire upper surface of the interlayer insulating layer 160 on which the data line 170, the source electrode 180, the drain electrode 190, the lower gate pad 153, and the lower data pad 172 are formed. It is preferable to form at a temperature of 300 to 500 degrees Celsius or more. Of course, it is more preferable to deposit the passivation film 200 at a temperature of 350 to 400 degrees. As a result, contact resistance between the lower pad electrode 151 and the lower pad 153 may be reduced. For example, when Al is used as the gate line 120, the lower pad electrode 151 formed at the end of the gate line 120 is opened by the lower pad electrode contact hole 152, and the aluminum natural oxide film is formed on the upper surface thereof. Is formed. Subsequently, when the lower gate pad 153 connected to the lower pad electrode 151 through the lower pad electrode contact hole 152 is formed using Al, the lower pad electrode 151 and the lower gate pad 153 may be formed. The natural oxide film remains and the contact resistance between the two metals becomes very large. In the present embodiment, at least a portion of the natural aluminum oxide film is changed to a nitride film during the heat treatment process using the above-described furnace, and the passivation film 200 is formed on the lower pad electrode 151 above the temperature at which Al can diffuse. Al is diffused into the native oxide film to reduce the contact resistance between the two metals.

Referring to FIG. 9, a passivation layer 210 is formed on an entire top surface of the passivation layer 200, and a portion of the passivation layer 200 and the passivation layer 210 is removed to form a pixel contact hole 221 and a gate pad contact hole ( 231 and a data pad contact hole 241 are formed.

A passivation layer 200 is formed on the passivation layer 200 by depositing an inorganic insulating material or an organic insulating material on the entire surface to form a protective film 210. That is, the passivation layer 210 serves to protect the thin film transistor 250 formed below. After the photoresist is coated on the passivation layer 210, a photolithography process using a mask is performed to form a photoresist pattern exposing the pixel contact hole region, the gate pad contact hole region, and the drain pad contact hole region. An etching process using the photoresist pattern as an etching mask is performed to sequentially etch the passivation layer 210 and the passivation layer 200 of the exposed region to sequentially etch the pixel contact hole 221, the gate pad contact hole 231, and the data pad contact. The hole 241 is formed. The photoresist pattern is removed through a predetermined strip process.

Referring to FIG. 10, a conductive film is deposited and patterned on the passivation layer 210 on which the contact holes 221, 231, and 241 are formed, thereby forming the pixel electrode 220, the upper gate pad 230, and the upper drain pad 240. Form.

A transparent conductive film containing indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire structure. After the photosensitive film is coated on the transparent conductive film, a photolithography process using a mask is performed to form a photosensitive film pattern exposing regions except for the pixel electrode region, the upper gate pad region, and the upper drain pad region. An etching process using the photoresist pattern as an etching mask is performed to form a pixel electrode 220 connected to the drain electrode 190 and the pixel contact hole 221 in the pixel region, and to form a lower gate pad ( An upper gate pad 230 connected to the 153 and the gate pad contact hole 231 is formed, and a lower data pad 172 and an upper drain pad 240 are formed in the data pad region.

In the above-described embodiment, a contact hole is formed to activate impurity ions implanted into the source region 111, the drain region 112, and the low concentration ion implantation regions 113 and 114, and then a heat treatment process using a furnace is performed. In addition, after the heat treatment process, the lower gate pad is formed on the lower pad electrode and the passivation film is deposited at a high temperature to reduce the manufacturing cost of the device, and to simplify the process, and to contact the lower pad electrode and the lower gate pad. Could reduce the resistance.

The contact resistance reduction will be described with reference to the experimental results as follows.

11 is a graph illustrating a result of measuring contact resistance of a thin film transistor according to the present invention.

In FIG. 11, a graph shows a result of measuring resistance between the lower pad electrode and the lower gate pad after forming the lower pad electrode, and a graph b shows a result of measuring resistance between the lower pad electrode and the lower gate pad after the passivation film is deposited at a high temperature. to be. In addition, condition 1 of FIG. 11 is an experimental result of performing a heat treatment process using a furnace at about 450 degrees for contact activation after the formation of a contact, and condition 2 is a test result of performing a heat treatment process using a furnace at a temperature of about 400 degrees to be.

It can be seen that the contact resistance is reduced by forming a contact as in the above-described experimental conditions, performing a heat treatment process, filling the contact, and depositing a passivation film at a high temperature. In addition, it can be seen that the change of the contact resistance value increases with the temperature of the heat treatment process.

As described above, after the lower pad electrode contact hole is formed, impurity ions implanted into the active layer may be activated through a heat treatment process using a furnace.

In addition, after the contact hole is formed, a heat treatment process using a furnace is performed, and the contact hole is filled with a metal, and then a passivation film is formed at a high temperature to reduce the contact resistance between the two metals connected through the contact hole, and simplify the process. It is possible to reduce the manufacturing cost of the device.

Although described with reference to the embodiments, it will be understood by those skilled in the art that the present invention may be modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. .

Claims (6)

Forming an active layer on the substrate; Forming a gate insulating layer covering the active layer and forming a gate pattern including a gate electrode and a gate line thereon; Forming an interlayer insulating layer on the gate pattern, forming a source contact hole and a drain contact hole penetrating the interlayer insulating layer to expose the active layer, and a lower gate contact hole exposing a portion of the gate line; Performing a heat treatment process using a furnace; A source electrode connected to the active layer through the source contact hole, a drain electrode connected to the active layer through the drain contact hole, a lower gate pad connected to the gate line through the lower gate contact hole, and an intersection with the gate line Forming a data line so as to define a pixel area; And And forming a passivation film at a temperature at which the metal atoms of the lower gate pad can be diffused. The method of claim 1, after the forming of the gate pattern, And implanting impurity ions to form a channel region, a source region and a drain region of the active layer. The method according to claim 1, The heat treatment process using the furnace is a thin film transistor substrate manufacturing method for a liquid crystal display device performed for about 30 to 120 minutes at a temperature within the range of 350 to 550 degrees in an N ₂ gas atmosphere. The method of claim 1, wherein the forming of the active layer on the substrate, Patterning amorphous silicon on the substrate; And A method for manufacturing a thin film transistor substrate for a liquid crystal display device comprising crystallizing patterned amorphous silicon using a laser. The method according to claim 1, The metal atom can be diffused to a temperature of 300 to 500 degrees Celsius or more thin film transistor substrate manufacturing method for a liquid crystal display device. The method of claim 1, wherein after forming the passivation film, A passivation layer may be formed on the passivation layer, the pixel contact hole exposing the drain electrode through the passivation layer, the upper gate pad contact hole exposing the lower gate pad, and the data contact hole exposing a portion of the data line. Forming; And A pixel electrode formed in the pixel region and connected to the drain electrode through the pixel contact hole, an upper gate pad connected to the lower gate pad through the upper gate pad contact hole, and the data line through the data contact hole; A method of manufacturing a thin film transistor substrate for a liquid crystal display device, further comprising the step of forming a data pad to be connected.

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