KR20040099616A - Layout method for semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout method of a semiconductor device. In an element having a minimum line width of 1F, an active region has a layout in which two word lines are repeatedly arranged on one straight word line as in the conventional art. Since the area with the adjacent cell is minimized, fine process margin is increased, it is advantageous for high integration of the device, and occurrence of short circuit is suppressed, thereby improving process yield and device reliability.

Description

Layout method for semiconductor devices

The present invention relates to a layout method of a semiconductor device. In particular, in a micro device having a low process margin between patterns, two adjacent word lines and one straight word line are repeatedly arranged to apply the design rules of the 8F 2 device as it is. The present invention relates to a layout method of a semiconductor device capable of increasing the fine process margin by reducing the area and improving process yield and device reliability.

The recent trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential requirements in the manufacturing process of semiconductor devices.

The resolution (R) of the photoresist pattern is closely related to the material of the photoresist itself or the adhesion to the substrate. It is inversely proportional to the lens aperture (NA, numerical aperture) of the device.

[R = k * λ / NA, R = resolution, λ = ~ wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of a line / space pattern. The limit is about 0.7 and 0.5 μm, respectively, and in order to form a fine pattern of 0.5 μm or less, deeper ultra violet (DUV) wavelengths, for example, KrF laser having a wavelength of 248 nm or 193 nm An exposure apparatus using an ArF laser as a light source should be used.

In addition to the reduction exposure apparatus, the process method includes a method of using a phase shift mask as a photo mask, or forming a separate thin film on the wafer to improve image contrast. A contrast enhancement layer (CEL) method or a tri layer resister (hereinafter referred to as a TLR) method in which an intermediate layer such as spin on glass (SOG) is interposed between two photoresist layers. In addition, a silicide method for selectively injecting silicon into the upper side of the photoresist film has been developed to lower the resolution limit.

In addition to these process efforts, a method of changing cell layout design to reduce cell area and achieving high integration has been performed.

1 is a layout view of a semiconductor device according to a first embodiment of the prior art, which is an example of an 8F ² cell array method.

First, rectangular active regions 12 are arranged in a matrix on a semiconductor substrate 10 such as a silicon wafer, and word lines 14 are arranged at equal intervals so as to cross two of the active regions 12 one by one. Are formed to extend in a vertical line in a vertical direction, and bit lines 16 extending in the horizontal direction are formed in a space between the active regions 12, and the bit lines 16 are formed in the active region 12. Is connected to the central portion of the interconnection via a local interconnect 18, and two charge storage electrode contact holes 19 are formed at both sides of each active region 12, and are not shown in the central portion. The bit lines are connected through bit line contact holes.

In the above device, if the called F the minimum line width, the spacing of the active region 12, the word line direction are 3F, a bit line direction, it is staggered at intervals of 1F area of the unit cell is 8F ² Has

The cell array structure, but noise suppression characteristics but are superior advantages, a 6F ² elements there is a limit in reducing the cell area to take in more tight the arrangement of the cells used, and this 6F ² element is less process margin, a contact forming There are additional processes for the process, and the process is complicated, and there is another problem of low process yield and device reliability due to high risk of short circuit between wires.

The present invention is to solve the above problems, an object of the present invention is to reduce the area of the unit cell while maintaining the 8F ² device design rule or arrangement is advantageous for high integration of the device without the addition of a process, the process The present invention provides a layout method of a semiconductor device that can easily secure a margin and improve process yield and device reliability.

1 is a layout diagram of a semiconductor device according to the prior art.

2 is a layout diagram of a semiconductor device according to the present invention;

<Description of Symbols for Main Parts of Drawings>

10, 20: semiconductor substrate 12, 22: active area

14: word line 16: bit line

18: local interconnection 19: charge storage electrode contact hole

23,25: Inclined word line 24: Straight word line

26: charge storage electrode contact plug 28: bit line contact plug

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Rectangular active regions arranged in a matrix form,

A method of laying out a semiconductor device, comprising: word lines traversing the active region, the word lines being arranged to traverse two in one active region;

The word line is provided with two slanted word lines, one to the left and one to the straight word line.

In addition, another feature of the present invention,

Rectangular active regions arranged in a matrix form,

A method of laying out a semiconductor device, comprising: word lines traversing the active region, the word lines being arranged to traverse two in one active region;

The active region is a rectangular shape of the size of 6F-1F and maintains the vertical and horizontal spacing of 1F, the degree of staggering between the vertical arrangement, the lower active region is moved to the right by 2F than the upper active region,

It is arranged in a vertical direction across the active area, and disposed so as to cross two in one active area, one straight word line overlaps the width of 1F with a space of 1.5F and 2.5F distance from both ends of the active area. Two oblique word lines extending in a vertical direction to the left and right of the straight wood line, and the oblique word line passes through a portion overlapping with the active area at the same distance as the straight word line, It is sequentially inclined by 0.5F from side to side, characterized by crossing the upper and lower active areas.

Hereinafter, a layout method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout diagram of a semiconductor device according to the present invention.

First, rectangular active regions 22 are arranged in a matrix on a semiconductor substrate 20 such as a silicon wafer, and are formed with a length and width of 6F-1F while maintaining a vertical and horizontal spacing of 1F. The degree of stagnation is such that the lower active region 22 is shifted by 2F to the right compared to the upper active region 22.

In addition, word lines 23, 24, and 25 are arranged in a vertical direction crossing the active area 22, and are arranged to cross two by one in the active area 22, but one straight word line 24 is disposed. It extends so as to overlap a width of 1F with a space between 1.5F and 2.5F from both ends of the active region 22, and two oblique word lines 23 and 25 extend in the vertical direction adjacent to each other.

Here, the portions of the inclined word lines 23 and 25 overlap the active region 22 and pass through the same portions as the straight word lines 24, but are sequentially inclined by 0.5F in the non-overlapping portions. The upper and lower active regions 22 are alternately connected to the contacts sequentially.

In addition, charge storage electrode contact plugs 26 are formed at a size of 1 × 2F at both ends of the active region 22, and bit line contact plugs 28 are 1 × 1F at a central portion of the active region 22. Is formed.

The device formed as described above has an area occupied by two cells of 1F × 7F, so that one cell has a size of 7F ² . That is, compared to the existing 8F ² cell, the size of the active region is the same, but the cell area can be reduced by minimizing the common area with neighboring cells.

As described above, in the semiconductor device layout method according to the present invention, the size of the active region in a device having a minimum line width of 1F is as follows. The layout with the repeated layout minimizes the area with adjacent cells, which increases the margin of microprocessing, is advantageous for high integration of devices, and suppresses the occurrence of short circuits, thereby improving process yield and device reliability. have.

Claims (2)

Rectangular active regions arranged in a matrix form, A method of laying out a semiconductor device, comprising: word lines traversing the active region, the word lines being arranged to traverse two in one active region; And the word line includes two slanted word lines, one to the left and one to the one straight word line. Rectangular active regions arranged in a matrix form, A method of laying out a semiconductor device, comprising: word lines traversing the active region, the word lines being arranged to traverse two in one active region; The active region is a rectangular shape of the size of 6F-1F and maintains the vertical and horizontal spacing of 1F, the degree of staggering between the vertical arrangement, the lower active region is moved to the right by 2F than the upper active region, It is arranged in a vertical direction across the active area, and disposed so as to cross two in one active area, one straight word line overlaps the width of 1F with a space of 1.5F and 2.5F distance from both ends of the active area. Two oblique word lines extending in a vertical direction to the left and right of the straight wood line, and the oblique word line passes through a portion overlapping with the active area at the same distance as the straight word line, The semiconductor device layout method characterized in that the inclined by 0.5F sequentially left and right to cross the top and bottom active regions alternately.