KR20040051672A - Circuit for generating reference voltage in semiconductor memory device - Google Patents

Abstract

PURPOSE: A reference voltage generation circuit of a semiconductor memory device is provided to reduce the area of a circuit by generating reference voltages with a different level each other. CONSTITUTION: A reference voltage generator(70) receives an external source voltage to generate and output first and second reference voltages(VREF1,VREF2). A peripheral region reference voltage generator(72) receives the first reference voltage(VREF1) generated in the reference voltage generator(70) to generate a reference voltage used in a peripheral circuit region. A cell region reference voltage generator(74) receives the second reference voltage(VREF2) generated in the reference voltage generator(70) to generate a reference voltage used in a memory cell array region. A first standby reference voltage supplier(76) supplies the reference voltage generated from the peripheral region reference voltage generator(72) for a standby reference voltage. A first active reference voltage supplier(78) supplies the reference voltage generated from the peripheral region reference voltage generator(72) for an active reference voltage. A second standby reference voltage supplier(80) supplies the reference voltage generated from the cell region reference voltage generator(74) for the standby reference voltage. A second active reference supplier(82) supplies the reference voltage generated from the ell region reference voltage generator(74) for an active reference voltage. A peripheral circuit(84) receives a voltage supplied from the first standby reference voltage supplier(76) or the first active reference voltage supplier(78) so as to operate. An operational voltage generator(86) receives a voltage supplied from the first standby reference voltage supplier(76) or the first active reference voltage supplier(78) to generates all sort of operational voltages. A memory cell array(88) receives a voltage supplied from the second standby reference voltage supplier(80) or the second active reference supplier(82) so as to operate.

Description

Reference voltage generating circuit of semiconductor memory device {CIRCUIT FOR GENERATING REFERENCE VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a reference voltage generating circuit of a semiconductor device, and more particularly to a reference voltage generating circuit having a plurality of output voltages in a semiconductor memory device.

In recent years, semiconductor memory devices generally adopt an internal voltage generator circuit that inputs an external power supply voltage and generates an internal voltage lower than that for low voltage and low power consumption. For example, in a semiconductor memory device such as an EDO DRAM, an internal voltage generator circuit lowers an external supply voltage of 3.3V to an internal supply voltage of about 2.8V.

As described above, the internal voltage generation circuit in the semiconductor memory device represents a circuit which lowers the power level supplied from the outside to an arbitrary level and supplies it to the power inside the chip. The internal voltage generation circuit not only ensures a stable power supply inside the chip when the external power supply voltage fluctuates, but also proactively copes with the fluctuation according to temperature or process conditions, thereby ensuring a constant performance of the chip.

As the degree of integration of semiconductor memory devices increases, the gate applied voltage and the thickness of the gate oxide film of the MOSFET used continuously decrease. Accordingly, when the external voltage is used as the operating voltage of the semiconductor memory device, a voltage higher than the breakdown voltage limit of the gate oxide film is applied, and the reliability characteristics of the MOS field effect transistor are deteriorated. To solve this problem, it is possible to increase the reliability of the transistor device by lowering the power supply voltage used in the semiconductor memory device compared to the external voltage.

In addition, the power consumption of the CMOS circuit is proportional to the square of the voltage, so a low power supply voltage can reduce the power consumption. In particular, when the internal voltage source is described as a constant voltage source having a constant voltage level, a stable power supply voltage can be obtained even when the external power supply voltage fluctuates, and thus the operation of the chip is also stabilized. In order to obtain a good internal voltage source, a reference voltage generator, which is a circuit that stably supplies a constant voltage against temperature or external voltage fluctuations, is required. To design a reference voltage generator, a voltage based on a physical constant is used. Typical examples include a built-in voltage of a PN junction and a threshold voltage of an MOS structure.

In general, in a CMOS circuit, since a PN junction or a bipolar transistor is not optimized in terms of fixed conditions or design variables, a MOS type reference voltage generator as shown in FIG. 1 is used. This circuit always connects an NMOS transistor to a diode and always near a threshold voltage. Constant voltage was maintained.

MOS-type reference voltage generators generally have short circuits, which have lower temperature characteristics than bipolar ones. To compensate for this, the voltage generator was designed by adding a voltage divider in which a general resistor and a MOS resistor were connected in series to the output of the MOS type reference voltage generator as shown in FIG. 2.

The MOS type reference voltage generator of FIG. 1 has a negative temperature coefficient. As shown in FIG. 2, the voltage divider is designed such that the general resistance is located above the MOS resistor and the voltage ratio of the voltage divider is positive. Since it has the improved temperature coefficient characteristics compared to FIG.

3 is a configuration diagram of an internal power supply voltage generation circuit of a general semiconductor memory device.

A reference voltage generator 10 for generating and outputting a reference voltage by receiving an external voltage and a reference voltage V _REFP which is used in a peripheral circuit area by receiving a reference voltage V _REF generated from the reference voltage generator 10. Periphery region reference voltage generator 12 generating the reference voltage and the reference voltage V _REF generated from the reference voltage generator 10 to generate the reference voltage V _REFA used in the memory cell array region. A first standby reference voltage supply unit 16 for supplying a reference voltage V _REFP generated from the cell region reference voltage generator 14 and the peripheral region reference voltage generator 12 as a standby reference voltage; The first active reference voltage supply unit 18 for supplying the reference voltage V _REFP generated from the peripheral region reference voltage generator 12 as the active reference voltage and the cell region reference voltage generator 14 voltage with a reference voltage (V _REFA) criteria for standby A second standby reference voltage supply 20, and a second active reference voltage supply for supplying a reference voltage (V _REFA) generated by the cell region reference voltage generation section 14 as the reference voltage for the active for supplying a ( 22, a peripheral circuit 24 operating by receiving a voltage supplied from the first standby reference voltage supply unit 16 or the first active reference voltage supply unit 18, and the first standby reference voltage supply unit 16. (B) an operation voltage generator 26 for receiving various voltages supplied from the first active reference voltage supply unit 18 and generating various operating voltages; and the second standby reference voltage supply unit 20 or the second active reference voltage. The memory cell array 28 operates by receiving a voltage supplied from the supply unit 22.

4 is a detailed circuit diagram of the peripheral circuit region reference voltage generator 12 and the cell region reference voltage generator 14 of FIG. 3.

The comparator 30 for comparing the reference voltage V _REFA used in the memory cell array area or the reference voltage V _REFP used in the peripheral circuit area with a set reference voltage and outputting the comparator 30. And a resistor (R1, R2) for outputting a divided voltage for controlling gain by being connected between the drain and the ground of the P-MOS transistor 32 to adjust the output voltage. have.

The reference voltage (V _REFA ) used in the memory cell array region or the reference voltage (V _REFP ) used in the peripheral circuit region is input to one input of the comparator 30, and the divided voltages of the resistors R1 and R2 are input to the comparator. It is input to another input of 30, and at this time, the values of the resistors R1 and R2 are set to have a constant gain. The resistors R1 and R2 are used as voltage dividers using polysilicon resistors or MOS resistors, and have a large resistance value corresponding to several hundred kΩ to reduce current consumption. In this case, since the polysilicon pattern having a very large area is required, the capacitance generated by the resistance pattern is large, resulting in unstable operation of the peripheral circuit region reference voltage generator 12 and the cell region reference voltage generator 14. There is.

In addition, the area of polysilicon resistors increases, which increases the complexity in terms of layout. In order to prevent such a problem, as shown in FIG. 5, the MOS is diode-connected. At this time, the most appropriate ratio of MOS resistors MP1 and MP2 is one. When the gate width and length of the MOS transistors corresponding to the MOS resistors MP1 and MP2 are the same, the gate width and length of the MOS transistors corresponding to the MOS resistors MP1 and MP2 are equal to the process variation and temperature change. The reference voltage (V _REFA ) used in the constant memory cell array region having a level twice the reference voltage (V _REF ) or the reference voltage (V _REFP ) used in the peripheral circuit region can be obtained for process variation and temperature change. have.

Double designing and a reference voltage (V _REF), except using a single reference voltage (V _REF) to which one of the levels when generating a reference voltage of the internal power supply voltage having at least two different voltage levels, such as the This can greatly increase the rate of change in process and temperature fluctuations.

In order to solve this problem, as shown in FIG. 6, an internal voltage generation circuit having a reference voltage generation unit generating different voltage levels is disclosed.

The first reference voltage generator 40 receives an external voltage and generates and outputs a first reference voltage V _REF1 . The second reference voltage generator 40 receives an external voltage and generates and outputs a second reference voltage V _REF2 . The peripheral region reference voltage generator 44 receives the first reference voltage V _REF1 generated by the first reference voltage generator 40 and generates and outputs a reference voltage V _REFP used in the peripheral circuit region. . The cell region reference voltage generator 46 receives the second reference voltage V _REF2 generated from the second reference voltage generator 42 to generate and output a reference voltage V _REFA used in the memory cell array region. do. The first standby reference voltage supply unit 48 supplies the reference voltage V _REFP generated from the peripheral region reference voltage generator 44 as a standby reference voltage. The first active reference voltage supply unit 50 supplies the reference voltage V _REFP generated from the peripheral region reference voltage generator 44 as an active reference voltage. The second standby reference voltage supply unit 52 supplies the reference voltage V _REFA generated from the cell region reference voltage generator 46 as a standby reference voltage. The second active reference voltage supply unit 54 supplies the reference voltage V _REFA generated from the cell region reference voltage generator 46 as an active reference voltage. The peripheral circuit 24 operates by receiving a voltage supplied from the first standby reference voltage supply unit 16 or the first active reference voltage supply unit 18. The operation voltage generator 58 receives a voltage supplied from the first standby reference voltage supply unit 48 or the first active reference voltage supply unit 50 to generate various operating voltages and apply them to the peripheral circuit 56. The memory cell array 60 operates by receiving a voltage supplied from the second standby reference voltage supply unit 52 or the second active reference voltage supply unit 54.

In the conventional internal power supply voltage generation circuit as described above, two or more reference voltage generators for generating reference voltages having different levels have to be designed, thereby increasing the area of the circuit and making the layout complicated.

Accordingly, an object of the present invention is to provide a reference voltage generator circuit of a semiconductor memory device capable of reducing the area of a circuit and simplifying the layout by generating reference voltages having different levels with one reference voltage generator.

The reference voltage generation circuit of the semiconductor memory device of the present invention for achieving the above objects, the preliminary reference voltage generation unit for generating a preliminary reference voltage having a plurality of levels set by inputting an external power supply voltage, and generating the preliminary reference voltage And a voltage divider for inputting a plurality of preliminary reference voltages generated from a negative part to output a plurality of reference voltages of different levels.

The preliminary reference voltage generator may include a first resistor connected between the external power supply voltage and the first node to limit a current, and a power source connected in series between the first node and the second node and input through the first resistor. Second and third resistors for dividing a voltage and outputting the voltage; a first NMOS transistor having a drain-source connected between the second node and the third node and a gate connected to the first node; A drain-source is connected between the ground power supply, a second NMOS transistor whose gate is connected to the external power supply voltage, a source-drain is connected between the first node and the ground power supply, and a gate is connected to the second node. It is characterized by including a PMOS transistor.

The voltage dividers may include resistors connected between the same reference voltage nodes corresponding to the preliminary reference voltages and a ground power source.

The resistors are made of a resistor and a MOS resistor composed of a MOS transistor.

The reference voltage generation circuit of the semiconductor memory device of the present invention for achieving the above object, the first resistor connected between the external power supply voltage and the first node to limit the current, and in series between the first node and the second node; Second and third resistors connected to each other to divide and output a power supply voltage input through the first resistor; and a drain-source connected between the second node and the third node and a gate connected to the first node. A first NMOS transistor, a drain-source connected between the third node and the ground power supply, and a gate connected to the external power supply voltage; and a source-drain between the first node and the ground power supply. A first voltage divider connected to the PMOS transistor having a gate connected to a second node, a first voltage divider connected between the first node and a ground power source, and outputting a first reference voltage; And a is connected between the fourth node and a lower supply voltage between the third resistance is characterized by made of an a second voltage divider for outputting a second reference voltage.

The first voltage divider includes a resistor connected to the first node, a third MOS transistor having a gate connected to the first node, a drain connected to the resistor, and a source connected to a ground power source.

The second voltage divider includes a fourth MOS transistor having a resistor connected to the fourth node, a gate connected to the fourth node, a drain connected to the resistor, and a source connected to a ground power source.

1 is a circuit diagram of a conventional MOS type reference voltage generator

2 is a circuit diagram of a conventional MOS type reference voltage generator with improved positive temperature coefficient characteristics.

3 is a configuration diagram of an internal power supply voltage generation circuit of a semiconductor memory device to which one reference voltage generator is applied;

4 is a detailed circuit diagram of an exemplary embodiment of the peripheral circuit region reference voltage generator 12 and the cell region reference voltage generator 14 of FIG. 3.

FIG. 5 is a detailed circuit diagram of another embodiment of the peripheral circuit region reference voltage generator 12 and the cell region reference voltage generator 14 of FIG. 3.

6 is a configuration diagram of an internal power supply voltage generation circuit of a semiconductor memory device to which a plurality of reference voltage generators are applied.

7 is a circuit diagram for generating an internal power supply voltage of a semiconductor memory device according to an exemplary embodiment of the present invention.

8 is a detailed circuit diagram of the reference voltage generator 70 of FIG. 7 according to an embodiment of the present invention.

9 is a detailed circuit diagram of a reference voltage generator according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

70: reference voltage generator 72: peripheral region reference voltage generator

74: cell region reference voltage generator 76: first standby reference voltage supply unit

78: first active reference voltage supply unit 80: second standby reference voltage supply unit

82: second active reference voltage supply unit 84: peripheral circuit

86: operation voltage generator 88: memory cell array

Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It should be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth. It should be noted that the following examples are intended to be illustrative and to sufficiently convey the spirit of the present invention to those skilled in the art. It should also be noted that detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention are omitted.

7 is a circuit diagram for generating an internal power supply voltage of a semiconductor memory device according to an exemplary embodiment of the present invention.

A reference voltage generator 70 for generating and outputting a predetermined first reference voltage V _REF1 and a second reference voltage V _{REF2 by} receiving an external power supply voltage; and generated from the reference voltage generator 70. A peripheral region reference voltage generator 72 that receives the first reference voltage V _REF1 and generates a reference voltage V _REFP used in the peripheral circuit region, and a second reference generated from the reference voltage generator 70; The cell region reference voltage generator 74 receives the voltage V _REF and generates the reference voltage V _REFA used in the memory cell array region, and the reference voltage V generated from the peripheral region reference voltage generator 72. _REFP ) for supplying a first standby reference voltage supply unit 76 for supplying a standby reference voltage and a reference voltage V _REFP generated from the peripheral region reference voltage generator 72 as an active reference voltage. A first active reference voltage supply unit 78 and a cell region reference voltage generation unit A second standby reference voltage supply unit 80 for supplying the reference voltage V _REFA generated from the 74 as a standby reference voltage, and the reference voltage V _REFA generated from the cell region reference voltage generator 74. ) And a second active reference voltage supply unit 82 for supplying an active reference voltage and a voltage supplied from the first standby reference voltage supply unit 76 or the first active reference voltage supply unit 78 A peripheral circuit 84, an operating voltage generation unit 86 for receiving various voltages supplied from the first standby reference voltage supply unit 76 or the first active reference voltage supply unit 78 and generating various operating voltages; The memory cell array 88 is configured to operate by receiving a voltage supplied from the second standby reference voltage supply unit 80 or the second active reference voltage supply unit 82.

8 is a detailed circuit diagram of the reference voltage generator 70 of FIG. 7 according to an exemplary embodiment of the present invention.

The resistor R1 is connected between the external power supply voltage V _DD and the first node N1 to limit the current. The resistor R2 is connected between the first node N1 and the second node N2 so that the first reference voltage V _REF1 appearing at the first node N1 is set to be higher than or equal to a specific voltage. In the first NMOS transistor M1, a drain is connected to the second node N2, a gate is connected to the first node N1, and a source is connected to the third node N3. A drain of the second NMOS transistor M2 is connected to the third node N3, an external power supply voltage V _DD is connected to the gate, and a source is connected to the ground. The second NMOS transistor M2 controls the enable or disable of the reference voltage generation circuit in response to the power-on. In the PMOS transistor M3, a source is connected to the first node N1, a gate is connected to the second node M2, and a drain is grounded. The PMOS transistor M3 provides a threshold voltage V _tp across the resistor R2 connected between the first node N1 and the second node N2. The resistor R11 is connected between the first node N1 and the first reference voltage output terminal. In the third NMOS transistor MN1, a gate is connected to the first node N1, a drain is connected to the resistor R11, and a source is grounded. The resistor R12 is connected between the fourth node N4, which is a connection node of the resistors R1 and R2, and the second reference voltage output terminal. In the fourth NMOS transistor MN2, a gate is connected to the fourth node N4, a drain is connected to the resistor R12, and a source is grounded.

7 and 8 will be described in detail the operation of the preferred embodiment of the present invention.

The reference voltage generator 70 receives an external voltage and generates and outputs a first reference voltage V _REF1 and a second reference voltage V _REF2 . The operation of generating the first and second reference voltages V _{REF1 and} V _REF2 will be described in detail with reference to FIG. 8 for the operation of the reference voltage generator 70. If the channel on resistance of M2) is called the equivalent resistance R _eq , and the threshold voltage of the PMOS transistor M3 is | V _TP |, the first preliminary reference voltage V _f1 output through the node N1 is It can obtain | require by following formula (1).

The reference voltage V _f1 outputted through the node N1 is divided by a MOS resistor composed of the resistor R11 and the third NMOS transistor MN1 to generate and output the first reference voltage V _REF1 . .

The second preliminary reference voltage V _f2 output through the node N4 may be obtained by Equation 2 below.

The second preliminary reference voltage V _f2 outputted through the node N4 is divided by the MOS resistor including the resistor R12 and the fourth enMOS transistor MN2 to generate a second reference voltage V _REF2 . To print.

The peripheral region reference voltage generator 72 receives the first reference voltage V _REF1 generated by the reference voltage generator 70 to generate and output a reference voltage V _REFP used in the peripheral circuit region. The cell region reference voltage generator 76 receives the second reference voltage V _REF2 generated from the second reference voltage generator 72 to generate and output a reference voltage V _REFA used in the memory cell array region. do. The first standby reference voltage supply unit 76 supplies the reference voltage V _REFP generated from the peripheral region reference voltage generator 74 as a standby reference voltage. The first active reference voltage supply unit 78 supplies the reference voltage V _REFP generated from the peripheral region reference voltage generator 74 as an active reference voltage. The second standby reference voltage supply unit 80 supplies the reference voltage V _REFA generated from the cell region reference voltage generator 74 as a standby reference voltage. The second active reference voltage supplyer 82 supplies the reference voltage V _REFA generated from the cell region reference voltage generator 74 as an active reference voltage. The peripheral circuit 84 operates by receiving a voltage supplied from the first standby reference voltage supply unit 76 or the first active reference voltage supply unit 78. The operation voltage generator 86 receives a voltage supplied from the first standby reference voltage supply unit 76 or the first active reference voltage supply unit 78, generates various operation voltages, and applies them to the peripheral circuit 84. The memory cell array 88 operates by receiving a voltage supplied from the second standby reference voltage supply unit 80 or the second active reference voltage supply unit 82.

9 is a detailed circuit diagram of a reference voltage generator according to another exemplary embodiment of the present invention.

An embodiment in which N reference voltages V _REF1 to V _REFN are generated. Similar to the reference voltage generator for outputting the two reference voltage levels shown in FIG. 8, a resistor connecting the gate and the source of the PMOS transistor is connected. Branching into N and connecting the voltage divider consisting of MOS equivalent resistors consisting of general resistors (R11 to R1n) and enMOS transistors (MN1 to MNN) at each branch of N-1 and starting point of resistor, respectively The N reference voltages V _REF1 to V _REFN are generated at the connection nodes of the equivalent resistors of the NMOS transistors MN1 to MNN. As a result, the required number of reference voltage levels excellent in sensitivity to temperature and external voltage can be obtained from a single reference voltage generator.

In the first embodiment of the present invention, a reference voltage generator for generating different first and second reference voltages is provided to supply operating voltages of the peripheral circuit 84 and the memory cell array 88 to different reference voltages. However, as shown in FIG. 9, two or more first to Nth reference voltages V _{REF1 to} V _REFN are generated by the reference voltage generator to generate an operating voltage used for the peripheral circuit 84 and the memory cell array 88. It is also possible to implement to supply without departing from the scope of the present invention.

As described above, the present invention generates a plurality of reference voltages in one reference voltage generator in the semiconductor memory device, and generates operating voltages of the peripheral circuits of the semiconductor memory and the operating voltages of the memory cell array using the reference voltages, respectively. Since it is possible to generate a plurality of reference voltages with one reference voltage generator, the circuit area can be reduced and the layout can be simplified.

In addition, the present invention can change the internal power supply voltage or high voltage by changing the reference voltage in the semiconductor memory device has the effect of reducing the production cost or development period by strengthening the test environment.

Claims (7)

In the reference voltage generation circuit of a semiconductor memory device, A preliminary reference voltage generating unit generating a preliminary reference voltage having a plurality of levels set by inputting an external power supply voltage; And a voltage divider configured to input a plurality of preliminary reference voltages generated from the preliminary reference voltage generator to output a plurality of reference voltages at different levels. The method of claim 1, wherein the preliminary reference voltage generator, A first resistor connected between the external power supply voltage and a first node to limit a current; Second and third resistors connected in series between the first node and the second node to divide and output a power supply voltage input through the first resistor; A first NMOS transistor having a drain-source connected between the second node and a third node and a gate connected to the first node; A second NMOS transistor having a drain-source connected between the third node and a ground power supply and a gate connected to the external power supply voltage; And a PMOS transistor having a source-drain connected between the first node and a ground power supply and a gate connected to the second node. The method of claim 2, wherein the voltage dividers, And a resistor connected between the same number of reference voltage nodes corresponding to the preliminary reference voltages and a ground power source. The method of claim 3, And the resistors comprise a resistor and a MOS resistor composed of MOS transistors. In the reference voltage generation circuit of a semiconductor memory device, A first resistor connected between the external power supply voltage and the first node to limit current; Second and third resistors connected in series between the first node and the second node to divide and output a power supply voltage input through the first resistor; A first NMOS transistor having a drain-source connected between the second node and a third node and a gate connected to the first node; A second NMOS transistor connected between the third node and a ground power source and having a gate connected to the external power voltage; A PMOS transistor having a source-drain connected between the first node and a ground power supply and a gate connected to the second node; A first voltage divider connected between the first node and a ground power source and outputting a first reference voltage; And a second voltage divider connected between a fourth node and a ground power source between the second resistor and the third resistor to output a second reference voltage. The method of claim 5, wherein the first voltage divider, A resistor connected to the first node; And a third MOS transistor having a gate connected to the first node, a drain connected to the resistor, and a source connected to a ground power source. The method of claim 6, wherein the second voltage divider, A resistor connected to the fourth node; And a fourth MOS transistor having a gate connected to the fourth node, a drain connected to the resistor, and a source connected to a ground power source.