KR100919807B1 - Reference Voltage Generation Circuit - Google Patents

Abstract

The present invention includes a first reference voltage generator for generating a first reference voltage; A selection signal generator for generating a selection signal according to a test mode signal or a fuse signal; And a second reference voltage generator configured to receive the selection signal and the first reference voltage to generate a second reference voltage.

Description

Reference Voltage Generation Circuit

The present invention relates to a semiconductor memory device. More specifically, the level change of the first reference voltage VREF_Widler according to a change in PVT characteristics is canceled to generate a second reference voltage VREF0 having a stable level even when the PVT characteristics change. And a reference voltage generating circuit.

Currently, a DRAM (DRAM) is a voltage conversion circuit that generates a low level reference voltage by receiving an external power source and includes a reference voltage generation circuit. In order to improve the operation reliability of the DRAM, the reference voltage generated by the reference voltage generation circuit should be set to a constant voltage so that the level can be stably maintained regardless of the level variation of the external power supply.

1 is a circuit diagram of a Widlar reference voltage generator included in a reference voltage generator according to the prior art, and FIG. 2 is a circuit diagram of a reference voltage generator included in the reference voltage generator according to the prior art.

The reference voltage generation circuit according to the prior art is composed of the Widlar reference voltage generator 1 shown in FIG. 1 and the reference voltage generator 2 shown in FIG. 2. As shown, the Widlar reference voltage generator 1 generates the first reference voltage VREF_Widler using the potential difference generated by the resistors R10 and R12. The reference voltage generator 2 receives the first reference voltage VREF_Widler and generates a second reference voltage VREF0. Looking at the generation process of the second reference voltage (VREF0) in more detail as follows.

First, the distribution signal VA is generated by voltage-dividing the second reference voltage VREF0 through the voltage divider 20. Next, the driving signal PU0 is generated by comparing the distribution signal VA0 with the first reference voltage VREF_Widler. When the distribution signal VA0 is at a level lower than the first reference voltage VREF_Widler, the driving signal PU0 is at a low level. Next, the low level driving signal PU0 turns on the PMOS transistor P22 of the driving unit 24 to drive the second reference voltage VREF0 to an external voltage.

In the reference voltage generation circuit according to the related art which drives the second reference voltage VREF0 by using the first reference voltage VREF_Widler generated by the Widlar reference voltage generator 1, PVT (Process), Voltage ( In order to generate the second reference voltage VREF0 having no fluctuation even in the change of voltage) and temperature) characteristics, the first reference voltage VREF_Widler having a stable level even in the PVT characteristic change through the Widlar reference voltage generator 1. Should be generated. However, as shown in FIG. 3, when the temperature is changed from −40 ° C. to 120 ° C., the level of the first reference voltage VREF_Widler generated by the Widlar reference voltage generator 1 varies from 781V to 699 mV. Accordingly, the level of the second reference voltage VREF0 generated by the reference voltage generator 2 also varies from 900 mV to 804 mV according to the temperature change.

Accordingly, the present invention discloses a reference voltage generation circuit that cancels the level change of the first reference voltage VREF_Widler according to the PVT characteristic change to generate the second reference voltage VREF0 having a more stable level in response to the PVT characteristic change. do.

To this end, the present invention includes a first reference voltage generator for generating a first reference voltage; A selection signal generator for generating a selection signal according to a test mode signal or a fuse signal; And a second reference voltage generator configured to receive the selection signal and the first reference voltage to generate a second reference voltage.

In the present invention, the second reference voltage generation unit voltage division unit for generating a distribution voltage by voltage-dividing the second reference voltage; A driving signal generator for generating a driving signal by comparing the divided voltage with the first reference voltage; A driving unit driving the second reference voltage in response to the driving signal; And a division voltage adjusting unit configured to adjust a level of the division voltage in response to the selection signal and the first reference voltage.

In an embodiment, the voltage divider includes: a first resistor connected between the second reference voltage output terminal and a first node to which the divided voltage is output; And a second resistor element connected between the first node and the second node.

In the present invention, the distribution voltage adjusting unit may include a transfer unit transferring a signal of the second node in response to a selection signal; And a MOS transistor connected between the transfer unit and a ground terminal and turned on in response to the first reference voltage.

In an embodiment, the selection signal generation unit may include a fuse signal generation unit configured to generate a fuse signal in response to a power-up signal; A test mode signal generator configured to generate a test mode signal in response to the enable signal and the pulse signal; A selection unit selectively transferring the fuse signal or the test mode signal in response to the enable signal; And a decoder for decoding the output signal of the selector to generate the select signal.

In the present invention, the fuse signal generating unit for generating a fuse signal in response to the power-up signal; A test mode signal generator configured to generate a test mode signal in response to the enable signal and the pulse signal; A selection unit selectively transferring the fuse signal or the test mode signal in response to the enable signal; And a decoder for decoding the output signal of the selector to generate the select signal.

In an embodiment of the present invention, the fuse signal generation unit may include a first pull-up device connected between a power supply voltage and a third node to pull up the third node in response to a power-up signal; A first fuse connected to the third node to generate a first fuse signal; And a second fuse connected to the third node in parallel with the first fuse to generate a second fuse signal.

The test mode signal generator may include: a second pull-up device configured to pull-up a fourth node in response to the enable signal; A first pull-down element configured to pull down the fourth node in response to the pulse signal; An enable element for enabling the first pull-down element in response to the enable signal; A latch for latching a signal of the fourth node; And a counter configured to receive an output signal of the latch and to generate a first test mode signal and a second test mode signal by performing a counting operation in response to the pulse signal.

In the present invention, the selector receives the first fuse signal and the first test mode signal, and selectively transmits one of the first fuse signal and the first test mode signal in response to the enable signal. A first selection unit to make; And a second selector configured to receive the second fuse signal and the second test mode signal and selectively transmit one of the second fuse signal and the second test mode signal in response to the enable signal. do.

The first selector may include: a third pull-up device configured to pull-up a fifth node in response to the enable signal; A fuse signal transmitter configured to buffer the first fuse signal and transmit the buffered first fuse signal to the fifth node in response to the enable signal; A buffer for buffering the first test mode signal; And a logic unit configured to receive the output signal of the fuse signal transmitter and the buffer to perform a logic operation to generate a first output signal.

The second selector may include: a fourth pull-up device configured to pull-up a sixth node in response to the enable signal; A fuse signal transmitter configured to buffer the second fuse signal in response to the enable signal and to transfer the second fuse signal to the sixth node; A buffer for buffering the first test mode signal; And a logic unit configured to receive the output signal of the fuse signal transmitter and the buffer to perform a logic operation to generate a first output signal.

In the present invention, it is preferable that the decoder generates the first to fourth selection signals by decoding the first output signal and the second output signal.

In an embodiment of the present invention, the division voltage adjusting unit includes a MOS transistor connected between the second node and the ground terminal and turned on in response to the first reference voltage.

In addition, the present invention is a reference voltage generation circuit that receives a first reference voltage and generates a second reference voltage, the first node outputting a divided voltage obtained by voltage-dividing the second reference voltage output terminal and the second reference voltage; A voltage divider including a first resistor connected between the first resistor and a second resistor connected between the first node and the second node; A driving signal generator for generating a driving signal by comparing the divided voltage with the first reference voltage; A driving unit driving the second reference voltage in response to the driving signal; A fuse signal generation unit generating a fuse signal in response to a power-up signal, a test mode signal generation unit generating a test mode signal in response to an enable signal and a pulse signal, and the fuse signal in response to the enable signal; A selection signal generation unit including a selection unit for selectively transmitting a test mode signal and a decoder to decode an output signal of the selection unit to generate a selection signal; And a transfer unit configured to transfer a signal of the second node in response to a selection signal, and a MOS transistor connected between the transfer unit and a ground terminal and turned on in response to the first reference voltage. do.

1 is a circuit diagram of a Widlar reference voltage generator included in a reference voltage generation circuit according to the prior art.

2 is a circuit diagram of a reference voltage generator included in a reference voltage generator according to the related art.

FIG. 3 is a waveform diagram according to a temperature change of the second reference voltage VREF0 generated in FIG. 2.

4 is a block diagram showing a configuration of a reference voltage generation circuit according to an embodiment of the present invention.

5 is a circuit diagram of a first embodiment of the reference voltage generator included in FIG. 4.

FIG. 6 is a block diagram illustrating a configuration of a selection signal generator included in FIG. 4.

FIG. 7 is a circuit diagram of a fuse signal generator included in FIG. 6.

FIG. 8 is a circuit diagram of a test mode signal generator included in FIG. 6.

FIG. 9 is a circuit diagram of a first selector included in FIG. 6.

FIG. 10 is a circuit diagram of a decoder included in FIG. 6.

FIG. 11 is a waveform diagram according to a temperature change of the second reference voltage VREF0 generated in FIG. 4.

12 is a circuit diagram of a second embodiment of the reference voltage generator included in FIG. 4.

<Description of the symbols for the main parts of the drawings>

3: Widlar reference voltage generator 4: Reference voltage generator

42: drive signal generator 44: driver

46: distribution voltage control unit 50: fuse signal generation unit

52: test mode signal generator 54: first selector

56: second selector 58: decoder

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

4 is a block diagram illustrating a configuration of a reference voltage generation circuit according to an embodiment of the present invention, FIG. 5 is a circuit diagram according to a first embodiment of the reference voltage generation unit included in FIG. 4, and FIG. 6 is FIG. 4. 7 is a block diagram illustrating a configuration of a selection signal generator included in FIG. 7, FIG. 7 is a circuit diagram of a fuse signal generator included in FIG. 6, FIG. 8 is a circuit diagram of a test mode signal generator included in FIG. 6, and FIG. 6 is a circuit diagram of the first selector included in FIG. 6, and FIG. 10 is a circuit diagram of the decoder included in FIG. 6.

As shown in FIG. 4, the reference voltage generation circuit according to the present embodiment includes a Widlar reference voltage generation unit 3, a reference voltage generation unit 4, and a selection signal generation unit 5.

The Widlar reference voltage generator 3 may be implemented with the same circuit as the circuit illustrated in FIG. 1.

As illustrated in FIG. 5, the reference voltage generator 4 includes a voltage divider 40, a drive signal generator 42, a driver 44, and a divider voltage adjuster 46. The voltage divider 40 includes a resistor R40 and a resistor R41 to divide the voltage of the second reference voltage VREF0. The driving signal generator 42 includes an NMOS transistor N41 that receives the distribution voltage VA1 from the node nd44, an NMOS transistor N40 that receives the first reference voltage VREF_Widler, and a PMOS that configures a current mirror. Comprising transistors P40 and P41, differentially amplifies distribution voltage VA1 and first reference voltage VREF_Widler to generate drive signal PU1. The driver 440 is a capacitor C40 that maintains the potential of the PMOS transistor P42 and the node nd43 that pull-up the second reference voltage VREF0 with an external voltage in response to the low-level driving signal PU1. It is composed.

The distribution voltage adjusting unit 46 is connected between the node nd45 and the node nd46 and is turned on in response to the first selection signal DEC1 and between the node nd46 and the ground terminal. The NMOS transistor N43 connected to the first reference voltage VREF_Widler and turned on in response to the first reference voltage VREF_Widler, and the second transfer coupled between the node nd45 and the node nd47 and turned on in response to the second selection signal DEC2. An NMOS transistor N44 connected between the gate T41, the node nd47, and the ground terminal and turned on in response to the first reference voltage VREF_Widler, and connected between the node nd45 and the node nd48. A third transfer gate T42 turned on in response to the third selection signal DEC3, an NMOS transistor N45 connected between the node nd48 and a ground terminal and turned on in response to the first reference voltage VREF_Widler; A fourth transfer gate T43 connected between the node nd45 and the node nd49 and turned on in response to the fourth selection signal DEC4 and the node nd49 Is connected between the ground terminal is composed of an NMOS transistor (N46) being turned on in response to the first reference voltage (VREF_Widler).

As shown in FIG. 6, the selection signal generator 5 includes a fuse signal generator 50, a test mode signal generator 52, a first selector 54, a second selector 56, and a decoder. It consists of 58.

As illustrated in FIG. 7, the fuse signal generator 50 may pull up and drive the node nd50 in response to an inverter IV50 for inverting the power-up signal PWRUP signal and an output signal of the inverter IV50. A first fuse FU50 connected to the PMOS transistor P50, the node nd50 to generate the first fuse signal FUSE0, and a second fuse connected to the node nd50 to generate the second fuse signal FUSE1. 2 fuses (FU52).

The test mode signal generator 52 pulls down the node nd51 in response to the pulse signal TMPul and the PMOS transistor P51 for pulling up the node nd51 in response to the test mode enable signal TM_EN. The NMOS transistor N51, the NMOS transistor N50 for enabling pull-down driving of the NMOS transistor N51 in response to the test mode enable signal TM_EN, and the latch 522 for latching the signal of the node nd51. ), An inverter IV53 that inverts the output signal of the latch 522 to generate the counting enable signal CNTENB, and is activated in response to the test mode enable signal TM_EN, and counting enable signal CNTENB. The first counter 524 generates the first test mode signal TM1 and the second test mode signal TM2 is generated according to the first test mode signal TM1 and the counting enable signal CNTENB. The second counter 526 is configured.

As illustrated in FIG. 9, the first selector 54 selects the inverters IV54 and IV55 buffering the test mode enable signal TM_EN and the node nd54 in response to the output signal of the inverter IV54. The pull-up driving PMOS transistor P52, the fuse signal transfer unit 542, the inverter IV58 which inverts the first test mode signal TM1 and transfers it to the node nd55, the node nd54 and the node ( and a NAND gate ND50 that receives the signal of nd55 and generates a first output signal TMOUT1 that performs a negative logical product operation. The fuse signal transfer unit 542 includes inverters IV56 and IV57 that buffer the first fuse signal FUSE1 and transmit the buffered signal to the node nd54. Inverter IV57 operates in response to a signal from inverter IV55. In addition, the fuse signal transfer unit 542 pulls down the node nd57 in response to the signal of the node nd54 and the NMOS transistor N52 for pull-down driving the node nd56 in response to the inverted power-up signal PWRUPB. It consists of a driving NMOS transistor N53.

In the second selector 56, the second fuse signal FUSE2 is input instead of the first fuse signal FUSE1, and the second test mode signal TM2 is input instead of the first test mode signal TM1. The configuration is the same as that of the first selector 54 except that the second output signal TMOUT2 is output instead of the output signal TMOUT1.

As illustrated in FIG. 10, the decoder 58 decodes the first output signal TMOUT1 and the second output signal TMOUT2 to generate the first to fourth decoded signals S0-S3. -ND54, NAND gates ND55-ND57, NOR gates NR50, and inverters that decode the first to fourth decoding signals S0-S3 to generate the first to fourth selection signals DEC1-DEC4. (IV59-IV62).

The operation of the reference voltage generation circuit configured as described above will be described with reference to FIGS. 5 to 10.

 First, when the high level test mode enable signal TM_EN is input, the test mode signal generator 52 generates the first test mode signal TM1 and the second test mode signal TM2. That is, referring to FIG. 8, when the NMOS transistor N50 is turned on by the high level test mode enable signal TM_EN and the pulse signal TMPulse is input, the node nd51 is pulled down to drive the counting enable signal ( CNTENB) goes low level. The first counter 524 and the second counter 526 that have received the low level counting enable signal CNTENB start the counting operation and according to the pulse signal TMPulse, the first test mode signal TM1 and the first counter 524. 2 Generate a test mode signal TM2.

In this case, referring to FIG. 9, the high level test mode enable signal TM_EN is inverted by the inverter IV54 to generate the low level signal S1, and is inverted by the inverter IV55 to invert the high level. Generate signal S1B. The high level signal S1B prevents the inverter IV57 from operating so that the first fuse signal FUSE1 is not transmitted to the node nd54, and the low level signal S1 is applied to the PMOS transistor P52. The node nd54 is pulled up. Therefore, the first selector 54 outputs a signal having the same level as the first test mode signal TM1 as the first output signal TMOUT1. In addition, the second selector 56 having the same configuration also outputs a signal having the same level as the second test mode signal TM2 as the second output signal TMOUT2.

Referring to FIG. 10, the decoder 58 receiving the first output signal TMOUT1 and the second output signal TMOUT2 receives the first to fourth decoding signals S0-S3 and the first to fourth selection signals DEC1. -DEC4) The first to fourth decoding signals S0-S3 and the first to fourth selection signals DEC1 to DEC4 generated by the decoder 58 of the present embodiment are shown in Table 1 below.

TABLE 1

As shown in Table 1, enable of the first to fourth selection signals DEC1 to DEC4 is determined according to a combination of the first test mode signal TM1 and the second test mode signal TM2. That is, when the first test mode signal TM1 and the second test mode signal TM2 are 'low level and high level', respectively, the second to fourth selection signals among the first to fourth selection signals DEC1 to DEC4. The first to fourth selection signals DEC1 when (DEC2-DEC4) are enabled at a high level and the first test mode signal TM1 and the second test mode signal TM2 are 'high level and high level', respectively. Only the fourth selection signal DEC4 of the DEC4) is enabled at a high level.

As such, the generated first to fourth selection signals DEC1 to DEC4 are applied to the first to fourth transfer gates T40 to T43 of the reference voltage generator 4 illustrated in FIG. 5, respectively. At this time, the first to fourth NMOS transistors N43 to N46 connected to the first to fourth transfer gates T40 to T43 cancel out the variation of the first reference voltage VREF_Widler which is inversely proportional to temperature, thereby making it more stable to temperature changes. A second reference voltage VREF0 having a level is generated.

For example, at a low temperature of -90 ° C, since the level of the first reference voltage VREF_Widler is high, the turn-on degree of the NMOS transistors N43 -N46 is large. Accordingly, the level of the divided voltage VA1 output to the node nd44 is relatively low, and the level of the second reference voltage VREF0 generated therefrom is also lowered.

On the other hand, at a high temperature of 125 ° C, since the level of the first reference voltage VREF_Widler is low, the turn-on degree of the first to fourth NMOS transistors N43 to N46 is small. Accordingly, the level of the divided voltage VA1 output to the node nd44 is relatively high, and the level of the second reference voltage VREF0 generated therefrom is also increased.

In summary, the first to fourth NMOS transistors N43 to N46 lower the level of the distribution voltage VA1 at a low temperature to lower the level of the second reference voltage VREF0, and at a high temperature, The level is increased to increase the level of the second reference voltage VREF0. However, not all of the first to fourth NMOS transistors N43 to N46 operate, but only those connected to the enabled signals of the first to fourth selection signals DEC1 to DEC4 operate. That is, some or all of the first to fourth NMOS transistors N43 to N46 are selected by the first to fourth selection signals DEC1 to DEC4 to adjust the level of the distribution voltage VA1. That is, in order to cancel the level change according to the temperature change of the first reference voltage VREF_Widler, when the level change according to the temperature of the first reference voltage VREF_Widler is large, the first to fourth NMOS transistors N43 to N46 may be replaced. When all of them are operated, when the level change according to the temperature of the first reference voltage VREF_Widler is small, some of the first to fourth NMOS transistors N43 to N46 are operated.

Through the test mode, a combination of the first to fourth selection signals DEC1 to DEC4 when the level change of the second reference voltage VREF0 according to the temperature change is the smallest can be confirmed. In addition, the combination of the first test mode signal TM1 and the second test mode signal TM2 may be determined by the combination of the first to fourth selection signals DEC1 to DEC4.

When a combination of the first test mode signal TM1 and the second test mode signal TM2 capable of generating the second reference voltage VREF0 most stably is found, the first fuse FU50 and It is determined whether the second fuse FU52 is cut. Combination of the first fuse signal FUSE0 and the second fuse signal FUSE1 generated according to whether the first fuse FU50 and the second fuse FU52 are cut, and the first to fourth selection signals generated according thereto ( The combination of DEC1-DEC4) is shown in Table 2 below.

TABLE 2

As shown in the table, a first inverted fuse signal FUSE0B and a second inverted fuse signal FUSE1B corresponding to the first test mode signal TM1 and the second test mode signal TM2 exist.

For example, when the combination of the first test mode signal TM1 and the second test mode signal TM2 when the level change of the second reference voltage VREF0 is the smallest is 'low level, high level', The first fuse FU50 may not be cut, and the second fuse FU52 may be cut.

When the first fuse FU50 and the second fuse FU52 are set as described above, and the test mode enable signal TM_EN is shifted to the low level, the first counter 524 and the second counter 526 shown in FIG. ) Stops the operation and generates the low level first test mode signal TM1 and the second test mode signal TM2.

In addition, the inverter IV57 of the first selector 54 shown in FIG. 9 operates by the low level test mode enable signal TM_EN, and the low level first test mode signal TM1 is operated by the NAND gate. Since the ND50 is operated like an inverter, the first output signal TMOUT1 becomes at the same level as the first inverted fuse signal FUSE1B. Similarly, the second output signal TMOUT2 output from the second selector 56 is at the same level as the second inverted fuse signal FUSE2B.

As compared with Table 1 and Table 2, since the first test mode signal TM1 and the second test mode signal TM2, the first inverted fuse signal FUSE0B and the second inverted fuse signal FUSE1B correspond to each other, The combination of the first to fourth selection signals DEC1 to DEC4 generated by the decoder 58 is the same as the case where the first test mode signal TM1 and the second test mode signal TM2 are applied.

As described above, the first test mode signal TM1 and the second test mode signal which enable the test mode enable signal TM_EN to enable the second reference voltage VREF0 to have the most stable level even with temperature changes. After the combination of the TM2 is found, the first fuse FU50 and the second fuse FU52 capable of generating the corresponding first inverted fuse signal FUSE0B and the second inverted fuse signal FUSE1B through the combination. Determine the state of. As a result, the second reference voltage VREF0 having a small level change range may be generated even with a temperature change.

That is, referring to FIG. 11, when the temperature is changed from −40 ° C. to 120 ° C., the level of the first reference voltage VREF_Widler generated by the Widlar reference voltage generator 3 varies from 781 V to 699 mV, but generates a reference voltage. The level change of the second reference voltage VREF0 generated in the unit 4 is greatly reduced from 866 mV to 849 mV.

12 is a circuit diagram of a second embodiment of the reference voltage generator included in FIG. 4.

As shown in FIG. 12, the reference voltage generator 4 according to the present embodiment includes a voltage divider 60, a drive signal generator 62, a driver 64, and a divider voltage adjuster 66. do.

Unlike the reference voltage generator 4 shown in FIG. 5, the reference voltage generator 4 according to the present exemplary embodiment includes only one NMOS transistor N63 connected between the voltage divider 60 and the ground terminal. Therefore, there is no need to separately provide a circuit for generating the first to fourth selection signals DEC1 to DEC4, and the second reference voltage VREF0 is stabilized using only the NMOS transistor N63.

That is, at a low temperature, the level of the distribution voltage VA2 is lowered to lower the level of the second reference voltage VREF0, and at a high temperature, the level of the distribution voltage VA2 is increased to raise the level of the second reference voltage VREF0. .

Claims (19)

A first reference voltage generator configured to generate a first reference voltage; A selection signal generator for generating a selection signal according to a test mode signal or a fuse signal; And Comparing the level of the first reference voltage and the second reference voltage to drive the second reference voltage, the driving force for driving the second reference voltage includes a second reference voltage generator for adjusting in response to the selection signal Reference voltage generation circuit. The method of claim 1, wherein the second reference voltage generator A voltage divider configured to divide the second reference voltage by voltage to generate a divided voltage; A driving signal generator for generating a driving signal by comparing the divided voltage with the first reference voltage; A driving unit driving the second reference voltage in response to the driving signal; And And a division voltage adjusting unit configured to adjust a level of the division voltage in response to the selection signal and the first reference voltage. The method of claim 2, wherein the voltage divider is A first resistance element connected between the second reference voltage output terminal and a first node to which the divided voltage is output; And And a second resistance element connected between the first node and the second node. The method of claim 3, wherein the distribution voltage adjusting unit A transmission unit for transmitting a signal of the second node in response to a selection signal; And And a MOS transistor connected between the transfer unit and a ground terminal and turned on in response to the first reference voltage. The method of claim 1, wherein the selection signal generator A fuse signal generator configured to generate a fuse signal in response to the power-up signal; A test mode signal generator configured to generate a test mode signal in response to the enable signal and the pulse signal; A selection unit selectively transferring the fuse signal or the test mode signal in response to the enable signal; And And a decoder for decoding the output signal of the selector to generate the select signal. The method of claim 5, wherein the fuse signal generating unit A first pull-up element connected between a power supply voltage and a third node to pull-up the third node in response to a power-up signal; A first fuse connected to the third node to generate a first fuse signal; And And a second fuse connected to the third node in parallel with the first fuse and generating a second fuse signal. The method of claim 6, wherein the test mode signal generation unit A second pull-up element configured to pull-up a fourth node in response to the enable signal; A first pull-down element configured to pull down the fourth node in response to the pulse signal; An enable element for enabling the first pull-down element in response to the enable signal; A latch for latching a signal of the fourth node; And a counter configured to receive an output signal of the latch and to enable a counting operation in response to the pulse signal to generate the first test mode signal and the second test mode signal. The method of claim 7, wherein the selection unit A first selector configured to receive the first fuse signal and the first test mode signal and selectively transmit one of the first fuse signal and the first test mode signal in response to the enable signal; And And a second selector configured to receive the second fuse signal and the second test mode signal and selectively transmit one of the second fuse signal and the second test mode signal in response to the enable signal. Reference voltage generation circuit. The method of claim 8, wherein the first selector A third pull-up element configured to pull-up a fifth node in response to the enable signal; A fuse signal transmitter configured to buffer the first fuse signal and transmit the buffered first fuse signal to the fifth node in response to the enable signal; A buffer for buffering the first test mode signal; And And a logic unit configured to receive the fuse signal transfer unit and the output signal of the buffer and perform a logic operation to generate a first output signal. The method of claim 9, wherein the second selector A fourth pull-up element configured to pull-up a sixth node in response to the enable signal; A fuse signal transmitter configured to buffer the second fuse signal in response to the enable signal and to transfer the second fuse signal to the sixth node; A buffer for buffering the first test mode signal; And And a logic unit configured to receive the fuse signal transfer unit and the output signal of the buffer and perform a logic operation to generate a first output signal. The reference voltage generation circuit of claim 10, wherein the decoder generates the first to fourth selection signals by decoding the first output signal and the second output signal. The method of claim 3, wherein the distribution voltage adjusting unit And a MOS transistor connected between the second node and a ground terminal and turned on in response to the first reference voltage. In a reference voltage generation circuit that receives a first reference voltage and generates a second reference voltage, A first resistor connected between the second reference voltage output terminal and a first node outputting a divided voltage obtained by dividing the second reference voltage, and a second resistor connected between the first node and the second node Voltage divider comprising a; A driving signal generator for generating a driving signal by comparing the divided voltage with the first reference voltage; A driving unit driving the second reference voltage in response to the driving signal; A fuse signal generation unit generating a fuse signal in response to a power-up signal, a test mode signal generation unit generating a test mode signal in response to an enable signal and a pulse signal, and the fuse signal in response to the enable signal; A selection signal generation unit including a selection unit for selectively transmitting a test mode signal and a decoder to decode an output signal of the selection unit to generate a selection signal; And And a transfer unit configured to transfer a signal of the second node in response to a selection signal, and a MOS transistor connected between the transfer unit and a ground terminal and turned on in response to the first reference voltage. The method of claim 13, wherein the fuse signal generating unit A first pull-up element connected between a power supply voltage and a third node to pull-up the third node in response to a power-up signal; A first fuse connected to the third node to generate a first fuse signal; And And a second fuse connected to the third node in parallel with the first fuse to generate a second fuse signal. 15. The method of claim 14, wherein the test mode signal generation unit A second pull-up element configured to pull-up a fourth node in response to the enable signal; A first pull-down element configured to pull down the fourth node in response to the pulse signal; An enable element for enabling the first pull-down element in response to the enable signal; A latch for latching a signal of the fourth node; And a counter configured to receive an output signal of the latch and to enable a counting operation in response to the pulse signal to generate the first test mode signal and the second test mode signal. The method of claim 15, wherein the selection unit A first selector configured to receive the first fuse signal and the first test mode signal and selectively transmit one of the first fuse signal and the first test mode signal in response to the enable signal; And And a second selector configured to receive the second fuse signal and the second test mode signal and selectively transmit one of the second fuse signal and the second test mode signal in response to the enable signal. Reference voltage generation circuit. The method of claim 16, wherein the first selector A third pull-up element configured to pull-up a fifth node in response to the enable signal; A fuse signal transmitter configured to buffer the first fuse signal and transmit the buffered first fuse signal to the fifth node in response to the enable signal; A buffer for buffering the first test mode signal; And And a logic unit configured to receive the fuse signal transfer unit and the output signal of the buffer and perform a logic operation to generate a first output signal. The method of claim 17, wherein the second selector A fourth pull-up element configured to pull-up a sixth node in response to the enable signal; A fuse signal transmitter configured to buffer the second fuse signal in response to the enable signal and to transfer the second fuse signal to the sixth node; A buffer for buffering the first test mode signal; And And a logic unit configured to receive the fuse signal transfer unit and the output signal of the buffer and perform a logic operation to generate a first output signal. 19. The reference voltage generation circuit of claim 18, wherein the decoder generates the first to fourth selection signals by decoding the first output signal and the second output signal.