KR20040013122A - 반도체 칩용 패키지의 제조 방법 - Google Patents
반도체 칩용 패키지의 제조 방법 Download PDFInfo
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- KR20040013122A KR20040013122A KR10-2004-7000203A KR20047000203A KR20040013122A KR 20040013122 A KR20040013122 A KR 20040013122A KR 20047000203 A KR20047000203 A KR 20047000203A KR 20040013122 A KR20040013122 A KR 20040013122A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2924/151—Die mounting substrate
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- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims (13)
- a) 캐리어 기판(1)을 제공하는 단계,b) 일정한 온도 이상 가열되면 그 접착 특성을 잃어버리는 하나 이상의 접착층(4)을 상기 캐리어 기판(1)상에 제공하는 단계,c) 상기 캐리어 기판(1) 상에 반도체 칩(2)을 제공하고 상기 접착층(4)에 의해 고정하는 단계,d) 경화성 물질(6)을 제공하고 한번 이상의 열처리를 수행하는 단계를 포함하고, 상기 열 처리의 온도는 적어도 일시적으로 상기 접착층(4)이 그 접착 특성을 잃어버리는 온도 보다 높아서, 상기 접착층(4)이 그 접착 특성을 잃어버리고 상기 경화성 물질(6)이 경화되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항에 있어서,그 상부 면에 누빈(3)을 가진 캐리어 기판(1)이 제공되고, 상기 접착층이 상기 누빈(3)상에 제공되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 또는 제 2항에 있어서,상기 단계 d)에서 경화성 물질(6)이 제공되고 제 1 열처리가 수행됨으로써, 상기 경화성 물질이 응고되며, 상기 제 1 열처리의 온도는 상기 접착층(4)이 그 접착 특성을 잃어버리는 온도 미만이고, 후속해서 제 2 열처리가 수행되며, 상기 제2 열처리의 온도는 상기 접착층(4)이 그 접착 특성을 잃어버리는 온도 보다 높아서, 상기 접착층(4)이 그 접착 특성을 잃어버리고 상기 경화성 물질(6)이 경화되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 3항 중 어느 한 항에 있어서,상기 단계 d)전에 상기 반도체 칩(2)이 와이어 또는 필름-캐리어 본딩에 의해 상기 캐리어 기판(1)에 전기 접속되고, 상기 본딩 온도는 상기 접착층(4)이 그 접착 특성을 잃어버리는 온도 미만인 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 4항 중 어느 한 항에 있어서,상기 단계 b)에서 상기 접착층(4)이 펀칭 프로세스에 의해 제공되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 5항 중 어느 한 항에 있어서,상기 단계 b)에서 제 1 접착층, 베이스 층 및 제 2 접착층(4)이 제공되고, 적어도 상기 제 2 접착층(4)은 일정한 온도 이상으로 가열되면 그 접착 특성을 잃어버리는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 6항에 있어서,상기 제 1 접착층, 베이스 층 및 제 2 접착층(4)이 필름의 형태로 공동으로 제공되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 7항 중 어느 한 항에 있어서,상기 캐리어 기판(1)으로서 폴리이미드, BT 또는 FR4 기판이 사용되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 8항 중 어느 한 항에 있어서,상기 캐리어 기판(1)이 하나 이상의 본딩 채널(5)을 갖는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 9항 중 어느 한 항에 있어서,상기 경화성 물질(6)로서 실리콘과 에폭시수지의 혼합물 또는 순수한 에폭시수지가 사용되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 10항에 있어서,상기 단계 d)에서 제 1 열처리가 130℃ 내지 150℃ 의 온도로 수행된 다음, 제 2 열처리가 150℃ 내지 170℃의 온도로 수행되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 1항 내지 제 11항 중 어느 한 항에 있어서,상기 경화성 물질(6)이 프린팅 프로세스 또는 압축-몰딩 프로세스에 의해 제공되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
- 제 2항 내지 제 12항 중 어느 한 항에 있어서,상기 누빈(3)이 프린팅 프로세스 및 후속하는 열처리로 상기 캐리어 기판(1)상에 제공되는 것을 특징으로 하는 반도체 칩용 패키지의 제조 방법.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10133361.7 | 2001-07-10 | ||
DE10133361A DE10133361C2 (de) | 2001-07-10 | 2001-07-10 | Verfahren zur Herstellung einer Verpackung für Halbleiterchips |
PCT/EP2002/007439 WO2003007364A2 (de) | 2001-07-10 | 2002-07-04 | Verfahren zur herstellung einer verpackung für halbleiterchips |
Publications (2)
Publication Number | Publication Date |
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KR20040013122A true KR20040013122A (ko) | 2004-02-11 |
KR100575354B1 KR100575354B1 (ko) | 2006-05-03 |
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ID=7691194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020047000203A Expired - Fee Related KR100575354B1 (ko) | 2001-07-10 | 2002-07-04 | 반도체 칩용 패키지의 제조 방법 |
Country Status (5)
Country | Link |
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US (1) | US7326593B2 (ko) |
KR (1) | KR100575354B1 (ko) |
DE (1) | DE10133361C2 (ko) |
TW (1) | TW565898B (ko) |
WO (1) | WO2003007364A2 (ko) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10238581B4 (de) * | 2002-08-22 | 2008-11-27 | Qimonda Ag | Halbleiterbauelement |
DE102005015036B4 (de) | 2004-07-19 | 2008-08-28 | Qimonda Ag | Verfahren zur Montage eines Chips auf einer Unterlage |
CN100416811C (zh) * | 2005-10-24 | 2008-09-03 | 南茂科技股份有限公司 | 光电芯片封装构造、制造方法及其芯片承载件 |
DE102006023168B4 (de) * | 2006-05-17 | 2011-02-03 | Infineon Technologies Ag | Herstellungsverfahren für eine elektronische Schaltung |
Family Cites Families (16)
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US5030308A (en) * | 1986-07-14 | 1991-07-09 | National Starch And Chemical Investment Holding Corporation | Method of bonding a semiconductor chip to a substrate |
US4906314A (en) * | 1988-12-30 | 1990-03-06 | Micron Technology, Inc. | Process for simultaneously applying precut swatches of precured polyimide film to each semiconductor die on a wafer |
US5169056A (en) * | 1992-02-21 | 1992-12-08 | Eastman Kodak Company | Connecting of semiconductor chips to circuit substrates |
KR970008355B1 (ko) * | 1992-09-29 | 1997-05-23 | 가부시키가이샤 도시바 | 수지밀봉형 반도체장치 |
US5504374A (en) * | 1994-02-14 | 1996-04-02 | Lsi Logic Corporation | Microcircuit package assembly utilizing large size die and low temperature curing organic die attach material |
JP3195236B2 (ja) * | 1996-05-30 | 2001-08-06 | 株式会社日立製作所 | 接着フィルムを有する配線テープ,半導体装置及び製造方法 |
EP1793421A3 (en) * | 1996-10-08 | 2007-08-01 | Hitachi Chemical Co., Ltd. | Semiconductor device, substrate for mounting a semiconductor chip, process for their production, adhesive, and double-sided adhesive film |
JP2956617B2 (ja) * | 1996-10-31 | 1999-10-04 | 日本電気株式会社 | 樹脂封止型半導体装置 |
EP0886313A4 (en) * | 1996-12-04 | 2001-02-28 | Shinko Electric Ind Co | RESIN SEALED SEMICONDUCTOR DEVICE, MANUFACTURE OF SUCH DEVICE |
JPH10178145A (ja) * | 1996-12-19 | 1998-06-30 | Texas Instr Japan Ltd | 半導体装置及びその製造方法並びに半導体装置用絶縁基板 |
JP3293753B2 (ja) | 1997-01-31 | 2002-06-17 | 日立化成工業株式会社 | 半導体パッケージ用チップ支持基板及びこれを用いた半導体パッケージ |
JPH10303352A (ja) * | 1997-04-22 | 1998-11-13 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
US5972735A (en) * | 1998-07-14 | 1999-10-26 | National Starch And Chemical Investment Holding Corporation | Method of preparing an electronic package by co-curing adhesive and encapsulant |
KR100308884B1 (ko) * | 1998-12-22 | 2001-11-22 | 박종섭 | 씨모스 이미지 센서를 위한 아날로그-디지털 변환 장치 |
JP3384357B2 (ja) * | 1999-04-13 | 2003-03-10 | 日立電線株式会社 | 液晶ポリマーテープの接着方法、およびリードフレームへの半導体チップの搭載方法 |
DE19921113C2 (de) | 1999-05-07 | 2001-11-22 | Infineon Technologies Ag | Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine |
-
2001
- 2001-07-10 DE DE10133361A patent/DE10133361C2/de not_active Expired - Fee Related
-
2002
- 2002-06-20 TW TW091113504A patent/TW565898B/zh not_active IP Right Cessation
- 2002-07-04 WO PCT/EP2002/007439 patent/WO2003007364A2/de active Application Filing
- 2002-07-04 KR KR1020047000203A patent/KR100575354B1/ko not_active Expired - Fee Related
- 2002-07-04 US US10/483,212 patent/US7326593B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060211166A1 (en) | 2006-09-21 |
WO2003007364A2 (de) | 2003-01-23 |
DE10133361C2 (de) | 2003-05-28 |
TW565898B (en) | 2003-12-11 |
DE10133361A1 (de) | 2003-01-30 |
US7326593B2 (en) | 2008-02-05 |
WO2003007364A3 (de) | 2003-07-24 |
KR100575354B1 (ko) | 2006-05-03 |
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