KR20040006335A - Device for controlling sensing margin of magnetoresistive random access memory - Google Patents
Device for controlling sensing margin of magnetoresistive random access memory Download PDFInfo
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- KR20040006335A KR20040006335A KR1020020040585A KR20020040585A KR20040006335A KR 20040006335 A KR20040006335 A KR 20040006335A KR 1020020040585 A KR1020020040585 A KR 1020020040585A KR 20020040585 A KR20020040585 A KR 20020040585A KR 20040006335 A KR20040006335 A KR 20040006335A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
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Abstract
본 발명은 MRAM의 센싱 마진 제어 장치에 관한 것으로, MRAM의 트랜지스터 구조를 개선하여 센싱 마진을 향시킬 수 있도록 하는 MRAM의 센싱 마진 제어 장치에 관한 것이다. 이를 위해, 본 발명은 MRAM의 트랜지스터의 소스와 드레인 사이에 채널 저항에 상응하는 저항을 연결하고, 이를 이용하여 MTJ를 통한 센싱 마진의 증가와 MTJ 저항 스펙의 폭을 증가시킬 수 있도록 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensing margin control apparatus for an MRAM, and more particularly, to an apparatus for controlling a sensing margin for an MRAM, in which a sensing margin can be directed to a sensing margin. To this end, the present invention connects a resistor corresponding to the channel resistance between the source and the drain of the transistor of the MRAM, by using it to increase the sensing margin through the MTJ and the width of the MTJ resistance specification.
Description
본 발명은 MRAM의 센싱 마진 제어 장치에 관한 것으로, MRAM의 트랜지스터 구조를 개선하여 센싱 마진 및 MTJ 저항 스펙을 향상시킬 수 있도록 하는 MRAM의 센싱 마진 제어 장치에 관한 것이다The present invention relates to a sensing margin control device of the MRAM, and to a sensing margin control device of the MRAM to improve the sensing margin and MTJ resistance specifications by improving the transistor structure of the MRAM.
대부분의 반도체 메모리 제조 업체들은 차세대 기억소자의 하나로 강자성체 물질을 이용한 MRAM을 개발하고 있다.Most semiconductor memory manufacturers are developing MRAM using ferromagnetic materials as one of the next generation memory devices.
MRAM은 자기 물질의 박막에 자기 분극(Magnetic Polarization) 상태를 저장시키는 메모리 형태로서, 비트라인 전류와 워드라인 전류의 조합에 의해 생성된 자기장에 의해 자기 분극 상태를 바꾸거나 감지해 냄으로써 쓰기와 읽기 동작이 수행된다.MRAM is a type of memory that stores a magnetic polarization state in a thin film of magnetic material. The write and read operation is performed by changing or detecting a magnetic polarization state by a magnetic field generated by a combination of bit line current and word line current. This is done.
이러한 MRAM은 일반적으로 GMR(Giant Magneto Resistance), MTJ(MagneticTunnel Junction)등 여러 가지 셀 종류로 구성된다.Such MRAM is generally composed of several cell types such as Giant Magneto Resistance (GMR) and Magnetic Tunnel Junction (MTJ).
즉, MRAM은 스핀이 전자의 전달 현상에 지대한 영향을 미치기 때문에 생기는 거대자기저항(GMR) 현상이나 스핀 편극 자기투과 현상을 이용해 메모리 소자를 구현한다.In other words, MRAM implements a memory device by using a large magnetoresistance (GMR) phenomenon or spin polarization magnetic permeation phenomenon, which occurs because spin has a great influence on electron transfer.
먼저, 거대자기 저항(GMR) 현상을 이용한 MRAM은 비자성층을 사이에 둔 두 자성층에서 스핀방향이 같은 경우보다 다른 경우의 저항이 크게 다른 현상을 이용해 구현된다.First, an MRAM using a giant magnetoresistance (GMR) phenomenon is implemented using a phenomenon in which the resistance in the case where the spin directions are different in the two magnetic layers having a nonmagnetic layer between them is significantly different.
그리고, 스핀 편극 자기 투과 현상을 이용한 MRAM은 절연층을 사이에 둔 두자성층에서 스핀 방향이 같은 경우가 다른 경우보다 전류 투과가 훨씬 잘 일어난다는 현상을 이용해 구현된다.In addition, the MRAM using the spin polarization magnetic permeation phenomenon is implemented by using the phenomenon that current transmission occurs much better than the case where the spin direction is the same in the two magnetic layers having the insulating layer interposed therebetween.
이러한 MRAM은 많은 연구 개발이 진행중이나, 궁극적으로 마그네틱 분야 인가 영역인 MTJ(Magnetic Tunnel Junction)의 면적 및 형성 방식이 고집적도 실현에 가장 핵심 공정에 해당한다.MRAMs are under much research and development, but the area and formation method of magnetic tunnel junction (MTJ), which is an area of magnetic application, is the most important process for achieving high density.
도 1은 이러한 종래의 MRAM셀을 나타내는 구성도이다.1 is a block diagram showing such a conventional MRAM cell.
종래의 MRAM셀은 하나의 트랜지스터 T1와 하나의 MTJ(1)를 구비하는데, MTJ(1)는 전원전압 Vcc 레벨을 갖는 비트라인 BL과 연결되고, 트랜지스터 T1는 게이트가 워드라인 인에이블 전압 Vpp 레벨을 갖는 워드라인 WL이 연결된다.A conventional MRAM cell has one transistor T1 and one MTJ (1), where the MTJ (1) is connected to a bit line BL having a power supply voltage Vcc level, and the transistor T1 has a gate line at the word line enable voltage Vpp level. Is connected to the word line WL.
그런데, 종래의 MRAM셀은 트랜지스터 T1의 크기가 작아짐에 따라 발생되는 채널 저항 및 컨택저항의 증가로 인하여 상대적으로 센싱 가능한 MTJ(1)의 저항 영역이 감소되어 센싱 마진이 저하된다. 이 뿐만 아니라, 센싱 가능한 MTJ(1) 저항영역을 제조하기가 어려운 문제점이 있다.However, in the conventional MRAM cell, as the size of the transistor T1 decreases, the resistance area of the relatively sensitive MTJ 1 is reduced due to the increase in the channel resistance and the contact resistance, which lowers the sensing margin. In addition to this, there is a problem that it is difficult to manufacture a sensing MTJ (1) resistance region.
본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, MRAM셀 트랜지스터의 컨택저항 및 채널저항을 감소시키기 위해 트랜지스터의 소스단과 드레인단 사이에 채널 저항에 상응하는 저항을 연결하여 MTJ를 제외한 실제적인 저항값을 절반으로 줄임으로써 트랜지스터의 전류 구동 능력을 향상시켜 센싱 마진을 향상시키도록 하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in order to reduce the contact resistance and channel resistance of the MRAM cell transistor, a resistor corresponding to the channel resistance is connected between the source and drain terminals of the transistor, except for the MTJ. The goal is to improve the sensing margin by improving the current drive capability of the transistor by cutting the resistance in half.
도 1은 종래의 MRAM셀을 나타내는 도면.1 is a view showing a conventional MRAM cell.
도 2는 본 발명에 따른 MRAM의 센싱 마진 제어 장치를 나타내는 도면.2 is a diagram illustrating a sensing margin control apparatus of an MRAM according to the present invention;
상기한 목적을 달성하기 위한 본 발명의 MRAM의 센싱 마진 제어 장치는, 비트라인의 전류를 센싱하는 MTJ와, MTJ와 연결되어 게이트와 워드라인이 연결되는 트랜지스터 및 트랜지스터의 소스와 드레인 사이에 연결되어 저항 텀을 형성하는 저항을 구비함을 특징으로 한다.Sensing margin control apparatus of the MRAM of the present invention for achieving the above object, the MTJ for sensing the current of the bit line, the transistor connected to the MTJ and the gate and word line is connected between the source and drain of the transistor is connected And a resistance forming a resistance term.
이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.
도 2는 본 발명에 따른 MRAM의 센싱 마진 제어 장치의 구성도이다.2 is a block diagram of a sensing margin control apparatus of an MRAM according to the present invention.
본 발명은 도 2에 도시된 바와 같이, 하나의 트랜지스터 T1와 하나의 MTJ(1)및 더미(Dummy) 저항 R을 구비한다.As shown in FIG. 2, the present invention includes one transistor T1, one MTJ (1), and a dummy resistor R. As shown in FIG.
먼저, MTJ(10)는 전원전압 Vcc 레벨을 갖는 비트라인 BL과 연결되고, 트랜지스터 T2는 게이트가 워드라인 인에이블 전압 Vpp 레벨을 갖는 워드라인 WL과 연결된다.First, the MTJ 10 is connected to a bit line BL having a power supply voltage Vcc level, and the transistor T2 is connected to a word line WL whose gate has a word line enable voltage Vpp level.
또한, 트랜지스터 T2의 소스와 드레인 사이에는 저항 R이 연결되어, 저항 텀을 형성하게 된다. 이때, 소스와 드레인 사이에 형성되는 저항 텀은 트랜지스터 T2의 채널저항 및 컨택 저항에 상응한다.In addition, a resistor R is connected between the source and the drain of the transistor T2 to form a resistance term. At this time, the resistance term formed between the source and the drain corresponds to the channel resistance and the contact resistance of the transistor T2.
따라서, 트랜지스터 T2의 채널에 발생되는 전압과 저항 R 사이에는 같은 전압이 형성되고 채널 저항이 감소하여 실제적인 채널 저항은 절반으로 줄어들게 된다.Therefore, the same voltage is formed between the voltage generated in the channel of the transistor T2 and the resistor R, and the channel resistance decreases, thereby reducing the actual channel resistance by half.
이때, 트랜지스터 T2에 실제적으로 흐르는 전류의 양은 동일하다.At this time, the amount of current actually flowing through the transistor T2 is the same.
이에 따라, MTJ(10)는 트랜지스터 T2의 감소된 채널 저항에 대응하여 전류 변화를 센싱하게 되므로 센싱 마진을 향상시킬 수 있게 된다.Accordingly, the MTJ 10 senses a current change in response to the reduced channel resistance of the transistor T2, thereby improving the sensing margin.
이상에서 설명한 바와 같이, 본 발명은 트랜지스터의 크기가 작아짐에 따라 증가되는 채널 저항의 크기를 감소시켜 MTJ의 저항 변화에 대한 전류 변화의 센싱 마진을 증대시킬 수 있도록 하는 효과를 제공한다.As described above, the present invention provides an effect of increasing the sensing margin of the current change with respect to the resistance change of the MTJ by reducing the size of the channel resistance that increases as the size of the transistor decreases.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020020040585A KR20040006335A (en) | 2002-07-12 | 2002-07-12 | Device for controlling sensing margin of magnetoresistive random access memory |
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| KR1020020040585A KR20040006335A (en) | 2002-07-12 | 2002-07-12 | Device for controlling sensing margin of magnetoresistive random access memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030019262A (en) * | 2001-08-31 | 2003-03-06 | 휴렛-팩커드 컴퍼니(델라웨어주법인) | Methods and structure for maximizing signal to noise ratio in resistive array |
| US9183931B2 (en) | 2013-12-03 | 2015-11-10 | Samsung Electronics Co., Ltd. | Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors |
-
2002
- 2002-07-12 KR KR1020020040585A patent/KR20040006335A/en not_active Ceased
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030019262A (en) * | 2001-08-31 | 2003-03-06 | 휴렛-팩커드 컴퍼니(델라웨어주법인) | Methods and structure for maximizing signal to noise ratio in resistive array |
| US9183931B2 (en) | 2013-12-03 | 2015-11-10 | Samsung Electronics Co., Ltd. | Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors |
| US9378815B2 (en) | 2013-12-03 | 2016-06-28 | Samsung Electronics Co., Ltd. | Resistive memory device capable of increasing sensing margin by controlling interface states of cell transistors |
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