KR20040005499A - Method of manufacturing dielectric layer of semiconductor device - Google Patents

Abstract

Disclosed is a method of forming an insulating film of a semiconductor device in which the flatness of the SOG coating on the metal of the semiconductor device can be improved to minimize the thickness of the SOG on the metal and to form a good via profile. After the atomic layer deposition oxide is deposited on the semiconductor substrate on which the metal pattern is formed to form an atomic layer deposition oxide film, an undoped silicate glass oxide is deposited on the atomic layer deposition oxide film to form an undoped silicate glass oxide film. Spin-on glass is coated on the undoped silicate glass oxide film to form a spin-on glass insulating film, and an oxide is formed on the spin-on glass insulating film by applying an oxide. When the SOG coating, the gap fill is easy, the flatness is excellent, and the thickness of the SOG on the upper portion of the metal on which the via hole is formed can be minimized, thereby forming an insulating film of a semiconductor device having a good via profile.

Description

METHODS OF MANUFACTURING DIELECTRIC LAYER OF SEMICONDUCTOR DEVICE

The present invention relates to a method for forming an insulating film of a semiconductor device. More specifically, an insulating layer of a semiconductor device in which an atomic layer deposition (ALD) oxide and an undoped silicate glass (USG) oxide are deposited under a spin on glass (SOG) layer It is about a method.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to these demands, semiconductor technologies have been developed in the direction of improving the degree of integration, reliability and response speed.

Fabrication of integrated circuits requires the formation of many active devices on a single substrate. Initially, the devices must be isolated from each other, but to achieve the desired function of the circuit, certain devices need to be electrically interconnected during the manufacturing process. MOS and bipolar VLSI and ULSI devices have a multilevel interconnection structure that facilitates many interconnections of the devices. In such interconnect structures, as the number of layers increases, the topography of the top layer becomes more and more uneven and uneven.

For example, in the case of manufacturing a semiconductor wafer on which two or more metal layers are formed, after forming a first interlayer insulating film on a semiconductor wafer on which a plurality of oxide films, polycrystalline silicon conductive layers and first metal wiring layers are formed, A via is formed to electrically connect with the second metal layer. Since the lower structure of the first interlayer insulating film is uneven, the surface of the first interlayer insulating film is uneven. In the case of directly forming the second metal layer on the first interlayer insulating film, the second metal layer is fractured due to the protrusion or crack of the first interlayer insulating film, and the metal coating on the underlying insulating layer is poor. This failure lowers the yield of the semiconductor device, and therefore, in a multilevel metal interconnection, planarization of the interlayer insulating film is required before forming the via or the second metal layer.

For the planarization of the interlayer insulating film, various methods such as a BPSG (Borophosphorous Silicate Glass) film and a SOG film having high reflow characteristics and a chemical mechanical polishing (CMP) method have been developed.

In general, a method using BPSG has been widely used as a material of an interlayer insulating film for embedding a gap between metal wirings. However, the process of depositing BPSG has a strong dependence between facilities and chamber conditions, and the gas used is not only expensive but also toxic and thus poses a danger to the human body.

Moreover, as the degree of integration increases and the design rule decreases to manufacture VLSIs of 256 mega DRAM or more, the interlayer insulating film is formed using BPSG, and when the gaps between the wirings are filled, the bridge is formed by voids. Yield may decrease or the etch stop layer to be used in subsequent processes may be damaged. To avoid this, it is necessary to perform additional reflow process and expensive CMP process.

In contrast, the SOG film can form a flat insulating film by a simple coating process, and has advantages such as excellent step coverage and planarization characteristics. For example, Korean Patent Application No. 10-2000-0011238, US Patent No. 5,310,720 (issued to Shin et al), and US Patent No. 5,976,618 (issued to Shunichi Fukuyama et al.) Use an SOG film as an interlayer insulating film. A method is disclosed.

However, SOG has a problem in that it has a poor adhesiveness with a metal, so before forming the SOG film, the SOG is formed as a lower film. Phosphorus-containing tetraethyl orthosilicate (P-TEOS) oxide or plasma oxide (Plasma Enhanced OXide (PE-OX)) is deposited and the top layer is coated with SOG to form a gap fill (gapfill) process Proceed.

However, when P-TEOS oxide or Pe-OX oxide is applied as the lower layer of the SOG film, the step coverage is poor and the thickness of the upper and corners of the metal pattern is thick, but the thickness of the side and the lower part of the metal pattern is thin, resulting in poor profile. And it cannot be deposited to a low thickness, the subsequent SOG coating is poor in gap fill and flatness, and to overcome this requires a larger amount of SOG. Therefore, in this case, there is a problem in that the thickness of the SOG layer on the upper part of the metal pattern increases, resulting in poor profile after via formation.

Accordingly, it is an object of the present invention to provide a method for forming an insulating film of a semiconductor device by improving the flatness of the SOG coating on the metal pattern, thereby minimizing the SOG thickness on the metal pattern and forming a good via profile.

1A to 1J are cross-sectional views illustrating the formation of a metal pattern on a semiconductor substrate.

2 is a cross-sectional view illustrating that an ALD oxide film is deposited on a semiconductor substrate on which a metal pattern is formed.

3 is a cross-sectional view showing that the USG oxide film is deposited on the ALD oxide film.

4 is a cross-sectional view illustrating that an SOG insulating film is deposited on a USG oxide film.

5 is a cross-sectional view showing that an oxide film is deposited and a via hole is formed after the SOG insulating film is formed.

Explanation of symbols for main parts of the drawings

10 semiconductor substrate 12 trench

13: first SOG film 13a: first silicon oxide film

14 silicon oxide 16 gate oxide film

20: n-type well 22: photoresist pattern

24a: polysilicon pattern 24b: tungsten silicide pattern

24c: tungsten pattern 24d: silicon nitride pattern

24Ga, 24Gb, 24Gc: gate electrode 24GWL: word line

25: p-type impurity region 26, 27: n-type impurity region

30: p-type well 32: silicon nitride film

32a: spacer 40: n-type well

50: second SOG film 50a: second silicon oxide film

52 metal pattern 60 ALD oxide film

62 USG oxide film 64 SOG insulation film

66: oxide film 70: via hole

In order to achieve the above object of the present invention, the present invention comprises the steps of preparing a semiconductor substrate on which a metal pattern is formed, depositing ALD oxide on the semiconductor substrate on which the metal pattern is formed to form an ALD oxide film, on the ALD oxide film Forming an USG oxide film by depositing USG oxide, forming an SOG insulating film by coating SOG on the USG oxide film, and forming an oxide film by applying oxide on the SOG insulating film It provides a formation method.

According to the present invention, the ALD oxide and the USG oxide are sequentially deposited on the metal pattern and the SOG coating is applied on the metal pattern to facilitate the gap fill between the metal pattern and the metal pattern, thereby forming a structure having excellent flatness and forming a structure on the metal pattern. The via profile can be made good by minimizing the thickness of the SOG.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

1A to 1J are cross-sectional views illustrating a process of forming a metal pattern on a semiconductor substrate according to an embodiment of the present invention.

Referring to FIG. 1A, a p-type substrate 10 made of a semiconductor such as silicon (Si) is prepared. The trench 12 is formed by etching the device isolation region on the substrate 10. The first SOG film 13 is formed by applying an SOG solution on the substrate 10 on which the trench 12 is formed.

Referring to FIG. 1B, the first SOG film 13 is converted into the first silicon oxide film 13a by performing a preliminary baking process and a main baking process.

Next, referring to FIG. 1C, the obtained first silicon oxide film 13a is polished until exposed to the upper surface of the semiconductor substrate 10 by a chemical mechanical polishing method (CMP), as shown, An isolation region in which the inside of the trench 12 is filled with silicon oxide 14 is formed.

Referring to FIG. 1D, an n-type impurity, for example, phosphorus (P) is implanted into a semiconductor substrate 10 in a region (cell region) in which a memory cell is to be formed to form an n-type semiconductor region 20, and then a cell array P-type impurities, such as boron (B), are ion-implanted into the region and a portion of the peripheral circuit region to form the p-type well 30, and n-type impurities, such as phosphorus (P), in the remaining portion of the peripheral circuit region. ) Is implanted to form an n-type well 40. Next, impurities for adjusting the threshold voltage, such as BF ₂ (boron fluoride), are implanted into the p-type well 30 and the n-type well 40. Subsequently, each surface portion of the p-type well 30 and the n-type well 40 is cleaned using a hydrofluoric acid-based cleaning liquid, and then the semiconductor substrate 10 is wet oxidized to form the p-type well 30 and the n-type well ( A gate oxide film 16 is formed on each surface portion of 40. At this time, a part of the substrate on the inner surface portion of the trench 12 is also partially oxidized, so that the gate oxide film 16 is formed continuously.

Referring to FIG. 1E, doped with n-type impurities such as, for example, P (phosphorus) on the entire surface of the substrate 10 on which the silicon oxide 14 embedded in the trench 12 and the gate oxide film 16 are formed as the field oxide film. The polycrystalline silicon film is deposited by low pressure chemical vapor deposition (LPCVD) to form a polysilicon film. Subsequently, a tungsten silicide film and a tungsten film are deposited on the polysilicon film by a sputtering method, and then a silicon nitride film is laminated on the tungsten film. The silicon nitride film is formed using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

After the photoresist film is formed on the silicon nitride film, the photoresist film is selectively exposed using a mask. Next, the photoresist film is developed to form a photoresist pattern 22 for forming a gate electrode. Using the photoresist pattern 22 as an etching mask, the silicon nitride film, tungsten film, tungsten nitride film and polysilicon film are sequentially etched to form a polysilicon pattern 24a, a tungsten silicide pattern 24b, and a tungsten pattern 24c. ) And gate electrodes 24Ga, 24Gb, 24Gc, and 24GWL formed of a silicon nitride pattern 24d. Then, as illustrated, gate electrodes 24Ga and word lines 24GWL are formed in the cell array region, and gate electrodes 24Gb and 24Gc are formed in the peripheral circuit region, respectively.

The gate electrodes 24Ga and 24GWL formed in the cell array region form dense stepped portions having an aspect ratio of 5: 1 to 10: 1, which is a ratio of the height to the gap of the gate electrodes 24Ga and 24GWL. The gate electrodes 24Gb and 24Gc formed in the circuit region form a global stepped portion whose aspect ratio, which is the ratio of the height to the gap between the gate electrodes, is 1: 1 or less.

Referring to FIG. 1F, p-type impurities such as boron are ion-implanted into the n-type well 20 to form the p-type impurity region 25 in the n-type well 40 on both sides of the gate electrode 24Gc. do. Further, an n-type impurity, for example phosphorus, is ion-implanted into the p-type well 30 to form the n-type impurity region 27 in the p-type well 30 on both sides of the gate electrode 24Gb. N-type impurity regions 26 are formed in the p-type wells 20 on both sides of 24Ga).

Referring to FIG. 1G, a silicon nitride film 32 is formed by depositing silicon nitride on the semiconductor substrate 10 by vapor deposition. Next, the silicon nitride film 32 of the cell array region is covered with a photoresist film, and the silicon nitride film 32 of the peripheral circuit is anisotropically etched so that the sidewalls of the gate electrodes 24Gb and 24Gc of the peripheral circuit are spacer 32a. To form.

Next, p-type impurities, such as boron, are ion-implanted into the n-type well 40 of the peripheral circuit to form p + type impurity regions (source and drain regions). In addition, n-type impurities such as arsenic (As) are ion-implanted into the p-type well 30 of the peripheral circuit to form n + type impurity regions (source and drain regions).

Referring to FIG. 1H, the SOG solution is coated on the semiconductor substrate 10 to form a second SOG film 50. The second SOG film 50 is formed to completely cover the gate electrodes 24Ga, 24Gb, 24Gc, and 24GWL in a spin coating method. Next, the second SOG film 50 is prebaked, and then main baked to form a silicon oxide film. Through this process, as shown in FIG. 1I, a second silicon oxide film 50a is obtained in which the thickness is about 19 to 20% contracted.

Referring to FIG. 1J, a metal layer is formed by depositing a metal such as aluminum or tungsten on the second silicon oxide film 50a by a conventional sputtering method. The metal layer is patterned by photolithography to form metal patterns 52.

2 is a cross-sectional view illustrating a method of forming an ALD oxide film 60 by depositing ALD oxide on a semiconductor substrate on which a metal pattern 52 manufactured by the method shown in FIGS. 1A to 1J is formed.

ALD is a thin film deposition technique using chemisorption and desorption of a monoatomic layer. Each reactant is individually separated and supplied to the chamber in the form of a pulse to use chemical adsorption and desorption by surface saturation of the reactant on the substrate surface.

Compared to conventional chemical vapor deposition (CVD), ALD is easy to precisely control the composition of the thin film, there is no particle generation, excellent uniformity when depositing large-area thin film, and it is easy to precisely adjust the film thickness. It contains less impurities in the thin film and has excellent step coverage. After the metal pattern 52 is formed, the lower film of the SOG insulating film 64 used as a gapfill material between the metal pattern 52 and the metal pattern 52 is a USG oxide having excellent step coverage but having a lower film dependency. In order to remove the film dependency of the USG oxide underneath the USG oxide without being deposited immediately, it is first deposited with ALD oxide having good step coverage but poor throughput per unit time. As described above, in the ALD deposition method, the thin film to be deposited has advantages such as fine control of atomic units, excellent step coverage, minimization of impurities in the deposited thin film, and excellent insulating properties, but poor throughput.

The ALD oxide is deposited by selecting from Al ₂ O ₃ or SiO ₂ . Since Al ₂ O ₃ and SiO ₂ have low dielectric constants, they may serve as insulating films. Specifically, the gaseous reactant AXn (g) is transferred to the surface of the material to be coated with the thin film. The delivered reactant AXn (g) is adsorbed to the surface by chemisorption and is deposited by physical adsorption on the chemical adsorbate. Subsequently, when AXn is physically adsorbed by a purging process, only AXn (s) in a chemically adsorbed solid state remains. Therefore, the monoatomic layer has a thickness. Here, Xn means a chemical ligand formed of n groups. Subsequently, when water vapor, such as H ₂ O, is delivered to the surface of the material coated with AXn (s), A is oxidized to form AO on the surface, and the Xn group reacts with the H group to remove HXn (g). Subsequently, when residual impurities are removed by a purging process, only an oxide film having a thickness of a monoatomic layer of AO (s) in a chemically adsorbed solid state remains.

Hereinafter, a method of depositing Al ₂ O ₃ will be described in detail. Trimethyl aluminum (Al (CH ₃ ) ₃ ; TMA) consisting of a thin film of aluminum and a methyl ligand is injected into a reaction chamber loaded with a metal patterned substrate. Subsequently, the TMA which has a physical bond is removed by purging an inert gas. As a result, the TMA is chemisorbed onto the semiconductor substrate on which the metal pattern is formed. Subsequently, water (H ₂ O) composed of oxygen and hydrogen radicals forming a thin film is injected into the TMA chemisorbed reaction chamber. In this case, the water vapor is chemically adsorbed to the TMA. Here, the hydrogen radicals of the chemisorbed water vapor move to the methyl ligand of the TMA to separate the methyl ligand from the TMA. Then, as shown in the following Chemical Formula 1, the hydrogen radical of the transferred steam reacts with the methyl ligand of the separated TMA to form a volatile gaseous substance consisting of CH ₄ . On the semiconductor substrate, an aluminum oxide film is formed by reaction of aluminum of TMA and oxygen of the water vapor.

2Al (CH ₃ ) ₃ + 3H ₂ O → Al ₂ O ₃ + 6CH ₄ --- Formula 1

Next, the volatile gaseous substance consisting of CH ₄ and unreacted water vapor are removed by purging an inert gas. Then, the above-described process is repeated as necessary.

The thickness of the ALD oxide film 60 formed at this time is about 10 to 150 kPa. Forming the thickness of the ALD oxide film 60 to less than or equal to 10 μs is difficult to implement in practice, and if it exceeds 150 μs, there is a problem that it is ineffective in consideration of the recent reduction in design rules due to high integration. .

Referring to FIG. 3, after the ALD oxide layer 60 is formed, USG oxide is deposited to form the USG oxide layer 62.

The USG film is an interlayer insulating film capable of realizing excellent flatness that can solve the increase in the level difference caused by the high integration of the semiconductor device. Of these USG films, in particular, an oxide film (hereinafter referred to as TEOS film) formed by using TEOS (Tetra Ethyl Ortho Silicate) has attracted attention. The TEOS film is formed mainly by reaction of ozone and TEOS. Such a TEOS film can obtain excellent flatness compared to the oxide film formed by exciting SiH ₄ in a plasma state to react.

However, the TEOS film has under layer dependence such as the deposition rate decreases and the roughness increases depending on the film quality of the underlayer. That is, when the underlying film is a hydrophilic high temperature oxide or thermal oxide film, and the TEOS film is formed on the hydrophilic undercoat, the surface of the TEOS film is very rough due to its opposing characteristics, and the target thickness is also the target thickness. It is difficult to apply to the actual device because it is not. Therefore, the present invention can overcome the disadvantages of the USG film by depositing ALD oxide under the USG oxide film 62 first.

The USG oxide layer 62 of the present invention loads a semiconductor substrate on which the ALD oxide layer 60 is formed into a reaction chamber, and reacts at a high temperature by using O ₃ and TEOS as a source gas on the entire surface of the semiconductor substrate to form a TEOS film. do. In this case, in order to smoothly flow the O ₃ and the TEOS into the reaction chamber, the O ₃ gas and the TEOS gas are preferably introduced into the reaction chamber together with the carrier gas. At this time, the carrier gas is preferably nitrogen gas.

In this case, the thickness of the USG oxide film 62 is preferably about 50 to 400 Pa. Forming the thickness of the USG oxide film 62 to 50 GPa or less is difficult to implement in practice, and when it exceeds 400 GPa, the design rule and thus the distance between the metal and the metal are reduced according to high integration. Considering this, there is a problem ineffectiveness.

Referring to FIG. 4, after forming the USG oxide layer 62, an SOG insulating layer 64 is formed by coating SOG on the USG oxide layer 62. At this time, SOG plays a role of gap filling between metal pattern and metal pattern, and has excellent planarization property that can fill narrow space more smoothly than CVD type interlayer insulating film without forming voids. There are advantages such as simplicity, low defect density, relatively low cost and no use of harmful gases.

Instead of directly depositing SOG on the metal, the ALD oxide layer 60 and the USG oxide layer 62 are first deposited as the lower layer of the SOG insulating layer 64 to form a vertical structure to easily form a gap fill during SOG coating. And excellent flatness.

Specifically, the SOG is laminated on the substrate by a coating method, and when the SOG film is applied, soft baking is performed at a low temperature of about 100 to 300 ° C. to remove the solvent component, and the hard bake is about 400 ° C. according to the kind of the film to complete the film. Alternatively, a bake of about 400 ° C. and annealing of 700 ° C. or more may be used to remove the unstable components in the SOG film and to stabilize and stabilize the structure.

In this case, the SOG insulating layer 64 may be formed of inorganic SOG, such as polysilazane, HSQ (Hydro Silses Quioxane), or silicate, or methyl silses quoxane (MSQ), such as siloxane. Organic SOG is possible.

Referring to FIG. 5, an oxide film 66 is formed on the SOG to form an inter metallic dielectric.

In this case, silicon oxide (SiO ₂ ) silicon oxide fluoride (SiOF) or the like may be used as the oxide layer 66. The oxide layer 66 may include a thermal oxide layer and / or a plasma oxide layer. Here, the thermal oxide film is to form an oxide film using the thermal oxidation method, and the plasma oxide film is to deposit silicon oxide by plasma chemical vapor deposition. When forming the oxide film, the reaction gas containing ozone gas may be flowed to have a good step coverage and to form a flat surface.

In this way, it can be seen that the SOG thickness of the upper portion of the metal where the via holes 70 are formed can be minimized, thereby making the via profile good.

According to the present invention, it is possible to form an insulating film of a semiconductor device having a good via profile since the gap fill is easily and excellent in SOG coating, and the SOG thickness of the upper portion of the metal where the via hole is formed can be minimized.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (5)

Preparing a semiconductor substrate on which a metal pattern is formed; Depositing an atomic layer deposition oxide on the semiconductor substrate on which the metal pattern is formed to form an atomic layer deposition oxide film; Depositing an undoped silicate glass oxide on the atomic layer deposition oxide film to form an undoped silicate glass oxide film; Coating a spin on glass on the undoped silicate glass oxide film to form a spin on glass insulating film; And And forming an oxide film by applying an oxide on the spin-on glass insulating film. The method of claim 1, wherein the atomic layer deposition oxide is Al ₂ O ₃ or SiO ₂ . The method of forming an insulating film of a semiconductor device according to claim 1, wherein the atomic layer deposited oxide film has a thickness of 10 to 150 GPa. The method of claim 1, wherein the undoped silicate glass oxide is prepared using Tetra Ethyl Ortho Silicate (TEOS) and O ₃ . The method for forming an insulating film of a semiconductor device according to claim 1, wherein the undoped silicate glass oxide film has a thickness of 50 to 400 GPa.