KR20030059483A - Method for reliefing failures in semiconductor memory device and semiconductor memory device using thereof - Google Patents

Abstract

In order to utilize a semiconductor memory device without discarding a plurality of bits in the post-package step due to the concentration of a specific cell block region,

By programming the address using a programmable fuse on the address path of the defective cell, the remaining cells except the defective cell are utilized.

Description

METHODS FOR RELIEFING FAILURES IN SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect repair method of a semiconductor memory device and a semiconductor memory device using the same. In particular, an address of a cell block group to which a corresponding memory cell belongs by using a programmable fuse on an address path of a memory cell having a large number of defects in a post-package step. The present invention relates to a defect repair method of a semiconductor memory device utilizing the remaining memory cells except a memory cell block to which a defective cell belongs, and a semiconductor memory device using the same.

According to the prior art, when a defect occurs in a memory cell of a semiconductor memory device, spare rows and columns are provided in advance for every 256k cell array, and the defective / defective memory cells are arranged in rows / columns. A method of replacing a spare memory cell with a unit, a so-called redundancy method, is used.

That is, after completion of the wafer process, the internal circuit is programmed to select the defective cell and convert the corresponding address into the address signal of the spare cell, so that the spare line is selected when an address corresponding to the defective line is input in actual use. do.

According to the prior art, when a plurality of defects occur in a memory cell having a redundancy or larger number of redundancy cells in a post-package step, such as a burn-in test, the defects cannot be repaired and the entire memory device must be discarded. Lowered.

In order to solve this problem, the number of redundancy cells can be increased, but this also has the problem of increasing the size of the chip size more than necessary.

An object of the present invention is to partially use the semiconductor memory device without discarding even when a plurality of defects occur in the memory cell block in the post-package step.

1 is a schematic block diagram illustrating a portion of a semiconductor memory device in order to explain a defect repair method according to an embodiment of the present invention.

2 is a schematic block diagram illustrating a portion of a semiconductor memory device in order to explain a defect repair method according to another exemplary embodiment of the present invention.

3 is a block diagram illustrating an address bit programming unit according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a coding unit and an output selector according to an embodiment of the present invention shown in FIG.

<Description of Symbols for Main Parts of Drawings>

10: row address buffer 20: predecoder

30: main decoder 50: first programmable fuse

60: second programmable fuse unit 70: coding unit

80: output selector ADDR [n]: address bit

PADDR [n]: programmed address bits

In accordance with an aspect of the present invention, a semiconductor memory device may include: at least one programmable fuse unit configured to externally program a 0 or 1 programmed bit signal; An output selector for selecting and outputting one of a corresponding address bit, a high level voltage, or a low level voltage as a programmed address bit; And a coding unit configured to code one or more programmed bit signals output from the one or more programmable fuse units, and output a plurality of control signals for controlling the output of the output selection unit on the address path.

In addition, the one or more programmable fuses may include a first programmable fuse and a second programmable fuse.

The coding unit may further include a first control signal for outputting a high level voltage, a second control signal for outputting a corresponding address bit, and a low level based on a first programmed bit signal and a second programmed bit signal. A third control signal for outputting a voltage may be output.

The second control signal of the coding unit may be a signal obtained by performing a NOR operation on the first programmed bit signal and the second programmed bit signal.

The output selector may include a first transfer unit configured to transfer a high level voltage based on the first control signal; A second transfer unit transferring a corresponding address bit based on the second control signal; And a third transfer unit configured to transfer a low level voltage based on the third control signal.

The output selector may be a 3: 1 multiplexer for selectively outputting one of a high level voltage, a corresponding address bit, or a low level voltage based on the first to third control signals.

In addition, an address bit programming unit may be included on the refresh address path.

According to another aspect of the present invention, there is provided a defect repairing method of a semiconductor memory device, the method comprising: dividing a memory cell block into a plurality of groups according to an input address; Programming some bits of the row address on the address path, thereby making some groups of the plurality of cell block groups unavailable; And using only the remaining available group of the plurality of cell block groups.

Also, some bits of the address are the most significant bits of the address, and the cell block group set to be unavailable may be 1/2 of the entire cell block.

In addition, some bits of the address are the most significant two bits of the address, and the cell block group set to be unavailable may be one quarter of all cell blocks.

In addition, by programming some bits of the refresh address on the refresh address path, the method may further include refraining from performing a refresh on some groups that are not available.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a portion of a semiconductor memory device in order to explain a defect repair method according to an embodiment of the present invention.

The row address ADDR input from the outside is converted into a CMOS level signal inside the semiconductor memory device in the row address buffer 10 and output to the internal address An. The internal address An is decoded through the predecoder 20 and the main decoder 30 and then determined whether to drive the word lines Ci, Di, Ei, Fi, where i is an integer of 1 or more. Done.

As shown, the cell blocks in the memory bank or in the entire chip may be divided into several groups by the row address bits ADDR [n]. 1 and 2, the cell blocks are divided into four groups of equal numbers using the most significant two bits of the row address ADDR. For example, in the case of 256M cells, it may be divided into four 64M cell block groups. When the most significant two bits of the row address ADDR are 00, the first cell block group CB1 is 01, when the second cell block group CB2 is 10, and when the 10th third cell block group CB3 is 11, In this case, the fourth cell block group CB4 may be selected.

As shown in FIG. 1, assuming that defects are generated by concentrating on the third cell block group CB3, the first cell block group CB1 is programmed by programming the most significant bit of the row address ADDR to '0', for example. ) And the second cell block group CB2 may be set to be unavailable, and the third cell block group CB3 and the fourth cell block group CB4 may be set to be unavailable.

By specifying the number of bits of the programmable row address ADDR, the resolution specifying the group of unavailable cell blocks can be adjusted.

As shown in FIG. 2, by programming the most significant two bits of the row address ADDR, the first cell block group CB1, the second cell block group CB2, and the fourth cell block group CB4 are available. For example, the third cell block group CB3 may be set to be unavailable. It will be apparent to those skilled in the art that, by programming the most significant three bits of the row address ADDR, an unavailable cell block can be specified in units of one eighth.

In order to program some of these address bits ADDR, the address bit programming unit 100 of FIG. 3 may be included in an address path, for example, in each address bit output terminal after the row address buffer 10.

As shown in FIG. 3, the address bit programming unit 100 according to the present invention includes a corresponding address bit (ADDR [n], n is an integer of 1 or more), a high level voltage (eg, Vdd), or a low level voltage. An output selector 80 for selecting and outputting one of (eg, Vss); A coding unit 70 for outputting control signals CTRL1 to CTRL3 for controlling the output selection unit 80; And one or more programmable fuses 50 and 60 configured to be externally programmable to provide a bit of '0' or '1' to the coding unit 70.

The programmable fuses 50 and 60 may include, for example, an electric fuse for disconnecting the fuse due to overcurrent, a method for disconnecting the fuse with a laser beam, a method for shorting a junction with a laser beam, The present invention may be configured in various ways such as programming with EPROM memory cells, and the present invention is not limited thereto.

The results FUS1 and FUS2 programmed from the programmable fuse units 50 and 60 are input to the coding unit 70, and the coding unit 70 controls the control signals CTRL1 to CTRL3 for controlling the output selector 80. Outputs

The output selector 80 uses a corresponding address bit ADDR [n], a high level voltage (e.g., Vdd), or a low level voltage (e.g., by the control signals CTRL1 to CTRL3 from the coding unit 70). Vss) selects one of the outputs, and may be configured as, for example, a 3: 1 multiplexer.

4 shows a coding unit 70 and an output selecting unit 80 according to an embodiment of the present invention.

The coding section 70 is programmed logic '0' from the first programmable fuse section 50 or the first program bit FUS1 of logic '1' and the programmed logic 'from the second programmable fuse section 60'. The control signals CTRL1 to CTRL3 for controlling the output selector 80 are output based on the second program bit FUS2 of '0' or '1'. For example, as shown in FIG. 4, the first control signal CTRL1 is the first program bit FUS1 from the first programmable fuse unit 50, and the second control signal CTRL3 is the first programmable fuse unit. NOR operation is performed on the first programmed bit signal FUS1 from 50 and the second programmed bit signal FUS2 from the second programmable fuse 60, and the third control signal CTRL3 It may be a second programmed bit signal FUS2 from the two programmable fuses 60.

The output selector 80 outputs the high level Vdd voltage according to the first control signal CTRL1 and the corresponding address bit ADDR [n] according to the second control signal CTRL2. The second transmission gate (TG2) for outputting a) and the third transmission gate (TG3) for outputting a low level voltage (Vss) in accordance with the third control signal (CTRL3) is connected in parallel.

Therefore, based on the programming of the first and second programmable fuse units 50 and 60, the corresponding address bits ADDR [n], high level voltage Vdd, or low level voltage from the address bit program unit 100. One of (Vss) is output as the programmed address bit (PADDR [n]).

For example, when 0 is programmed in the first programmable fuse unit 50 and 0 in the second programmable fuse unit 60, the first transmission gate TG1 and the third transmission gate TG3 are disabled and the second The transmission gate TG2 is enabled and the corresponding address bit ADDR [n] is output.

When programmed as 0 in the first programmable fuse unit 50 and 1 in the second programmable fuse unit 60, the first transmission gate TG1 and the second transmission gate TG2 are disabled, and the third transmission gate TG3 is enabled to output a low level voltage Vss.

When programmed as 1 in the first programmable fuse unit 50 and 0 in the second programmable fuse unit 60, the second transmission gate TG2 and the third transmission gate TG3 are disabled and the first transmission gate is disabled. TG1 is enabled to output a high level voltage Vdd.

According to an embodiment of the present invention, the above-described address bit programming unit 100 programs the row address most significant bit ADDR [of the row address buffer 10 so that the most significant bit ADDR [n] of the row address ADDR is programmed. n]). Therefore, as shown in FIG. 1, half (CB1, CB2) including defective cells of the entire memory cell block are available, and half (CB3, CB4) including no defective cells are not available. do. For example, 128M memory cells become available for 256M DRAM.

According to another embodiment of the present invention, a row of a row address buffer such that the above-described address bit programming unit 100 programs the most significant two bits ADDR [n] and ADDR [n-1] of the row address bit ADDR. The two most significant bits ADDR [n] and ADDR [n-1] of the address bit ADDR may be included in the output terminal. Therefore, as shown in FIG. 2, only 1/4 (CB3) including defective cells in the entire memory cell block may be unavailable, and the remaining 3/4 (CB1, CB2, CB4) may be set to be available. .

That is, as the number of address bit programming units 100 according to an embodiment of the present invention increases, the number of cell block groups that are masked to be unusable also increases, so that masking may be performed more precisely. Therefore, the number of address bit programming units 100 according to an embodiment of the present invention may be appropriately adopted in consideration of the overall chip size and economic efficiency.

The above-described address bit programming unit 100 may be included in an output terminal of a refresh counter (not shown). That is, the refresh address TCTR [n] may be programmed in the refresh mode to enable the refresh operation only in the usable cell blocks CB1, CB2, and CB4 programmed as described above. Thus, the refresh operation cycle can be reduced, and the refresh current can be reduced by the number of cell blocks that are programmed to be unusable.

It will be apparent to those skilled in the art that the address bit programming section 100 of the present invention may be configured to program the enable / disable of the word line anywhere on the address path, for example, at the output of the predecoder.

According to the present invention, by programming the address bits to make the cell block group in which a plurality of defects occur have become unusable, it is possible to partially utilize the semiconductor memory device in which a plurality of defects occur. Therefore, the yield can be improved.

In addition, refresh cycles and refresh current consumption can be reduced by programming refresh addresses.

Claims (11)

One or more programmable fuse means for externally programming and outputting a programmed bit signal of logic 0 or logic 1; Output selecting means for selecting and outputting one of a corresponding address bit, a high level voltage, or a low level voltage as a programmed address bit; And Coding address bit programming means on an address path, the address bit programming means having a coding means for coding one or more programmed bit signals output from said at least one programmable fuse means and outputting a plurality of control signals for controlling output selection of said output selection means; The semiconductor memory device, characterized in that included in. The method of claim 1, The at least one programmable fuse means, First programmable fuse means for outputting a first programmed bit signal; And And a second programmable fuse means for outputting a second programmed bit signal. The method of claim 2, The coding means includes a first control signal for outputting the high level voltage, a second control signal for outputting the corresponding address bit, based on the first programmed bit signal and the second programmed bit signal; And outputting a third control signal for outputting the low level voltage. The method of claim 3, wherein And the second control signal of the coding means is a signal obtained by performing a NOR operation on the first programmed bit signal and the second programmed bit signal. The method of claim 3, wherein The output selection means may include first transmission means for transmitting the high level voltage based on the first control signal; Second transfer means for transferring the corresponding address bit based on the second control signal; And And third transmission means for transmitting the low level voltage based on the third control signal, wherein the third transmission means is provided from any one of the first transmission means and the third transmission means by the control of the first to third control signals. And selectively outputting a voltage. The method of claim 3, wherein And the output selection means is a 3: 1 multiplexer for selectively outputting one of the high level voltage, the corresponding address bit, or the low level voltage based on the first to third control signals. Memory device. The method according to any one of claims 1 to 6, And the address bit programming means is included on a refresh address path. Dividing the memory cell block into a plurality of groups according to an input address; Setting some of the plurality of cell block groups to be unavailable by programming some bits of the address on the address path; And And using only the remaining usable group of the plurality of cell block groups. The method of claim 8, And some of the bits of the address are the most significant bits of the address, and the cell block group set to be unavailable is 1/2 of all cell blocks. The method of claim 8, And some of the bits of the address are the most significant two bits of the address, and the cell block group set to be unavailable is one quarter of all cell blocks. The method according to any one of claims 8 to 10, And reprogramming some bits of the refresh address corresponding to the programmed address bits on the refresh address path so as not to perform a refresh on the some groups that are set to be unavailable. Defect Remedy.