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KR20030021378A - Metnod for manufacturing liquid crystal display panel - Google Patents

Metnod for manufacturing liquid crystal display panel Download PDF

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KR20030021378A
KR20030021378A KR1020010054516A KR20010054516A KR20030021378A KR 20030021378 A KR20030021378 A KR 20030021378A KR 1020010054516 A KR1020010054516 A KR 1020010054516A KR 20010054516 A KR20010054516 A KR 20010054516A KR 20030021378 A KR20030021378 A KR 20030021378A
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film
insulating film
forming
ito thin
organic insulating
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박재철
이호년
임승무
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주식회사 현대 디스플레이 테크놀로지
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00Manufacture or treatment of devices covered by this subclass
    • H10F71/138Manufacture of transparent electrodes, e.g. transparent conductive oxides [TCO] or indium tin oxide [ITO] electrodes
    • H10F71/1385Etching transparent electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 유기절연막상에 화소전극 증착시 식각 특성을 향상시킬 수 있는 액정표시소자의 패널 제조방법에 관한 것으로, 절연 기판상에 게이트 전극을 형성하는 단계와, 상기 게이트 전극을 포함한 기판 전면에 게이트 절연막을 형성하고, 상기 게이트 절연막상에 활성층을 형성하는 단계와, 상기 활성층을 포함한 게이트 절연막상에 소오스/드레인 전극 및 채널층을 형성하는 단계와, 상기 소오스/드레인 전극상을 포함한 기판 전면에 상기 소오스/드레인 전극중 어느 하나가 노출되도록 콘택홀을 갖는 보호막을 형성하는 단계와, 상기 보호막상에 유기절연막을 증착하여 상기 보호막과 같이 유기절연막을 패터닝하고, 열처리한 후, UV 세정과 SF6가스를 이용하여 플라즈마 처리하는 단계와, 상기 플라즈마 처리된 유기절연막상에 아리곤 가스를 이용하여 제 1 ITO 박막을 증착하는 단계와, 상기 플라즈마 처리된 유기절연막 및 제 1 ITO 박막상에 아르곤과 산소혼합 가스를 이용하여 제 2 ITO 박막을 증착하는 단계와, 상기 제 1, 제 2 ITO 박막을 선택적으로 제거하여 상기 소오스/드레인 전극중 어느 하나와 콘택되는 화소전극을 형성하는 단계를 포함한다.The present invention relates to a method for manufacturing a panel of a liquid crystal display device capable of improving etching characteristics when a pixel electrode is deposited on an organic insulating layer, the method comprising: forming a gate electrode on an insulating substrate; Forming an insulating film, forming an active layer on the gate insulating film, forming a source / drain electrode and a channel layer on the gate insulating film including the active layer, and forming the insulating layer on the entire surface of the substrate including the source / drain electrode. Forming a protective film having a contact hole so that any one of the source / drain electrodes is exposed, depositing an organic insulating film on the protective film, patterning the organic insulating film like the protective film, and performing heat treatment, followed by UV cleaning and SF 6 gas. Plasma treatment using Ar, and argon gas on the plasma-treated organic insulating layer Depositing a first ITO thin film, depositing a second ITO thin film using argon and an oxygen mixed gas on the plasma treated organic insulating film and the first ITO thin film, and the first and second ITO thin films. And selectively removing a to form a pixel electrode in contact with any one of the source / drain electrodes.

Description

액정표시소자의 패널 제조방법{METNOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY PANEL}Panel manufacturing method of liquid crystal display device {METNOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY PANEL}

본 발명은 액정표시소자의 패널 제조방법에 관한 것으로, 특히 유기절연막상에 화소전극 증착시 식각 특성을 향상시킬 수 있는 액정표시소자의 패널 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a panel of a liquid crystal display device, and more particularly, to a method of manufacturing a panel of a liquid crystal display device capable of improving etching characteristics when a pixel electrode is deposited on an organic insulating layer.

일반적으로 평판표시장치(Flat Panel Display)의 일종인 LCD(Liquid Crystal Display)는 액체의 유동성과 결정의 광학적 성질을 겸비하는 액정에 전계를 인가하여 광학적 이방성을 변화시켜 얻어지는 명암의 차이로 화상을 얻는 장치이다.In general, liquid crystal displays (LCDs), which are a type of flat panel display, obtain an image with a difference in contrast obtained by changing an optical anisotropy by applying an electric field to a liquid crystal having both liquidity and optical properties of a crystal. Device.

그리고 사용되는 액정의 종류에 따라 TN(Twisted Nematic), STN(Super TN), 강유전성(Ferro electric) LCD 등으로 나누어지고, 화소의 스위칭 소자인 TFT를 각 화소마다 내장하는 TFT LCD 등이 사용되고 있다.According to the type of liquid crystal used, TN (Twisted Nematic), STN (Super TN), Ferroelectric (LCD), etc. are divided into TFT LCDs, etc., in which TFTs, which are switching elements of pixels, are incorporated for each pixel.

또한, 화면을 수만에서 수십만개로 분할하여 각 화소에 구동소자를 제작하고 스위칭 특성을 이용하여 화소의 동작을 제어하는 방식의 AMLCD 등이 사용되고 있다.In addition, AMLCD and the like are used in which a driving device is manufactured for each pixel by dividing the screen into tens of thousands and hundreds of thousands, and the operation of the pixel is controlled using switching characteristics.

이러한 LCD는 종래 음극선관(Cathode Ray Tube)에 비해 소비전력이 낮고, 경박단소화가 용이하며 칼라화, 대형화 및 고정세화가 가능하여 차츰 사용 범위가 넓어지고 있으며, 최근에는 액정의 응답속도가 빠르고 고화질화에 유리한 TFT-LCD가 주목받고 있다.These LCDs have lower power consumption, easier light weight and shorter size than conventional cathode ray tubes, and can be used in color, large size, and high resolution, and are gradually expanding their range of use. Advantageous TFT-LCDs have attracted attention.

또한, 노트북 컴퓨터에 주로 사용되는 TFT LCD의 전력 소모량은 매우 중요하다. 즉, 전력소모가 적으면 노트북 컴퓨터의 충전지 용량이 작아도 되므로 경량화, 소형화를 이룰 수 있기 때문에 생산원가절감 등에 크게 기여할 수 있고, 같은 충전량일 경우에 더 오랜 시간을 사용할 수 있는 장점이 있다. 이러한 저소비 전력화를 달성하기 위한 핵심기술요소로서 백라이트의 고효율화, 구동회로의 저소비전력화,픽셀전극의 고개구율화로 요약할 수 있다.In addition, the power consumption of the TFT LCD mainly used in notebook computers is very important. In other words, if the power consumption is small, the battery capacity of the notebook computer can be small, so that the weight and size can be reduced, which can greatly contribute to production cost reduction, and the same amount of charge can be used for a longer time. Key technologies for achieving such low power consumption can be summarized as high efficiency of backlight, low power consumption of driving circuit, and high opening ratio of pixel electrode.

이러한 관점에서, 종래기술에 따른 액정표시장치의 패널 제조방법을 도 1을 참조하여 설명하면 다음과 같다.In this regard, a panel manufacturing method of a liquid crystal display according to the related art will be described with reference to FIG. 1.

도 1은 종래의 화소전극이 패너닝된 모양을 나타내는 광학 현미경 사진이다.종래기술에 따른 액정표시장치의 패널 제조방법은, 도면에는 도시하지 않았지만, 종래의 픽셀전극 고개구율화를 위해 유리기판상에 제 1 마스크를 이용하여 게이트 전극을 형성한 후, 기판 전면에 게이트 절연막을 형성한다.FIG. 1 is an optical micrograph showing a conventional pixel electrode panning. A method of manufacturing a panel of a liquid crystal display device according to the prior art, although not shown in the drawing, is provided on a glass substrate for high aperture ratio of the conventional pixel electrode. After the gate electrode is formed using one mask, a gate insulating film is formed over the entire substrate.

그다음, 상기 게이트 절연막상에 제 2 마스크를 이용하여 활성층을 형성하고, 상기 활성층을 포함한 게이트 절연막상에 제 3 마스크를 이용하여 소오스/드레인 전극 및 채널층을 형성한다.Next, an active layer is formed on the gate insulating film using a second mask, and a source / drain electrode and a channel layer are formed on the gate insulating film including the active layer using a third mask.

이어서, 상기 소오스/드레인 전극상을 포함한 기판 전면에 보호막을 형성하고, 상기 보호막상에 유기절연막을 증착한 후, 제 4 마스크를 이용하여 상기 소오스/드레인 전극중 어느 하나가 노출되도록 콘택홀을 형성한다.Subsequently, a protective film is formed on the entire surface of the substrate including the source / drain electrodes, an organic insulating film is deposited on the protective film, and a contact hole is formed to expose any one of the source / drain electrodes using a fourth mask. do.

그다음, 상기 유기절연막에 열처리한 후, UV 세정을 실시하고, SF6가스를 이용하여 플라즈마 처리한 후, 아르곤과 산소의 혼합가스를 이용하여 상기 유기절연막상에 ITO 박막을 증착한다.Thereafter, the organic insulating film is heat-treated, followed by UV cleaning, plasma treatment using SF 6 gas, and then an ITO thin film is deposited on the organic insulating film using a mixed gas of argon and oxygen.

그리고 제 5 마스크를 이용하여 상기 ITO 박막을 선택적으로 제거하여 상기 소오스/드레인 전극중 어느 하나와 콘택되는 화소전극을 형성한다.The ITO thin film is selectively removed using a fifth mask to form a pixel electrode contacting any one of the source / drain electrodes.

도 1은 종래의 화소전극이 패너닝된 모양을 나타내는 광학 현미경 사진이다.1 is an optical micrograph showing a state in which a conventional pixel electrode is panned.

그러나, 상기와 같은 종래기술의 저소비전력화를 위한 픽셀전극의 고개구율화에 있어서는 레진(Resin)이라는 유기절연물 위에 화소전극으로 이용되는 ITO 박막을 증착하여 식각하면 매우 상이한 특성을 가지고 있는 두 층간 계면 특성으로 인해 화소전극이 벗겨지거나, 들뜨거나 또는 화소전극간의 선폭 값이 매우 불균일하게 다량의 화소결함 및 빛이 새는 현상이 발생하는 문제점이 있다.However, in the high aperture ratio of the pixel electrode for the low power consumption of the prior art as described above, when an ITO thin film used as a pixel electrode is deposited and etched on an organic insulator called resin, it has a very different interface property between two layers. Due to this, there is a problem that a large amount of pixel defects and light leaks occur when the pixel electrode is peeled off, raised, or the line width value between the pixel electrodes is very uneven.

즉, 유기절연막상에 ITO 박막을 증착할 때 비정질층의 ITO 박막이 먼저 형성된 다음 그 상부에 결정질층의 ITO 박막이 형성되기 때문에 화소전극 식각시 결정질의 상부층이 식각된 후, 하부층이 식각될 대 식각속도가 너무 빨라서 상부층은 그대로 남아있는 상태에서 하부층만 식각되어 ITO 박막이 벗겨지거나, 들뜨거나 또는 불균일한 선폭값이 나타난다.That is, when the ITO thin film is deposited on the organic insulating layer, the ITO thin film of the amorphous layer is formed first, and then the crystalline layer of ITO thin film is formed thereon, so that when the crystalline upper layer is etched when the pixel electrode is etched, the lower layer is etched. The etching rate is so fast that only the lower layer is etched while the upper layer remains intact, resulting in peeling, lifting, or non-uniform linewidth values.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로, 화소전극의 고개구율화를 위해 유기절연막상에 화소전극으로 사용되는 ITO 박막 증착시 산소농도를 조절하여 식각특성을 향상시킬 수 있는 액정표시소자의 패널 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, it is possible to improve the etching characteristics by adjusting the oxygen concentration during the deposition of the ITO thin film used as the pixel electrode on the organic insulating film for the high aperture ratio of the pixel electrode It is an object of the present invention to provide a method for manufacturing a panel of a liquid crystal display device.

도 1은 종래의 화소전극이 패너닝된 모양을 나타내는 광학 현미경 사진1 is an optical micrograph showing a state in which a conventional pixel electrode is panned.

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 액정표시소자의 패널 제조방법을 나타낸 공정 단면도2A through 2E are cross-sectional views illustrating a method of manufacturing a panel of a liquid crystal display device according to an exemplary embodiment of the present invention.

도 3은 본 발명의 화소전극이 패너닝된 모양을 나타내는 광학 현미경 사진3 is an optical microscope photograph showing a pattern in which the pixel electrode of the present invention is panned.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode

13 : 게이트 절연막 14 : 활성층13 gate insulating film 14 active layer

15 : 채널층 16 : 소오스/드레인 전극15 channel layer 16 source / drain electrodes

17 : 보호막 18 : 유기 절연막17: protective film 18: organic insulating film

19 : 콘택홀 20 : 제 1 ITO 금속막19 contact hole 20 first ITO metal film

21 : 제 2 ITO 금속막 22 : 화소전극21: second ITO metal film 22: pixel electrode

상기 목적을 달성하기 위한 액정표시소자의 패널 제조방법은, 절연 기판상에 게이트 전극을 형성하는 단계와, 상기 게이트 전극을 포함한 기판 전면에 게이트 절연막을 형성하고, 상기 게이트 절연막상에 활성층을 형성하는 단계와, 상기 활성층을 포함한 게이트 절연막상에 소오스/드레인 전극 및 채널층을 형성하는 단계와, 상기 소오스/드레인 전극상을 포함한 기판 전면에 상기 소오스/드레인 전극중 어느하나가 노출되도록 콘택홀을 갖는 보호막을 형성하는 단계와, 상기 보호막상에 유기절연막을 증착하여 상기 보호막과 같이 유기절연막을 패터닝하고, 열처리한 후, UV 세정과 SF6가스를 이용하여 플라즈마 처리하는 단계와, 상기 플라즈마 처리된 유기절연막상에 아리곤 가스를 이용하여 제 1 ITO 박막을 증착하는 단계와, 상기 플라즈마 처리된 유기절연막 및 제 1 ITO 박막상에 아르곤과 산소혼합 가스를 이용하여 제 2 ITO 박막을 증착하는 단계와, 상기 제 1, 제 2 ITO 박막을 선택적으로 제거하여 상기 소오스/드레인 전극중 어느 하나와 콘택되는 화소전극을 형성하는 단계를 포함하는 것을 특징으로 한다.A panel manufacturing method of a liquid crystal display device for achieving the above object comprises the steps of forming a gate electrode on an insulating substrate, forming a gate insulating film on the entire surface of the substrate including the gate electrode, and forming an active layer on the gate insulating film Forming a source / drain electrode and a channel layer on the gate insulating film including the active layer, and having a contact hole to expose any one of the source / drain electrodes on the entire surface of the substrate including the source / drain electrode. Forming a passivation layer, depositing an organic insulation layer on the passivation layer, patterning the organic insulation layer like the passivation layer, and performing heat treatment, followed by plasma treatment using UV cleaning and SF 6 gas; Depositing a first ITO thin film using an argon gas on an insulating film, and performing plasma treatment Depositing a second ITO thin film using argon and an oxygen mixed gas on the substrate insulating film and the first ITO thin film, and selectively removing the first and second ITO thin films to contact any one of the source / drain electrodes. Forming a pixel electrode is characterized in that it comprises.

또한, 상기 제 1, 제 2 ITO 박막의 두께는 400∼2000Å인 것을 특징으로 하는 것이 바람직하다.Moreover, it is preferable that the thickness of the said 1st, 2nd ITO thin film is 400-2000 kPa.

또한, 상기 제 1 ITO 박막의 두께는 100∼500Å이고, 상기 제 2 ITO 박막의 두께는 300∼1500Å인 것이 바람직하다.In addition, the thickness of the first ITO thin film is preferably 100 to 500 kPa, and the thickness of the second ITO thin film is 300 to 1500 kPa.

또한, 상기 유기절연막 열처리시 200∼230℃에서 약 1시간 정도 하는 것이 바람직하다.In addition, the heat treatment of the organic insulating film is preferably performed at 200 to 230 ° C. for about 1 hour.

이하, 본 발명의 액정표시소자의 패널 제조방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a panel of a liquid crystal display device of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2는 본 발명의 일실시예에 따른 액정표시소자의 패널 제조방법을 나타낸 공정 단면도이다.2A through 2 are cross-sectional views illustrating a method of manufacturing a panel of a liquid crystal display according to an exemplary embodiment of the present invention.

본 발명의 액정표시소자의 패널 제조방법은, 도 2a에 도시한 바와 같이, 절연기판 즉, 유리기판(11)상에 게이트용 금속막을 증착하고, 제 1 마스크를 이용한식각 공정으로 상기 게이트용 금속막을 패터닝하여 게이트 전극(12)을 형성한다.In the method of manufacturing a panel of the liquid crystal display device of the present invention, as shown in FIG. 2A, a gate metal film is deposited on an insulating substrate, that is, the glass substrate 11, and the gate metal is etched by an etching process using a first mask. The film is patterned to form the gate electrode 12.

이어서, 상기 게이트 전극(12)을 포함한 기판(11) 전면에 게이트 절연막(13)을 형성한다.Subsequently, a gate insulating layer 13 is formed on the entire surface of the substrate 11 including the gate electrode 12.

그다음, 도 2b에 도시한 바와 같이, 상기 게이트 절연막(13)상에 도핑되지 않는 비정질 실리콘(이하, a-Si층이라 칭함)을 증착하고, 제 2 마스크를 이용한 식각 공정으로 상기 a-Si층을 선택적으로 식각하여 활성층(14)을 형성한다.Next, as shown in FIG. 2B, undoped amorphous silicon (hereinafter, referred to as an a-Si layer) is deposited on the gate insulating layer 13, and the a-Si layer is etched using a second mask. Is selectively etched to form the active layer 14.

이어서, 도 2c에 도시한 바와 같이, 상기 활성층(14)을 포함한 게이트 절연막(13)상에 채널층을 형성하기 위한 도핑된 비정질실리콘층(이하, n+a-Si층이라 칭함)과, 소오스/드레인 전극을 형성하기 위한 금속막을 차례로 형성하고, 제 3 마스크를 이용하여 상기 금속막과 n+a-Si층을 연속적으로 식각하여 소오스/드레인 전극(16) 및 채널층(15)을 형성한다.Next, as shown in FIG. 2C, a doped amorphous silicon layer (hereinafter referred to as n + a-Si layer) for forming a channel layer on the gate insulating layer 13 including the active layer 14, and a source. A metal film for forming a drain electrode is sequentially formed, and the source / drain electrode 16 and the channel layer 15 are formed by successively etching the metal film and the n + a-Si layer using a third mask. .

그다음, 도 2d에 도시한 바와 같이, 상기 소오스/드레인 전극(16)상을 포함한 기판(11) 전면에 보호막(17)과 유기절연막(18)을 증착하고, 제 4 마스크를 이용하여 상기 소오스/드레인 전극(16)중 어느 하나가 노출되도록 상기 보호막(17)과 유기절연막(18)을 선택적으로 식각하여 콘택홀(19)을 형성한다.Next, as shown in FIG. 2D, the passivation layer 17 and the organic insulating layer 18 are deposited on the entire surface of the substrate 11 including the source / drain electrodes 16, and the source / drain is formed using a fourth mask. The protective layer 17 and the organic insulating layer 18 are selectively etched to expose one of the drain electrodes 16 to form a contact hole 19.

이어서, 도 2e에 도시한 바와 같이, 상기 유기절연막(18)에 열처리 공정을 실시한 후, UV 세정 및 SF6가스를 이용하여 상기 유기절연막(18)을 플라즈마 처리한다. 이때, 상기 유기절연막(18)은 200∼230℃ 사이의 온도에서 약 1 시간 정도 열처리한다.Subsequently, as shown in FIG. 2E, the organic insulating film 18 is subjected to a heat treatment step, and then the organic insulating film 18 is plasma treated using UV cleaning and SF 6 gas. At this time, the organic insulating film 18 is heat treated for about 1 hour at a temperature between 200 and 230 ° C.

그다음, 상기 콘택홀(19)을 포함한 상기 유기절연막(18)상에 아르곤 가스을 주입하여 투명 금속막 예컨대, 제 1 ITO 금속막(20)을 증착한 후, 상기 유기절연막 (18) 및 상기 제 1 ITO 금속막(20)상에 아르곤 가스와 산소가스를 혼합 주압하여 제 2 ITO 금속막(21)을 증착한다. 이때, 상기 제 1 ITO 금속막(20)의 두께는 100∼500Å이고, 상기 제 2 ITO 금속막(21)의 두께는 300∼1500Å이다. 즉, 상기 제 1, 제 2 ITO 금속막(20)(21)의 총 두께는 400∼2000Å이다.Next, an argon gas is injected onto the organic insulating film 18 including the contact hole 19 to deposit a transparent metal film, for example, the first ITO metal film 20, and then the organic insulating film 18 and the first film. Argon gas and oxygen gas are mixed and pressurized on the ITO metal film 20 to deposit the second ITO metal film 21. At this time, the thickness of the first ITO metal film 20 is 100 to 500 kPa, and the thickness of the second ITO metal film 21 is 300 to 1500 kPa. That is, the total thickness of the first and second ITO metal films 20 and 21 is 400 to 2000 kPa.

이어서, 제 5 마스크를 이용하여 상기 제 1, 제 2 ITO 금속막(20)(21)을 선택적으로 식각하여 상기 소오스/드레인 전극(16)중 어느 하나와 콘택되는 화소전극 (22)을 형성한다.Subsequently, the first and second ITO metal layers 20 and 21 may be selectively etched using a fifth mask to form the pixel electrode 22 in contact with any one of the source / drain electrodes 16. .

도 3은 본 발명의 화소전극이 패너닝된 모양을 나타내는 광학 현미경 사진이다.3 is an optical photomicrograph showing a shape in which the pixel electrode of the present invention is panned.

이상에서 설명한 바와 같이, 본 발명의 액정표시소자의 패널 제조방법에 의하면, 유기절연막상에 화소전극을 증착시 화소전극으로 사용되는 ITO 박막의 산소 농도를 조절하여 비정질층 ITO 박막을 결정질층 ITO 박막으로 개질시킬 수 있다.As described above, according to the method of manufacturing a panel of the liquid crystal display device of the present invention, the amorphous ITO thin film is converted into an crystalline layer ITO thin film by adjusting the oxygen concentration of the ITO thin film used as the pixel electrode when the pixel electrode is deposited on the organic insulating film. Can be modified.

따라서, 장비나 공정의 변화없이 고개구율화 픽셀전극을 형성할 수 있고, 제조비용을 절감시킬 수 있다.Therefore, it is possible to form a high aperture pixel pixel electrode without changing equipment or processes, and to reduce manufacturing costs.

Claims (4)

절연 기판상에 게이트 전극을 형성하는 단계와;Forming a gate electrode on the insulating substrate; 상기 게이트 전극을 포함한 기판 전면에 게이트 절연막을 형성하고, 상기 게이트 절연막상에 활성층을 형성하는 단계와;Forming a gate insulating film on the entire surface of the substrate including the gate electrode, and forming an active layer on the gate insulating film; 상기 활성층을 포함한 게이트 절연막상에 소오스/드레인 전극 및 채널층을 형성하는 단계와;Forming a source / drain electrode and a channel layer on the gate insulating film including the active layer; 상기 소오스/드레인 전극상을 포함한 기판 전면에 상기 소오스/드레인 전극중 어느 하나가 노출되도록 콘택홀을 갖는 보호막을 형성하는 단계와;Forming a protective film having a contact hole on the entire surface of the substrate including the source / drain electrodes to expose one of the source / drain electrodes; 상기 보호막상에 유기절연막을 증착하여 상기 보호막과 같이 유기절연막을 패터닝하고, 열처리한후, UV 세정과 SF6가스를 이용하여 플라즈마 처리하는 단계와;Depositing an organic insulating film on the protective film, patterning the organic insulating film like the protective film, and performing heat treatment, followed by plasma treatment using UV cleaning and SF 6 gas; 상기 플라즈마 처리된 유기절연막상에 아리곤 가스를 이용하여 제 1 ITO 박막을 증착하는 단계와;Depositing a first ITO thin film on the plasma treated organic insulating layer using argon gas; 상기 플라즈마 처리된 유기절연막 및 제 1 ITO 박막상에 아르곤과 산소혼합 가스를 이용하여 제 2 ITO 박막을 증착하는 단계; 및Depositing a second ITO thin film on the plasma treated organic insulating film and the first ITO thin film using argon and an oxygen mixed gas; And 상기 제 1, 제 2 ITO 박막을 선택적으로 제거하여 상기 소오스/드레인 전극중 어느 하나와 콘택되는 화소전극을 형성하는 단계를 포함하는 것을 특징으로 하는 액정표시소자의 패널 제조방법.And selectively removing the first and second ITO thin films to form a pixel electrode in contact with any one of the source / drain electrodes. 제 1 항에 있어서,The method of claim 1, 상기 제 1, 제 2 ITO 박막의 두께는 400∼2000Å인 것을 특징으로 하는 액정표시소자의 패널 제조방법.The thickness of the said 1st, 2nd ITO thin film is 400-2000 micrometers, The panel manufacturing method of the liquid crystal display element characterized by the above-mentioned. 제 1 항 및 제 2 항에 있어서,The method according to claim 1 and 2, 상기 제 1 ITO 박막의 두께는 100∼500Å이고, 상기 제 2 ITO 박막의 두께는 300∼1500Å인 것을 특징으로 하는 액정표시소자의 패널 제조방법.The thickness of the first ITO thin film is 100 to 500 kPa, and the thickness of the second ITO thin film is 300 to 1500 kPa. 제 1 항에 있어서,The method of claim 1, 상기 유기절연막 열처리시 200∼230℃에서 약 1시간 정도 하는 것을 특징으로 하는 액정표시소자의 패널 제조방법.And about 1 hour at 200 to 230 [deg.] C during heat treatment of the organic insulating film.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100964615B1 (en) * 2003-08-29 2010-06-21 삼성전자주식회사 Manufacturing method of liquid crystal display device
KR101040834B1 (en) * 2009-03-31 2011-06-14 주식회사 탄탄구조엔지니어링 Solar Module Clamping Device for Solar Generator
US8207534B2 (en) * 2004-10-26 2012-06-26 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05158071A (en) * 1991-12-09 1993-06-25 Oki Electric Ind Co Ltd Production of lower substrate of active matrix liquid crystal display
KR19990010078A (en) * 1997-07-14 1999-02-05 구자홍 LCD and its manufacturing method
KR20000003740A (en) * 1998-06-29 2000-01-25 김영환 Method for manufacturing liquid crystal display of thin film transistor
KR20010057019A (en) * 1999-12-17 2001-07-04 구본준, 론 위라하디락사 Liquid Crystal Display Device and Method of Fabricating the Same
KR20010057018A (en) * 1999-12-17 2001-07-04 구본준, 론 위라하디락사 Method of Fabricating Liquid Crystal Display Device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05158071A (en) * 1991-12-09 1993-06-25 Oki Electric Ind Co Ltd Production of lower substrate of active matrix liquid crystal display
KR19990010078A (en) * 1997-07-14 1999-02-05 구자홍 LCD and its manufacturing method
KR20000003740A (en) * 1998-06-29 2000-01-25 김영환 Method for manufacturing liquid crystal display of thin film transistor
KR20010057019A (en) * 1999-12-17 2001-07-04 구본준, 론 위라하디락사 Liquid Crystal Display Device and Method of Fabricating the Same
KR20010057018A (en) * 1999-12-17 2001-07-04 구본준, 론 위라하디락사 Method of Fabricating Liquid Crystal Display Device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100964615B1 (en) * 2003-08-29 2010-06-21 삼성전자주식회사 Manufacturing method of liquid crystal display device
US8207534B2 (en) * 2004-10-26 2012-06-26 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US8288771B2 (en) 2004-10-26 2012-10-16 Samsung Electonics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US8455277B2 (en) 2004-10-26 2013-06-04 Samsung Display Co., Ltd. Thin film transistor array panel and manufacturing method thereof
KR101040834B1 (en) * 2009-03-31 2011-06-14 주식회사 탄탄구조엔지니어링 Solar Module Clamping Device for Solar Generator

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