KR20020023049A - Method for forming interconnection of semiconductor device - Google Patents

Abstract

A wiring forming method capable of reducing the interface resistance between a p-type impurity region and a contact plug is disclosed. An interlayer insulating film is formed on a semiconductor substrate having p-type and n-type impurity regions and then patterned to form a first contact hole exposing the n-type impurity region. A first conductive film is formed to fill the first contact hole. The first conductive film and the interlayer insulating film are patterned to form a second contact hole exposing a p-type impurity region. A second conductive film is formed to fill the second contact hole. The second and first conductive films are patterned to form first metal wirings connected with the p-type impurity region and second metal wirings connected with the n-type impurity region. According to this method, since the ion implantation process can be performed after forming the contact hole which exposes a p-type impurity region, the interface resistance between a p-type impurity region and a contact plug can be reduced.

Description

METHODS FOR FORMING INTERCONNECTION OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a wiring of a semiconductor device capable of reducing the interface resistance between a p-type impurity region and a contact plug.

As the circuit density increases in the semiconductor manufacturing process, the size of the metal wirings for electrically connecting the unit elements is also decreasing, and it is required to form wirings having a multilayer structure. As a result, not only the process of forming the metal wiring becomes more difficult, but also the problem of increasing the resistance due to the reduction in the cross-sectional area of the wiring occurs.

In particular, when manufacturing a DRAM cell having a stacked capacitor, it is difficult to apply a photolithography process to form a metal wiring because a step is generated in the cell region and the peripheral circuit region. In addition, an over-etching process for preventing open defects when forming contact holes in the peripheral circuit region is a cause of direct damage to the semiconductor substrate.

In order to improve this, a wiring forming method for simultaneously forming a contact plug and a metal pad connected to a source / drain region of a semiconductor substrate in a peripheral circuit region when forming a bit line in a cell region is used.

Hereinafter, the problems of the prior art will be described with reference to FIG. 1.

1A to 1D are cross-sectional views illustrating a wire forming method according to the related art, and illustrate portions corresponding to peripheral circuit regions of a semiconductor device.

Referring to FIG. 1A, an isolation layer 12 is formed to define an active region in a peripheral circuit region of a semiconductor substrate 10. A first gate pattern 18a and a second gate pattern 18b in which the gate oxide film 15, the gate electrode film 16, and the capping film 17 are sequentially stacked are formed on the active region.

N-type impurity ions are implanted on both sides of the first gate pattern 18a to form the first source / drain regions 20a, and p-type impurity ions are implanted on the sides of the second gate pattern 18b. 2 source / drain regions 20b are formed. Spacers 22 are formed of silicon nitride films on both sidewalls of the first and second gate patterns 18a and 18b. Here, the first gate pattern 18a and the first source / drain region 20a constitute an NMOS transistor, and the second gate pattern 18b and the second source / drain region 20b constitute a PMOS transistor.

Referring to FIG. 1B, an insulating film 25 is formed on the entire surface of the semiconductor substrate 10 on which the NMOS transistor and the PMOS transistor are formed. The insulating film 25 is patterned by a conventional photolithography process to form contact holes 27 exposing the first and second source / drain regions 20a and 20b.

Referring to FIGS. 1C and 1D, a tungsten film, which is a conductive film 31 filling the contact hole 27, is formed on the entire surface of the product in which the contact hole 27 is formed. The conductive film 31 is patterned to form a contact plug filling the contact hole 27 and a metal wiring 31a covering the contact plug.

According to this conventional technique, the contact hole 27 exposing the first and second source / drain regions 20a and 20b, that is, the n-type impurity region and the p-type impurity region, is simultaneously formed in a single photographic process. do. Therefore, it is difficult to secure a sufficient process margin during the photolithography process, and an additional ion implantation process for forming a low resistance contact in the p-type impurity region 20b cannot be performed. This increases the interfacial resistance of the contact plug connected to the p-type impurity region and causes the electrical characteristics of the device to decrease.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problems, and an object thereof is to provide a method for forming a wiring of a semiconductor device capable of reducing the interface resistance of a contact plug connected to a p-type impurity region.

1A to 1D are cross-sectional views illustrating a wiring forming method of a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a wiring forming method of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: device isolation film

18a, 18b, 108a, 108b: gate pattern

20a, 20b, 110a, 110b: source / drain regions

22, 112: spacer 25, 115: interlayer insulating film

27, 117, 122: contact hole 123: ion implantation process

31, 120, 125: conductive films 31a, 130, 132: metal wiring

(Configuration)

In order to achieve the above object, the present invention forms an interlayer insulating film on the entire surface of a semiconductor substrate having an impurity region of a first conductivity type and an impurity region of a second conductivity type. The interlayer insulating film is patterned to form first contact holes exposing impurity regions of the first conductivity type. A first conductive layer filling the first contact hole is formed on the entire surface of the resultant product in which the first contact hole is formed. The first conductive film and the insulating film are patterned to form second contact holes exposing impurity regions of the second conductivity type. A conductive film filling the second contact hole is formed on the entire surface of the resultant product in which the second contact hole is formed. The second conductive film and the first conductive film are patterned to form first wiring connected to the impurity region of the first conductivity type and second wiring connected to the impurity region of the second conductivity type.

One of the first conductivity type and the second conductivity type is n-type, the other is p-type, and a p-type impurity is formed on the exposed impurity region after forming a contact hole exposing the p-type impurity region. It is desirable to further ion implant the ions.

(Example)

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 2.

2A to 2F are cross-sectional views illustrating a wiring forming method of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 102 for defining an active region is formed on the semiconductor substrate 100. For example, the device isolation layer 102 is formed by a local oxidation of silicon (LOCOS) process or a trench device isolation process. The gate oxide layer 105, the gate electrode layer 106, and the gate capping layer 107 are formed on the entire surface of the semiconductor substrate 100 on which the device isolation layer 102 is formed, and then patterned to form the first gate pattern 108a and the second gate. Pattern 108b is formed.

Impurity ions of the first conductivity type are implanted on both sides of the first gate pattern 108a to form the first source / drain regions 110a. The first source / drain region 110a is formed by implanting n-type impurity ions such as phosphorus (P) or arsenic (As), for example. Impurity ions of the second conductivity type are implanted on both sides of the second gate pattern 108b to form the second source / drain regions 110b. The second source / drain region 110b is formed by implanting p-type impurity ions such as, for example, boron (B). Then, the first gate pattern 108a forms an NMOS transistor together with the n-type first source / drain region 110a, and the second gate pattern 108b forms the PMOS together with the second source / drain region 110b. Configure the transistor.

An insulating layer for forming a spacer, for example, a silicon nitride layer, is formed on the entire surface of the semiconductor substrate 100 on which the first and second source / drain regions 110a and 110b are formed. The insulating layer is anisotropically etched to form spacers 112 on both sidewalls of the first and second gate patterns 108a and 108b.

Referring to FIG. 2B, an interlayer insulating film 115 is formed on the entire surface of the resultant product in which the spacers 112 are formed. The interlayer insulating film 115 is formed of, for example, a high temperature oxide (HTO) film, an undoped silicate glass (USG) film, a borophosphosilicate glass (BPSG) film, and a plasma enhanced oxide (PE) oxide. The interlayer insulating film 115 is patterned to form a first contact / drain region 117, for example, a first contact hole 117 exposing an n-type impurity region.

Referring to FIG. 2C, the first conductive layer 120 filling the contact hole 117 is formed on the entire surface of the resultant product in which the first contact hole 117 is formed. The first conductive film 120 is formed of, for example, a doped polysilicon film or a tungsten film. When the first conductive film 120 is formed using a tungsten film, it is preferable to form a barrier film on the entire surface of the resultant product in which the contact hole 117 is formed before the conductive film 120 is formed.

Referring to FIG. 2D, the second contact hole 122 exposing the second source / drain region 110b, for example, a p-type impurity region, may be patterned by patterning the first conductive layer 120 and the interlayer insulating layer 115. To form. An ion implantation process 123 is performed to reduce the interface resistance between the second source / drain region 110b exposed through the contact hole 122 and the contact plug formed in a subsequent process. The ion implantation process 123 is selectively performed on the second source / drain region 110b, for example, using p-type impurity ions such as boron ions. In the present invention, since the process of forming the contact holes 117 and 122 exposing the n-type impurity region 110a and the p-type impurity region 110b is performed separately, the p-type impurity is not affected without affecting the n-type impurity region 110a. The ion implantation process 123 may be selectively performed only on the region 110b.

Referring to FIG. 2E, when the ion implantation process 123 is finished, the second conductive layer 125 filling the second contact hole 122 is formed on the entire surface of the resultant product in which the second contact hole 122 is formed. The second conductive film 125 is formed of, for example, a doped polysilicon film or a tungsten film. When the second conductive film 125 is formed using a tungsten film, it is preferable to form a barrier film on the entire surface of the resultant product in which the second contact hole 122 is formed before forming the tungsten film.

Referring to FIG. 2F, the second conductive film 125 and the first conductive film 120 are patterned to form the first metal wire 130 and the second metal wire 132. The first metal wire 130 is connected to the first source / drain region 110a by a first contact plug formed of the first conductive film 120, and the second metal wire 132 is connected to the second conductive film 125. Is connected to the second source / drain region 110b by the second contact plug formed of

According to this method, the photolithography process for forming the contact holes 117 and 122 exposing the first and second source / drain regions 110a and 110b is performed twice, thus forming the contact hole in one photolithography process. Process margins can be increased as compared to the prior art. Further, after forming the second contact hole 122 exposing the second source / drain region 110b, which is a p-type impurity region, an ion implantation process 123 is performed to reduce the interface resistance with the second contact plug. can do. Therefore, the interface resistance between the second source / drain region 110b and the second contact plug can be reduced.

According to the present invention, when forming contact plugs connected to a p-type impurity region and an n-type impurity region, the respective contact plugs are separately formed through two photolithography processes, thereby increasing the process margin during the photolithography process. In addition, since the interface resistance of the contact plug connected to the p-type impurity region is reduced by performing an ion implantation process to reduce the resistance in the p-type impurity region, there is an effect that can improve the electrical characteristics of the device.

Claims (4)

Forming an interlayer insulating film over the semiconductor substrate having the first conductivity type impurity region and the second conductivity type impurity region; Patterning the interlayer insulating film to form a first contact hole exposing the impurity region of the first conductivity type; Forming a first conductive layer filling the first contact hole on the entire surface of the resultant product in which the first contact hole is formed; Patterning the first conductive layer and the interlayer insulating layer to form a second contact hole exposing the second conductivity type impurity region; Forming a conductive film filling the second contact hole on the entire surface of the resultant product in which the second contact hole is formed; And Patterning the second conductive film and the first conductive film to form a first wiring connected to the first conductivity type impurity region and a second wiring connected to the second conductivity type impurity region; The wiring formation method of a semiconductor device. The method of claim 1, Wherein one of the first conductivity type and the second conductivity type is n-type and the other is p-type. The method of claim 2, And forming a contact hole for exposing the p-type impurity region and then ion implanting additional p-type impurity ions onto the exposed impurity region. The method of claim 1, And the first conductive film and the second conductive film are formed of a doped polysilicon film or a tungsten film.