KR100427719B1 - Method of Forming Bit-Line of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to form a contact hole in a P + source / drain (hereinafter referred to as "S / D") region, By forming contact holes in the N + S / D regions, the post etch treatment (hereinafter referred to as "PET") process for stabilizing the resistance of the P + S / D contact hole regions is performed. The present invention relates to a method for forming a bit line of a semiconductor device which prevents an increase in resistance.

The contact holes of the P + S / D region and the N + S / D region formed by the above-described process method of the present invention not only have a safe resistance but also perform additional ion implantation on the entire surface of the wafer, thereby causing local oxide damage. It is possible to prevent the formation of the bridge by preventing the step difference, and to reduce the mask process and the Rapidly Thermal Annealing (RTA) process step, thereby improving the performance and yield of the semiconductor device.

Description

Method of forming bit line of semiconductor device {Method of Forming Bit-Line of Semiconductor Device}

The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to form a contact hole in a P + source / drain (hereinafter referred to as "S / D") region, By forming contact holes in the N + S / D regions, the post etch treatment (hereinafter referred to as "PET") process for stabilizing the resistance of the P + S / D contact hole regions is performed. The present invention relates to a method for forming a bit line of a semiconductor device which prevents an increase in resistance.

At present, as the semiconductor memory device becomes more integrated and larger in capacity, the unit cell size of the semiconductor memory device continues to decrease. In particular, in the case of DRAM (Dynamic Random Access Memory (DRAM)), which leads to an increase in the degree of integration, the vertical structure becomes extremely complicated as the memory cell size is reduced, and the development of a method for increasing the effective area of the capacitor is difficult. It became necessary.

Conventionally, a bit line contact used as a path for data input and output using polysides of polycrystalline silicon (tungsten) and tungsten silicide in order to increase the high integration of semiconductor devices and to satisfy information processing capability. A hole was formed. However, the contact hole formed as described above has caused another problem that the resistance increases as the size decreases.

Therefore, in recent years, a contact hole is formed of tungsten having a low resistance to reduce the resistance value of the contact hole.

However, even in the case of the tungsten contact hole, the resistance change of the contact hole was large when the thermal process was performed.

In particular, since the contact hole resistance of the P + S / D region has increased greatly, to solve this problem, the subsequent PET process was performed only in the P + S / D region. However, since the above PET process is performed after simultaneously forming contact holes in the P + S / D region and the N + S / D region, the contact hole resistance of the P + S / D region is lowered, while the N + S / D region is used. Has caused another problem to increase.

This is because the contact hole resistances of the N + S / D region and the P + S / D region are opposite to each other. Therefore, when the contact hole resistance of the P + S / D region is lowered, the contact hole resistance of the N + S / D region becomes As the contact hole resistance in the N + S / D region decreases, the contact hole resistance in the P + S / D region increases.

That is, when the result is described in detail, as shown in FIG. 1, when the PET process is performed to lower the constant for the contact hole of the P + S / D region having an average resistance of 1200 kW, the P + S / D region may be formed. While the contact hole resistance was stabilized to an average of 900 kW, the contact hole resistance value of the N + S / D region, which had an average of 280 to 300 kW as shown in FIG. 2, was 450 kW by the PET process. There is a problem that the resistance value is increased.

The conventional bit line contact forming process will be described in detail with reference to the drawings.

First, as shown in FIG. 3A, a word line pattern and a plug 7 are formed in a cell region of a semiconductor substrate, and a P + S / D region 11 and an N + S / D region 13 are formed in a peripheral region. Formed.

An interlayer insulating film layer 9 was formed on the entire surface of the structure. At this time, the interlayer insulating film layer 9 was formed using an oxide film.

As shown in FIG. 3B, the plug region 7, the P + S / D region 11, and the N + S / D region 13 were simultaneously etched to form contact holes.

Thereafter, a PET process was performed on the contact holes in the P + S / D region.

As shown in FIG. 3C, a photoresist layer 15 was formed on the entire surface of the resultant contact hole.

As shown in FIG. 3D, a mask operation was performed on the photoresist layer 15 in the P + S / D region and developed to form a contact hole.

In addition, in order to stabilize the contact hole resistance of the P + S / D region, after performing P + additional impurity ion implantation 17, the photoresist 15 is stripped.

After removing the photoresist as shown in FIG. 3E, rapid thermal annealing (hereinafter, referred to as “RTA”) method is used to solve oxide damage of the P + S / D region due to the additional impurity ion implantation. Annealing was performed.

If a subsequent process is performed without performing the RTA process as described above, a rapid etching phenomenon occurs at a portion that is damaged during the subsequent barrier metal pre-clean process, and thus, the P + additional impurity ion implantation region is not formed. A step 23 was created between the regions that were not, resulting in a bridge 25 (see FIG. 4).

As shown in FIG. 3F, after the RTA process, a barrier metal layer 19 using titanium / titanium nitride (Ti / TiN) is formed on the contact hole and the entire surface of the interlayer insulating film, and the Ti layer deposited by the RTA process; After the TiSi ₂ was formed by the reaction of the Si substrate to stabilize the contact hole resistance, a tungsten (W) 21 layer was formed thereon.

As shown in FIG. 3g, the tungsten layer was etched to form a tungsten bit line.

However, since the contact holes of the P + S / D region and the contact holes of the N + S / D region are simultaneously formed in the bit line forming method of the conventional semiconductor device as described above, when the PET process, which is a subsequent process, is performed, The process steps are complicated, such as an increase in contact hole resistance, an RTA process to be introduced to prevent the oxide film damage caused by P + additional impurity ion implantation, and an increase in contact hole resistance, thereby increasing device integration and high-speed information processing capability. There was a problem of decreasing.

Accordingly, the present inventors have overcome the above problems, and an object of the present invention is to provide a method for forming a bit line of a semiconductor device in which both N + and P + S / D regions have stable resistance values.

1 is a graph showing the resistance value of the PET process presence or absence for the contact hole of the P + S / D region formed by a conventional method.

Figure 2 is a graph showing the resistance value of the PET process presence or absence for the contact hole of the N + S / D region formed by a conventional method.

3A to 3G are diagrams illustrating a bit line forming process of a semiconductor device by a conventional method.

4 is a view showing a step generated in the ion implantation process according to the conventional method.

5A to 5F are bit line forming process diagrams of a semiconductor device according to the present invention.

<Brief description of the main parts of the drawing>

1, 111: word line 3, 113: hard mask

5, 115: spacer 7, 117: plug

9, 119: interlayer insulating film 11, 121: P + source / drain

13, 123: N + source / drain 15, 125: photoresist layer

17, 127: P-type impurity ion implantation 19, 129: barrier metal layer

21, 131: tungsten 23: step

25: bridge

In order to achieve the above object, in the present invention, a method of forming a semiconductor device capable of stabilizing all contact hole resistance values by forming a P + S / D contact hole region, performing a PET process, and then forming an N + contact hole region. To provide.

Hereinafter, the present invention will be described in detail.

Forming a word line pattern, a plug, a P + S / D region, and an N + S / D region on the semiconductor substrate;

Forming a planarized interlayer insulating film layer over the entire surface of the structure;

Forming a contact hole by etching the interlayer insulating layer until the P + S / D region is exposed;

Performing P + additional impurity ion implantation on the entire surface of the interlayer insulating film;

Forming a contact hole by etching the interlayer insulating layer until the N + S / D region is exposed;

Etching the interlayer insulating layer until the plug region is exposed to form a contact hole;

Forming a planarized barrier metal layer on the interlayer insulating layer on which the contact hole is formed;

Forming a tungsten layer on the barrier metal layer; And

And forming a tungsten bit line by etching the tungsten layer and the barrier metal layer until the interlayer insulating layer is exposed.

In this case, the interlayer insulating film is formed using an oxide film.

The contact hole of the P + S / D region is inserted into the reaction chamber by mixing CF ₄ , CHF ₃ , O ₂ , Ar, and CO gas, and then etched until the P + region is exposed using the mixed contact.

After the etching process of forming the contact hole in the P + S / D region, the substrate is further etched by a thickness of about 20 to 50% of the height of the interlayer insulating film, preferably about 30 to 50%. It is preferable to carry out.

In addition, it is preferable to perform the PET process using the mixed gas of CF ₄ , Ar, and O ₂ in the reaction chamber once more on the semiconductor substrate, that is, the silicon (Si) substrate, in the contact hole portion of the exposed P + S / D region. Do. At this time, the thickness of the substrate to be etched is 20 to 150 kPa, preferably 50 to 100 kPa.

As described above, the PET process performed only on the contact hole of the P + S / D region may remove the damage portion of the silicon substrate, and the silicon substrate may be oxidized by the O ₂ gas used during etching, By removing the barrier metal during cleaning, the bonding ability of the barrier metal layer and the silicon substrate layer is increased, and thus the contact hole resistance value of the P + S / D region can be lowered.

Thereafter, P + additional impurity ions are implanted into the entire surface of the interlayer insulating film on which the contact holes are formed in order to stabilize the contact holes in the P + S / D region, since a local oxide loss as in the prior art does not occur. Do not perform the RTA process.

The implantation of additional impurity ions in the P + S / D region is preferably performed by using BF ₂ gas, and the energy conditions at the time of ion implantation are 10-30 KeV, preferably 10-25 KeV, and the dose of ion implantation is 1.0 × 10 ^{-15 to} 5.0 × 10 ^-15 , preferably 2.0 × 10 ^{-15 to} 4.0 × 10 ^-15 .

In the present invention, contact holes in the P + S / D region are formed under the above conditions, and then contact holes in the N + S / D region are formed.

The contact holes of the N + S / D region are inserted into the reaction chamber by mixing CF ₄ , CHF ₃ , O ₂ , Ar, and CO, etc., and then etched until the N + S / D region is exposed. .

Further, after the etching fixing, the substrate is further etched by 20 to 50% of the height of the interlayer insulating film, preferably 30 to 50%.

In addition, in the case of forming the contact hole for the plug, the same conditions as for forming the contact hole in the N + S / D region are performed.

As described above, the present invention forms a contact hole in the P + S / D region, and only performs the PET process, and thus does not affect the contact hole in the N + S / D region. Thus, both the contact hole in the P + S / D region and the contact hole in the N + region can have a stable resistance value.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 5A, a word line pattern and a plug 117 are formed in a cell region of a semiconductor substrate, and a P + S / D region 121 and an N + S / D region 123 are formed in a peripheral region. .

An interlayer insulating film layer 119 is formed over the entire structure. In this case, the interlayer insulating layer 119 is formed using an oxide film.

As shown in FIG. 5B, a photoresist is coated on the interlayer insulating layer, and the interlayer insulating layer 119 is etched by using the photoresist as a mask until the P + S / D region 121 is exposed. Form.

After stripping the photoresist, a PET process using CF ₄ , O _2, and Ar gas is performed on the contact holes in the P + S / D region.

Thereafter, a P + additional impurity ion implantation process is performed on the entire surface of the interlayer insulating layer 119 to stabilize the contact hole resistance of the P + S / D region.

After masking the N + S / D region as shown in FIG. 5C, the interlayer insulating layer is etched until the N + S / D region 123 is exposed to form contact holes in the N + S / D region. The etching process may be etched under the same conditions as the etching process for forming the P + S / D contact hole, but the PET process and the additional ion implantation process may not be performed.

As shown in FIG. 5D, a contact hole is formed in the upper portion of the plug 117 in the cell region. The etching process is also etched under the same conditions as the etching process for forming contact holes in the N + S / D region.

As shown in FIG. 5E, after forming the barrier metal layer 129 using Ti / TiN on the interlayer insulating layer 119 on which the contact hole is formed, TiSi is formed by the reaction of the Ti layer formed by the RTA process and the Si substrate. ₂ is formed to stabilize the resistance of the contact hole.

A tungsten layer 131 is formed on the barrier metal layer 129.

As shown in FIG. 5F, the turnsten layer and the barrier metal layer 129 are etched until the interlayer insulating layer is exposed to form stable bit line wiring.

As described above, according to the present invention, since the P + additional impurity ion implantation is performed on the entire surface of the wafer, local steps and bridges are not generated, so that subsequent mask processes and RTA process steps can be eliminated, and P + S / D Since the PET process is performed only on the contact holes in the region, both the contact holes in the P + S / D region and the contact holes in the N + S / D region have stable contact hole resistance, thereby improving performance and yield of the semiconductor device.

Claims (18)

Forming a word line pattern, a plug, a P + S / D region, and an N + S / D region on the semiconductor substrate; Forming a planarized interlayer insulating film layer on top of the structure; Forming a contact hole by etching the interlayer insulating layer until the P + S / D region is exposed; Implanting P + additional impurity ions into the entire interlayer insulating film layer; Forming a contact hole by etching the interlayer insulating layer until the N + S / D region is exposed; Etching the interlayer insulating layer until the plug region is exposed to form a contact hole; Forming a barrier metal layer on the interlayer insulating layer having the contact hole formed thereon; Forming a tungsten layer on the barrier metal layer; And Forming a tungsten bit line by etching the tungsten layer and the barrier metal layer until the interlayer insulating film is exposed. The method of claim 1, The contact hole of the P + S / D region is formed by an etching process using at least one gas selected from the group consisting of CF ₄ , CHF ₃ , O ₂ , Ar and CO. The method of claim 1, And forming a contact hole in the P + region, and overetching the semiconductor substrate. The method of claim 3, wherein The transient etching is performed to a thickness of 20 to 50% of the height of the interlayer insulating film. The method of claim 4, wherein The method of forming a semiconductor device, characterized in that the excessive etching is performed to 30 to 50% thickness of the interlayer insulating film height. The method of claim 3, wherein And forming a post-etch treatment (PET) process after the excessive etching. The method of claim 6, Wherein the PET process is performed using at least one gas selected from the group consisting of CF ₄ , Ar, and O ₂ . The method of claim 6, The PET process is a method for forming a semiconductor device, characterized in that to further etch a silicon (Si) substrate by 20 ~ 150Å thickness. The method of claim 8, The PET process is a method of forming a semiconductor device, characterized in that for further etching the silicon substrate by 50 ~ 150Å thickness. The method of claim 1, The method of forming a semiconductor device, characterized in that the P + additional impurity ion implantation using a BF ₂ gas. The method of claim 1, The energy condition for the P + additional impurity ion implantation is 10 to 30 KeV. The method of claim 11, The energy condition for the P + additional impurity ion implantation is 10 to 25 KeV. The method of claim 1, A dose amount of the P + additional impurity ion implantation is 1.0 × 10 ^{−15 to} 5.0 × 10 ⁻¹⁵ . The method of claim 13, The dose amount of the said P + addition impurity ion implantation is 2.0 * 10 <^-15> -4.0 * 10 <^-15> , The formation method of the semiconductor element characterized by the above-mentioned. The method of claim 1, And forming a contact hole in the N + S / D region using at least one gas selected from the group consisting of CF ₄ , Ar, and O ₂ . The method of claim 1, And forming a contact hole in the N + region, and then over-etching the semiconductor device. The method of claim 16, The transient etching is carried out at 20 to 50% of the height of the interlayer insulating film. The method of claim 17, The transient etching is carried out at 30 to 50% of the height of the interlayer insulating film.