KR20010038179A - method for fabricating SOI device - Google Patents

Abstract

Disclosed is a method of fabricating an SOI device in which a floating body effect is prevented from occurring below a channel region to achieve optimization of characteristics of an SOI product. In order to achieve this, in the present invention, a step of preparing an SOI substrate having a structure in which a BOX layer is formed on the first silicon layer and a second silicon layer is formed on the BOX layer, and an insulating material defining a channel forming part Sequentially etching the second silicon layer and the BOX layer to expose a predetermined portion of the surface of the first silicon layer using a mask to form a groove in the SOI substrate, and to form a planarized epi layer in the groove. Etching the second silicon layer to expose a portion of the surface of the BOX layer using a mask made of an insulating material defining an isolation region, and forming a device isolation layer on the etched portion of the second silicon layer. Forming a gate electrode by forming a gate oxide film on a predetermined portion of the second silicon layer including the epitaxial layer, and The SOI device manufacturing method comprising forming source / drain regions of the LDD structure in the second silicon layer of the gate electrode both side edges is provided.

Description

Method for fabricating SOI device

The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating an SOI device in which a floating body effect is prevented from occurring below a channel region, thereby optimizing characteristics of an SOI product. will be.

In recent years, a silicon on insulator (SOI) technology that forms a single crystal silicon layer on an insulator layer and integrates a unit device on the silicon layer has attracted attention. This is because in the case of a semiconductor device (eg, SOI) manufactured by applying the above technology, the silicon substrate and the unit device in the upper layer have a structure in which the oxide layer (aka, a buried oxide (BOX) layer) is completely separated. This is because it is possible to reduce the junction capacitance during driving, thereby achieving speed improvement compared to a general bulk device.

1 is a cross-sectional view showing the structure of the SOI device that has been commonly used in the prior art.

According to the cross-sectional view of FIG. 1, a conventional SOI device includes a BOX layer 12 formed on the first silicon layer 10 and a second silicon layer 14 formed on the BOX layer 12. A device isolation film 16 is formed in a predetermined portion (device isolation region) in the second silicon layer 14 so that the bottom surface is in contact with the BOX layer 12, and the second silicon layer 14 between the device isolation films 16 is formed. A gate electrode 20 is formed by interposing a gate oxide film 18 thereon, spacers 24 are formed on both sidewalls of the gate electrode 20, and a second silicon layer on both edges of the gate electrode 20 is formed. In the 14, source / drain regions 22a and 22b having a lightly doped drain (LDD) structure having a bottom surface in contact with the BOX layer 12 are formed, so that the BOX layer 12 and the device isolation film 16 are formed. It can be seen that the device design is made such that the sealed active region is used as the channel region of the transistor.

However, when the SOI device is manufactured to have the above structure, the following problem occurs when driving the transistor. Here, as an example, the first and second silicon layers 10 and 14 constituting the SOI substrate are formed of a P type, and the source / drain regions 22a and 22b are formed in an NMOS transistor formed of a high concentration N type. Examine.

In order to drive the transistor, V _G and V _D must be applied to the gate electrode and the drain region, respectively. In the case of an NMOS transistor, when V _D increases, electrons passing through the channel increase, thereby increasing current flow. As the current flow increases due to the increase in V _D, these electrons collide with silicon in the drain region to generate holes and silicon electrons. As a result, the holes are formed by the difference in potential (body). To an active region enclosed by the device isolation film and the BOX layer.

In the case of bulk elements, the holes do not have a problem because they exit through the ground-grounded substrate in the case of the bulk element, but in the case of the SOI element, the BOX layer is buried under the body so that the holes are formed in the first silicon. Since it does not escape to the layer and continuously accumulates in the body, the potential of the body, that is, the voltage is changed. As described above, a state in which the body is floated, that is, a floating body effect is generated, is changed.

When the floating body effect occurs, device characteristics such as lowering the threshold voltage (Vth) of the transistor or unstable dynamic characteristics of the SRAM may cause data error, resulting in deterioration of device characteristics. This is urgently required.

Accordingly, an object of the present invention is to directly connect a channel region of a unit element (transistor) formed at an upper end of a BOX layer and a silicon layer at a lower end of a BOX layer placed directly under the BOX layer through a process change during fabrication of an SOI device. The present invention provides a method of manufacturing an SOI device capable of optimizing characteristics of an SOI product by preventing floating body effects from occurring at the bottom.

1 is a cross-sectional view showing a conventional SOI device structure,

2A to 2F are process flowcharts illustrating a method for fabricating an SOI device according to a first embodiment of the present invention;

3A to 3F are process flowcharts illustrating a method for fabricating an SOI device according to a second exemplary embodiment of the present invention.

In order to achieve the above object, in the present invention, a step of preparing an SOI substrate having a structure in which a BOX layer is formed on the first silicon layer, and a second silicon layer is formed on the BOX layer, and insulation defining a channel forming portion. Forming a groove in the SOI substrate by sequentially etching the second silicon layer and the BOX layer so that the surface of the first silicon layer is partially exposed by using a mask made of a material; Etching the second silicon layer to expose a portion of the surface of the BOX layer using a mask made of an insulating material defining an isolation region, and forming an element on the etched portion of the second silicon layer. Forming a separator and forming a gate electrode by interposing a gate oxide film on a predetermined portion of the second silicon layer including the epitaxial layer; And forming a source / drain region of an LDD structure in the second silicon layer on both edges of the gate electrode.

In this case, the groove may be formed to have a "pillar" shape by etching the same area of the second silicon layer and the BOX layer, and to have a "T" shape by etching the second silicon layer more wider than the BOX layer. It may be formed. The planarized epi layer in the groove is formed by a CMP process or a PR etch back process.

In the process as described above, since the device fabrication is made so that the channel region of the transistor formed on the top of the BOX layer, that is, the body is directly connected to the first silicon layer through the BOX layer directly below, the device is driven Although the increase in current V _D causes a large flow of currents, which causes holes to collect toward the body, they all exit to the ground-grounded substrate, that is, the first silicon layer. Will not.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2F show a process flowchart showing the method for manufacturing the SOI device proposed in the first embodiment of the present invention. Referring to this, looking at the manufacturing method divided into six steps as follows.

As a first step, as illustrated in FIG. 2A, a SOI having a structure in which a BOX layer 102 is formed on the first silicon layer 100, and a second silicon layer 104 is formed on the BOX layer 102. Prepare the substrate.

As a second step, as shown in FIG. 2B, a first mask layer 106 made of an oxide film and a second mask layer 108 made of a nitride film are sequentially formed on the SOI substrate, and then a channel of the transistor is formed thereon. A photoresist pattern (not shown) defining the formation portion is formed. The first and second mask layers 106 and 108 are etched using the resist pattern as a mask, and then the resist patterns are removed, and the first and second mask layers 106 and 108 are etched. The second silicon layer 104 and the BOX layer 102 in portions not protected by the etching process are removed through an etching process. As a result, grooves g of a “pillar” shape having no line width change in the upper and lower ends are formed in the SOI substrate. Subsequently, the epitaxial layer 110 made of epitaxial Si or epitaxial Si-Ge is grown on the resultant including the groove g. In this case, since the epi layer 110 hardly grows on the mask layer 108 made of an insulating material, here, for convenience, the epi layer is grown only along the adjacent part including the inside of the groove. do. In this case, the epi layer 110 is preferably grown such that the thickness t from the surface of the second mask layer 108 has a value of 300 nm or less.

As a third step, as shown in FIG. 2C, the epi layer 110 is planarized by applying the CMP method. In this process, the second mask layer 108 is also partially removed. In the present embodiment, for example, the epi layer 110 is shown to be flattened to have the same step as the second silicon layer 104 forming the SOI substrate, but the epi layer has a somewhat higher step than this. It may be flattened so as to be flat.

As a fourth step, as illustrated in FIG. 2D, the first and second mask layers 106 and 108 are removed, and the third mask layer 112 made of an oxide film and the fourth material made of a nitride film are formed on the entire surface of the resultant product. After the mask layer 114 is formed sequentially, a photoresist pattern (not shown) defining an isolation region is formed thereon. After the third and fourth mask layers 112 and 114 are etched using the resist pattern as a mask, the resist patterns are removed, and the etched third and fourth mask layers 112 and 114 are etched. The second silicon layer 104 of the portion that is not protected by (ie, the portion to be used as the isolation region) is removed by an etching process. As a result, the surface of the BOX layer 102 is exposed to a predetermined portion.

As a fifth step, as shown in FIG. 2E, an oxide layer having a predetermined thickness is formed on the entire surface of the resultant by a film deposition method, and planarizes it until the surface of the second silicon layer 104 is exposed by CMP. An element isolation film 116 is formed.

As a sixth step, as shown in FIG. 2F, the gate electrode 120 is formed by interposing a gate oxide film 118 in a predetermined portion on the second silicon layer 104 including the epi layer 110. Subsequently, a low concentration of impurities are ion-implanted onto the substrate using the gate electrode 120 as a mask, and spacers 124 of an insulating material are formed on both sidewalls of the gate electrode 120, and then high concentrations are formed on the resultant. By implanting impurities, the source / drain regions 122a and 122b of the LDD structure whose bottom surface is in contact with the BOX layer 102 are formed in the second silicon layer 104 on both edges of the gate electrode 120. The process is completed.

In the present exemplary embodiment, the epi layer 110 may be replaced with poly polycrystalline Si or poly polycrystalline Si-Ge, and the process of forming the planarized epi layer in the groove g may be performed using a photoresist (hereinafter, P) instead of the CMP method. / R) can be implemented by applying the etch back technique. However, when the epi layer 110 is planarized by applying a PR etch back technique, a photoresist film having a predetermined thickness is formed on the entire surface of the resultant layer after the growth of the epi layer 110 is completed, so that a part of the mask layer remains. The process may be performed by etching back the resist film and the epi layer 110 and removing the remaining mask layer through a cleaning operation.

Meanwhile, as the second embodiment of the present invention, the element has the same basic process as the first embodiment, but forms a shape of the hole g formed in the SOI substrate slightly differently from the first embodiment. It is also possible to manufacture in a manner, Figures 3a to 3f is a process flow diagram illustrating a method for manufacturing a SOI device associated with it. In the present embodiment, for convenience, the process proceeding in the same manner as in the first embodiment will be briefly mentioned, and the process centered on this process will be described.

As a first step, as illustrated in FIG. 3A, a SOI having a structure in which a BOX layer 102 is formed on the first silicon layer 100 and a second silicon layer 104 is formed on the BOX layer 102. Prepare the substrate.

As a second step, as shown in FIG. 3B, a first mask layer 106 of an oxide film material and a second mask layer 108 of a nitride film material are sequentially formed on the substrate, and then a channel of a transistor is formed thereon. A photoresist pattern (not shown) defining portions is formed. After the first and second mask layers 106 and 108 are etched using the resist pattern as a mask, the resist patterns are removed, and the first and second mask layers 106 and 108 which are subsequently etched are subsequently removed. The second silicon layer 104 and the BOX layer 102 in portions not protected by the etch are sequentially etched. Thereafter, the first and second mask layers 106 and 108 around the channel forming portion are lateral in order to secure the etching region of the second silicon layer 104 more widely than the etching region of the BOX layer 102. After the predetermined partial expansion etching in the lateral direction, the second silicon layer 104 is etched using the mask as a mask so that the surface of the BOX layer 102 is partially exposed along the periphery of the channel forming portion. As a result, a "T" shaped groove g is made in the SOI substrate. As such, the groove g is formed in a “T” shape because an epitaxial layer having better film quality characteristics can be grown as compared with the case where the groove g is formed in a “column” shape having the same line width in a subsequent process.

As a third step, as illustrated in FIG. 3C, the epitaxial layer 110 may be planarized by applying a CMP process or a PR etch back process to partially retain the first and second mask layers 106 and 108.

As a fourth step, as illustrated in FIG. 3D, the remaining mask layers 106 and 108 are removed, and the third mask layer 112 made of an oxide film and the nitride film material are formed to open the device isolation region on the resultant. After the fourth mask layer 114 is sequentially formed, the second silicon layer 104 of the portion (that is, the portion to be used as the device isolation region) that is not protected by the mask layers 112 and 114 is formed. Removed by etching process.

As a fifth step, as shown in FIG. 3E, the device isolation layer 116 is formed on the portion where the second silicon layer 104 is etched.

As a sixth step, as shown in FIG. 3F, a gate oxide film 118 is formed on a predetermined portion of the second silicon layer 104 including the epi layer 110 to form the gate electrode 120. This process is completed by forming the spacers 124 and the source / drain regions 122a and 122b of the LDD structure through the process.

When the process is performed in this way, the channel region of the transistor formed on the top of the BOX layer, that is, the body (representing an active region surrounded by the device isolation layer and the BOX layer) penetrates the BOX layer 102 directly below the first silicon. The device configuration is made to have a structure that is directly connected to the layer 100.

Therefore, even though the current flowing through the channel is increased due to the increase in the V _D voltage applied to the drain region when driving the device, even though holes are collected toward the body due to the potential difference, they are all ground-grounded substrates. Since it is exited toward the first silicon layer 100, the floating body effect does not appear at the bottom of the channel region.

As a result, it is possible to prevent the deterioration of the characteristics of the transistor such as lowering the threshold voltage (Vth) of the transistor, dynamic characteristics instability of the SRAM, etc., thereby enabling the optimization of the characteristics of the SOI product.

As described above, according to the present invention, the channel region (ie, the body) of the unit element (transistor) formed on the top of the BOX layer and the first silicon layer directly below the BOX layer are directly grown through the epitaxial layer grown through the BOX layer. Since device fabrication is made to have a connected structure, the floating body effect can be prevented from occurring below the channel region, thereby maximizing the characteristics of the SOI product.

Claims (4)

Preparing a SOI substrate having a structure in which a BOX layer is formed on the first silicon layer, and a second silicon layer is formed on the BOX layer; Forming a groove in the SOI substrate by sequentially etching the second silicon layer and the BOX layer so that the surface of the first silicon layer is partially exposed using a mask made of an insulating material defining a channel forming portion; Forming a planarized epi layer in the groove; Etching the second silicon layer to expose a portion of the surface of the BOX layer by using an insulating mask defining an isolation region; Forming a device isolation layer on an etching portion of the second silicon layer; Forming a gate electrode by interposing a gate oxide film on a predetermined portion of the second silicon layer including the epi layer; And And forming a source / drain region of an LDD structure in the second silicon layer at both edges of the gate electrode. The method of claim 1, wherein the groove is formed to have a “pillar” shape by etching the second silicon layer and the BOX layer in the same area, or by etching the second silicon layer more widely than the BOX layer. SOI device manufacturing method characterized in that it is formed to have a shape. The method of claim 1, wherein the planarized epi layer is formed by a CMP process or a PR etch back process. The method of claim 1, wherein the epitaxial layer is formed of any one selected from epitaxial Si and epitaxial Si-Ge.