KR100188008B1 - Method of manufacturing cmos semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a CMOS semiconductor device, comprising: forming first and second conductivity type wells and a device isolation oxide film on a semiconductor substrate; Forming a gate oxide film on the resultant; Forming a first polysilicon layer and a nitride layer on the entire upper surface of the gate oxide layer; Etching the portion of the nitride film corresponding to the gate poly formation region to expose the first polysilicon layer; Implanting channel ions into the vicinity of the surface of the substrate (well) through the nitride film opening; Filling the opening of the nitride film with polysilicon to form a second polysilicon layer; The first and second polysilicon layers on the upper portion of the wafer are isotropically etched to a thickness of 1000 to 1500 angstroms by ion implantation of impurities implanted into the wells and impurities of other conductivity types, / Drain region; And forming a poly spacer on a sidewall of the gate poly to cover the LDD region.

According to this method, a semiconductor device having a channel length of less than a half-micron level and having channel ions implanted only in a channel forming region can be manufactured by using the etching technique, and the resistance to the hot- The increase of the threshold voltage can be suppressed and the current reduction phenomenon between the source and the drain can be prevented.

Description

Method for manufacturing a CMOS semiconductor device

The present invention relates to a method of manufacturing a CMOS semiconductor device, and more particularly, to a method of manufacturing a CMOS semiconductor device, in which a hot-carrier effect is reduced while having a channel length of half microns using an etching technique, To a method of manufacturing a semiconductor device.

As the semiconductor devices are rapidly integrated, CMOS semiconductor devices have also been reduced in size and have channel lengths of micron (micrometer), half micron, and even quarter micron .

However, if the channel length of the device is reduced, the magnitude of the electric field applied to the channel and the hot-carrier effect are increased. In the case of the NMOS device, the threshold voltage V _th increases over time and the drain- I _ds ) is decreased and the device characteristics are deteriorated.

Referring to the cross-sectional view of the conventional CMOS semiconductor device shown in FIG. 1, since a high concentration impurity is present between the gate poly 40 of the NMOS and the source / drain regions 50 and 50a, The hot-carrier effect will occur.

In addition, the semiconductor device having a channel length of less than half-micron level depends greatly on the process capability of the phototool, so that the semiconductor manufacturing process becomes complicated and prolonged.

Thus, the present invention is intended to solve the problems of the prior art, and its object is hot due to the change of the electric field formed in the channel using an etching gisulreul - increasing and the drain of the threshold voltage (V _th) to reduce the carrier effect (CMOS) semiconductor device which can prevent the reduction of the current (I _ds ) between the source and the source.

According to another aspect of the present invention, there is provided a method of manufacturing a CMOS semiconductor device, comprising: forming wells of a first conduction type and a second conduction type near a surface of a semiconductor substrate; Forming an element isolation oxide film on the substrate using an active mask and a LOCOS oxidation method; Forming a gate oxide film on the element region separated by the element isolating oxide film; Sequentially forming a first polysilicon layer and a silicon nitride film on the entire surface of the substrate above the gate oxide film; Etching the silicon nitride film located in the gate poly formation region on the element region to expose the first polysilicon layer; Implanting channel ions into the vicinity of the surface of the substrate (well) through the silicon nitride film opening on the resultant product; Filling an opening portion of the silicon nitride film with a second polysilicon; After removing the silicon nitride film, impurities other than the impurities implanted into the wells are implanted into the wells of the device region using a photo-resist mask, and the first and second polysilicon layers on the wafer are implanted into the first polysilicon layer Forming a source / drain region having an LDD by ion-implanting low-concentration impurities of the same conduction type after isotropic etching until complete removal; Forming a poly spacer on a sidewall of the gate poly to cover the LDD region; And depositing an insulating film on the resultant to form respective electrodes.

1 is a sectional view of a conventional CMOS semiconductor device;

2 is a cross-sectional view of a CMOS semiconductor device according to the present invention;

Figs. 3 to 11 are cross-sectional views of the CMOS semiconductor device shown in Fig. 2,

Description of the Related Art [0002]

10: silicon substrate 20, 22:

30, 32: oxide film 35: silicon nitride film

40, 41: gate poly 42, 44: polysilicon layer

46, 47: poly spacers 50, 50a, 52, 52a: source /

60, 62: photoresist 70: insulating film

80, 80a, 82, 82a:

BRIEF DESCRIPTION OF THE DRAWINGS Fig.

FIG. 2 is a cross-sectional view of a CMOS semiconductor device according to the present invention, and FIGS. 3 to 11 show cross-sectional views of the semiconductor device shown in FIG.

A p-type well 20 and an n-type well 22 are formed in the vicinity of the surface of a conventional silicon substrate 10 and an emmos and a p-mos device region are separated using an active mask and LOCOS (local oxidation of silicon) A gate oxide film 32 is grown on the substrate to a thickness of 150 to 200 angstroms by thermal oxidation on the substrate. A first polysilicon layer 42 having a thickness of 400 to 500 Å and a silicon nitride film 35 having a thickness of 4000 to 5000 Å are sequentially formed on the resultant, The silicon nitride film 35 located at the center of each device region is etched to expose the first polysilicon layer 42 (see FIG. 3).

Next, channel ions are implanted into the vicinity of the substrate surface of each of the wells 20 and 22 through the opening of the silicon nitride film 35 from the upper part of the resultant product. Then, as shown in FIG. 4, The polysilicon on the silicon nitride film 35 is etched and removed using an etch-back method so that the second polysilicon layer 44 is formed only in the opening of the silicon nitride film 35.

Therefore, since the channel ion is injected only in a region where the channel of the device is formed in this process, the electron mobility due to the channel ion in the LDD of the source / drain region to be formed later does not occur.

After the silicon nitride film 35 is completely removed, a photoresist is applied to the entire upper surface of the wafer as shown in FIG. 5, and then exposed and developed so that the photoresist 50 is applied only to the upper surface of the photoresist element region. N + impurity is implanted in the vicinity of the surface of the p-well 20 by using this as a mask. 6, the exposed first and second polysilicon layers 42 and 44 are formed to a thickness of about 500 to 1000 angstroms by isotropic etching while leaving the photoresist 50 as it is, Etch until the first polysilicon layer 42 is completely removed and n-impurity is implanted from the top of the resultant. In this way, the source / drain regions 50 and 50a having LDD (Lightly Doped Drain) are formed.

Since the sidewalls of the second polysilicon layer 44 are etched together using the isotropic etching, the effective gate length of the semiconductor device is reduced, and thus a CMOS semiconductor device having a short-channel length can be manufactured. At this time, the first polysilicon layer 42 acts as a buffer layer for preventing damage to the surface of the substrate 10.

In addition, source / drain regions 50 and 50a can be formed by ion implantation of high-concentration and low-concentration n-type impurities into the emmos region by one photo and development process, that is, by using one photoresist.

Next, after the photoresist 50 is removed, a photoresist 52 is applied to the emmos element region as shown in FIGS. 8, 9 and 10, and the photoresist is applied to the PMOS region using the above- Source / drain regions 52 and 52a are formed.

Next, as shown in FIG. 11, after the photoresist 52 is removed, the polysilicon is deposited to a thickness of 1000 to 1500 ANGSTROM on the resultant and etched by RIE (reactive ion etching) to form first and second polysilicon layers 42 ) 44, that is, the poly spacers 46 and 48 are formed on the side walls of the gate poly 40 (41).

At this time, when the n-type and p-type impurities are injected into the emmos and the pmos regions to form the source / drain regions 50a, 52a and 52a, Or a p-type impurity is doped.

Next, the impurities of the gate poly 40 (41) are doped into the poly spacers 46 and 48 by annealing, and the insulating film 70 is deposited on the resultant by a conventional method, Drain regions, and gate electrodes 80a, 82, and 82a connected to the gate poly.

As described above, according to the present invention, the LDD region of the source / drain region can be formed by using the etching technique without depending on the process capability of the photo equipment in manufacturing the CMOS semiconductor device, Strengthening tolerance. Therefore, the semiconductor device according to the present invention has the effect of suppressing the increase of the threshold voltage when driving the device and also preventing the current between the source and the drain from being reduced.

Claims (2)

Forming wells of a first conduction type and a second conduction type near the surface of the semiconductor substrate and forming a device isolation oxide film thereon; Forming a gate oxide film on the element region separated by the element isolating oxide film; Sequentially forming a first polysilicon layer and a silicon nitride film on the entire surface of the wafer above the gate oxide film; Etching the silicon nitride film located in the gate poly formation region on the element region to expose the first polysilicon layer; Implanting channel ions into the vicinity of the surface of the substrate (well) through the silicon nitride film opening on the resultant product; Filling the openings of the silicon nitride film with polysilicon to form a second polysilicon layer; After the silicon nitride film is removed, the first and second polysilicon layers on the wafer are subjected to isotropic etching so as to completely remove the first polysilicon layer by ion-implanting impurities implanted into the wells and other conductive impurities, Followed by ion implantation of a low concentration impurity to form a source / drain region having an LDD; Forming a poly spacer on a sidewall of the gate poly to cover the LDD region; And forming an electrode by depositing an insulating film on the resultant structure. 2. The method of claim 1, wherein impurity ions are implanted into the wells of each device region to form source / drain regions, and then the polysilicon layer is etched to a thickness of 1000 to 1500 ANGSTROM and ions of a low concentration are implanted. (CMOS) semiconductor device.