[go: up one dir, main page]

KR20010009022A - The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization - Google Patents

The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization Download PDF

Info

Publication number
KR20010009022A
KR20010009022A KR1019990027152A KR19990027152A KR20010009022A KR 20010009022 A KR20010009022 A KR 20010009022A KR 1019990027152 A KR1019990027152 A KR 1019990027152A KR 19990027152 A KR19990027152 A KR 19990027152A KR 20010009022 A KR20010009022 A KR 20010009022A
Authority
KR
South Korea
Prior art keywords
thin film
tin
electromigration
wiring
ulsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019990027152A
Other languages
Korean (ko)
Inventor
최시영
이정환
Original Assignee
최시영
이정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 최시영, 이정환 filed Critical 최시영
Priority to KR1019990027152A priority Critical patent/KR20010009022A/en
Publication of KR20010009022A publication Critical patent/KR20010009022A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체를 이용한 여러 IC소자에 있어 배선공정에서의 일어나는 문제점 중에 하나인 고전류 흐름에 의한 배선 원자의 이동(Electromigration)을 지연시키는 방법을 제시한 것이다.The present invention proposes a method of delaying the movement of wiring atoms due to high current flow, which is one of the problems in the wiring process in various IC devices using semiconductors.

이를 실현시키기 위해 본 발명은 기존의 Cu를 barrier layer인 TiN위에 바로 증착 하지 않고 Al을 수백∼수천 Å정도 우선 증착 하여 TiN과 Cu사이에 고전류 밀도에 의해 발생되어지는 계면간의 열적, 전기적 응력(stress)을 완화시켜주는 역할을 하는 것이다. 또한, Cu증착을 하는데 있어 TiN위에 전기적 저항이 낮은 Al을 사용함으로써 Cu증착을 높여준다.In order to realize this, the present invention does not directly deposit the existing Cu on the barrier layer TiN, but directly deposits Al to several hundreds to thousands of microseconds, so that thermal and electrical stresses between interfaces generated by high current density between TiN and Cu are stressed. ) Is to alleviate). In addition, Cu deposition is enhanced by using Al having low electrical resistance on TiN.

차세대 반도체의 새로운 배선구조형태가 될 trench구조에서도 보다 넓어진 TiN과 Cu간의 면적에 있어 이 방법을 사용함으로써 Electromigration (EM), Stressmigration (SM)에 대하여 높은 지연시간(MTF)을 가질 수 있다.In this trench structure, which will be the new wiring structure of the next-generation semiconductor, this method can have a high delay time (MTF) for Electromigration (EM) and Stressmigration (SM) by using this method in a wider area between TiN and Cu.

Description

차세대 집적회로 배선공정용 동박막의 일렉트로마이그레이션 향상용 알루미늄박막 형성기술{The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization}The Al barrier thin film deposition technology improving for electromigration of ULSI Cu thin film metallization}

본 발명은 반도체용 IC 제작에 적용되는 공정으로서 기존의 배선재료인 Al-alloy대신에 Cu를 사용하여 소자의 고속 스위칭 속도향상과 electromigration에 대한 높은 저항성을 가지고 있다. 그러나, Cu는 TiN과의 계면에서 어떠한 화학적 결합도 이루어지지 않기 때문에 계면에서 발생되어지는 Electromigration(EM), Stress migration(SM)에 관하여 별다른 대안이 없는 실정이다. 따라서, TiN과 화합물을 형성하여 강한 계면 접착력을 가지는 Al barrier를 이용하여 이러한 문제점을 개선하였다.The present invention is a process that is applied to the fabrication of semiconductor ICs using Cu instead of Al-alloy, which is a conventional wiring material, to improve the fast switching speed of the device and have high resistance to electromigration. However, since Cu does not form any chemical bonds at the interface with TiN, there is no alternative to the electromigration (EM) and stress migration (SM) generated at the interface. Therefore, this problem is solved by using an Al barrier having a strong interface adhesion by forming a compound with TiN.

최근의 반도체공정의 가장 큰 흐름은 고집적화에 따르는 선폭의 미세화에 의해 배선에서의 발생되어지는 여러 문제점의 해결이다. 따라서, 기존의 배선물질인 Al-alloy대신에 Cu, Cu-alloy등을 사용함으로써 나름대로 이러한 문제점들을 해결하러하고 있다. 그러나, Cu-alloy같은 경우 차세대 Cu 증착법으로는 문제가 많이 있다.The biggest flow of the recent semiconductor process is to solve various problems that occur in the wiring by miniaturization of the line width due to the high integration. Therefore, by using Cu, Cu-alloy, etc. in place of the existing wiring material Al-alloy to solve these problems in their own way. However, in the case of Cu-alloy, there are many problems with the next-generation Cu deposition method.

따라서, 아직까지 시도된 적이 없는 Al을 증착한 후 화학 기상 증착법(CVD)으로 Cu를 증착하여 기존의 단일 Cu박막보다 우수한 EM특성을 갖게하는 공정을 개발하였다. 이에 관한 연구나 논문이 발표된 바가 없다.Therefore, a process of depositing Al, which has not been tried yet, and then depositing Cu by chemical vapor deposition (CVD), has a superior EM characteristic than a conventional single Cu thin film. No research or paper has been published on this.

본 발명은 상기한 바와 같이 소자의 특성을 저하시키지 않고 종래의 배선에서 발생되어지는 문제점인 Electromigration 에 대하여 TiN위에 Al을 증착하여 높은 저항성을 가지는 배선구조 개발에 목적이 있다. 따라서, Al의 두께가 고속 스위칭속도에 미치지 않는 범위까지 증착하는 기술이 필요로 되어진다.The present invention aims to develop a wiring structure having high resistance by depositing Al on TiN against electromigration, which is a problem caused in conventional wiring, without degrading the characteristics of the device as described above. Therefore, there is a need for a technique for depositing a layer in which the thickness of Al does not reach a high switching speed.

도 1은 본 발명에 의해 형성된 계면 Al barrier 형성기술1 is an interface Al barrier formation technology formed by the present invention

도 2는 본 발명이 적용되어질 차세대 반도체 배선의 구조2 is a structure of a next-generation semiconductor wiring to which the present invention is applied

Sputter법에 의하여 증착된 TiN위에 진공증착법에 의하여 Al을 배선의 저항이 증가하지 않는 범위까지 얇게 수백∼수천Å 증착한 후 화학 기상 증착법(CVD), 또는 전기도금법(Electroplating)으로 Cu를 완전하게 성장시킨다.After depositing hundreds to thousands of thin layers of Al on the TiN deposited by Sputter method to the extent that wiring resistance does not increase, Cu is completely grown by chemical vapor deposition (CVD) or electroplating (Electroplating). Let's do it.

본 발명은 단순히 Electromigration에 대한 저항성을 향상시키는 것 외에 표면의 전기전도도가 높은 물질일수록 화학 기상 증착법(CVD), 전기도금법(Electroplating)에 있어 Cu가 증착이 잘되기 때문에 기존의 TiN보다는 전기전도도가 우수한 Al위에서의 Cu증착이 보다 높은 증착율을 가질 수 있을 것이다. 또한, 앞으로의 배선구조의 형태가 될 trench구조에서는 TiN의 면적이 보다 더 커지므로 본 발명으로 인하여 차세대 반도체 공정에 있어 electromigration대하여 더 높은 저항을 가질 것이다.According to the present invention, in addition to improving resistance to electromigration, the higher the electrical conductivity of the surface, the better the electrical conductivity than the conventional TiN because Cu is better deposited in chemical vapor deposition (CVD) and electroplating (Electroplating). Cu deposition on Al may have a higher deposition rate. In addition, the trench structure, which will be the form of the wiring structure in the future, will have a higher resistance against electromigration in the next-generation semiconductor process because the TiN area becomes larger.

Claims (1)

집적회로의 배선구조에서 barrier layer(TiN, TaN, W 등..)위에 Al barrier를 수백∼수천Å 증착한 후 Cu를 증착하는 일련의 모든 방법A series of methods for depositing Cu after depositing hundreds to thousands of layers of Al barrier on the barrier layer (TiN, TaN, W, etc.) in the integrated circuit wiring structure
KR1019990027152A 1999-07-01 1999-07-01 The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization Withdrawn KR20010009022A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990027152A KR20010009022A (en) 1999-07-01 1999-07-01 The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990027152A KR20010009022A (en) 1999-07-01 1999-07-01 The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization

Publications (1)

Publication Number Publication Date
KR20010009022A true KR20010009022A (en) 2001-02-05

Family

ID=19599776

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990027152A Withdrawn KR20010009022A (en) 1999-07-01 1999-07-01 The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization

Country Status (1)

Country Link
KR (1) KR20010009022A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100420598B1 (en) * 2001-11-28 2004-03-02 동부전자 주식회사 Method for formation copper diffusion barrier a film by using aluminum

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100420598B1 (en) * 2001-11-28 2004-03-02 동부전자 주식회사 Method for formation copper diffusion barrier a film by using aluminum

Similar Documents

Publication Publication Date Title
US7875977B2 (en) Barrier layers for conductive features
KR100329052B1 (en) Enhanced cvd copper adhesion by two-step deposition process
JP3793144B2 (en) Method for forming copper diffusion prevention film using aluminum
US6331484B1 (en) Titanium-tantalum barrier layer film and method for forming the same
JPH07321111A (en) Method of forming electroless plated interconnection for integrated circuit
CN102768985A (en) Damascus manufacturing method with air clearances
KR100896159B1 (en) Semiconductor device and method for manufacturing same
KR100559030B1 (en) Copper metal wiring formation method of semiconductor device
KR20010009022A (en) The Al barrier thin film deposition Technology improving for electromigration of ULSI Cu thin film metallization
KR101132700B1 (en) Metal wiring of semiconductor device and method of manufacturing the same
KR100973277B1 (en) Metal wiring of semiconductor device and method of forming the same
KR100430684B1 (en) Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer
KR100710201B1 (en) Metal wiring formation method of semiconductor device
JP2001319930A (en) Method of manufacturing semiconductor device
KR100633685B1 (en) Metal wiring formation method of semiconductor device
KR0142796B1 (en) Method of forming the multilayng wiring on the semiconductor device
KR100223748B1 (en) Metal wiring formation method of semiconductor device
KR100223332B1 (en) Forming method for metalization of semiconductor device
KR100494320B1 (en) Diffusion prevention film formation method of semiconductor device
KR100309811B1 (en) Metal wiring formation method of semiconductor device
KR100289685B1 (en) Metallization of semeconductor device
KR940002766B1 (en) How to Form Flat Metal Wiring
KR100197665B1 (en) Forming method for metal wiring in semiconductor device
KR101005739B1 (en) Metal wiring formation method of semiconductor device
KR19980060532A (en) Metal wiring formation method of semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19990701

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid