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KR101005739B1 - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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KR101005739B1
KR101005739B1 KR1020030047629A KR20030047629A KR101005739B1 KR 101005739 B1 KR101005739 B1 KR 101005739B1 KR 1020030047629 A KR1020030047629 A KR 1020030047629A KR 20030047629 A KR20030047629 A KR 20030047629A KR 101005739 B1 KR101005739 B1 KR 101005739B1
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metal
aluminum
titanium
alloy layer
tial
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KR20050007983A (en
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조영아
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 티타늄(Ti), 알루미늄(Al), 티타늄(Ti), 알루미늄(Al) 및 티타늄 나이트라이드(TiN)를 연속적으로 증착하되, 고온에서의 알루미늄(Al) 증착 과정에서 티타늄(Ti)과 알루미늄(Al)의 반응에 의해 알루미늄 합금층(TiAl3)이 형성되도록 한다. 따라서 알루미늄(Al)으로 이루어진 금속층의 상부 및 하부에는 합금층(TiAl3)이 형성되며, 최상부에는 합금층(TiAl3)과 티타늄 나이트라이드(TiN)로 이루어진 반사방지막이 형성된다. 본 발명에 따르면 합금층(TiAl3)에 의해 금속배선과 상, 하부층 간의 접착력이 향상되며, 알루미늄(Al) 원자의 이동이 억제되어 소자의 신뢰성이 향상된다. 또한, 금속 원자의 이동에 의해 금속배선에 보이드가 형성된다고 하더라도 합금층(TiAl3)의 저항이 티타늄(Ti)이나 티타늄 나이트라이드(TiN)보다 작기 때문에 반사방지막을 통한 전류의 흐름이 발생되더라도 배선 저항의 급격한 증가가 방지된다. The present invention relates to a method for forming a metal wiring of a semiconductor device, while continuously depositing titanium (Ti), aluminum (Al), titanium (Ti), aluminum (Al) and titanium nitride (TiN), at a high temperature In the (Al) deposition process, an aluminum alloy layer (TiAl 3 ) is formed by reaction of titanium (Ti) and aluminum (Al). Therefore, an alloy layer TiAl 3 is formed on the upper and lower portions of the metal layer made of aluminum (Al), and an antireflection film formed of an alloy layer (TiAl 3 ) and titanium nitride (TiN) is formed on the top. According to the present invention, the adhesion between the metal wiring and the upper and lower layers is improved by the alloy layer TiAl 3 , and the movement of aluminum (Al) atoms is suppressed, thereby improving the reliability of the device. In addition, even though voids are formed in the metal wiring due to the movement of metal atoms, the resistance of the alloy layer TiAl 3 is smaller than that of titanium (Ti) or titanium nitride (TiN). A sharp increase in resistance is prevented.

알루미늄 금속배선, 반사방지막, Ti/Al/TiN, EM, 저항Aluminum metal wiring, antireflection film, Ti / Al / TiN, EM, resistance

Description

반도체 소자의 금속배선 형성 방법 {Method for forming metal wires in a semiconductor device} Method for forming metal wires in a semiconductor device             

도 1a 내지 도 1c는 종래 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도. 1A to 1C are cross-sectional views illustrating a metal wiring forming method of a conventional semiconductor device.

도 2는 종래 반도체 소자의 금속배선에서 전자의 이동을 설명하기 위한 부분 단면도.2 is a partial cross-sectional view for explaining the movement of electrons in the metal wiring of the conventional semiconductor device.

도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도. 3A to 3D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1, 21: 반도체 기판 2, 22: 절연막1, 21: semiconductor substrate 2, 22: insulating film

3, 23, 25: 티타늄 4, 24, 26: 알루미늄3, 23, 25: titanium 4, 24, 26: aluminum

5, 11: 반사방지막 5a: 티타늄5, 11: antireflection film 5a: titanium

5b, 27: 티타늄 나이트라이드 10: 하부 금속배선5b, 27: titanium nitride 10: lower metal wiring

12: 플러그 13: 상부 금속배선12: Plug 13: upper metal wiring

14: 보이드 23a, 25a: 알루미늄 합금층
14: void 23a, 25a: aluminum alloy layer

본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 더욱 상세하게는 금속층의 상부 및 하부에 합금층을 형성하여 금속 원자의 이동을 억제하는 동시에 배선의 저항이 감소되도록 한 반도체 소자의 금속배선 형성 방법에 관한 것이다.
The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to form an alloy layer on the top and bottom of the metal layer to suppress the movement of metal atoms and at the same time to reduce the resistance of the wiring metal wiring formation of the semiconductor device It is about a method.

일반적으로 반도체 소자의 제조 공정에서 금속배선을 형성하는 과정은 다음과 같다.In general, a process of forming metal wiring in a semiconductor device manufacturing process is as follows.

도 1a에 도시된 바와 같이 소정의 공정을 거친 반도체 기판(1) 상에 절연막(2)을 형성한 후 절연막(2) 상에 티타늄(Ti; 3)을 증착한다. 도 1b와 같이 티타늄(Ti; 3) 상에 알루미늄(Al; 4)을 증착한다. 이 때 알루미늄(Al; 4)이 고온에서 증착되기 때문에 하부의 티타늄(Ti; 3)과 알루미늄(Al; 4)의 반응에 의해 알루미늄 합금층(TiAl3; 3a)이 형성된다. 이 후 도 1c와 같이 알루미늄(Al; 4) 상에 티타늄(Ti; 5a)과 티타늄 나이트라이드(TiN; 5b)로 이루어진 반사방지막(Anti Reflection Coating Layer; ARC)(5)을 형성한다.As shown in FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1 that has undergone a predetermined process, and then titanium (Ti) 3 is deposited on the insulating film 2. As shown in FIG. 1B, aluminum (Al) 4 is deposited on titanium (Ti) 3. At this time, since aluminum (Al; 4) is deposited at a high temperature, an aluminum alloy layer (TiAl 3 ; 3a) is formed by the reaction of titanium (Ti; 3) and aluminum (Al; 4) in the lower portion. Thereafter, as shown in FIG. 1C, an anti reflection coating layer (ARC) 5 including titanium (Ti; 5a) and titanium nitride (TiN; 5b) is formed on aluminum (Al) 4.

반도체 소자의 제조 과정에서는 상기와 같이 금속배선을 형성한 후 배선의 전기적 신뢰성을 테스트하기 위해 전자 이동도(Electro Migration)를 평가하게 된 다. 전자 이동도를 평가하기 위해서는 금속배선에 높은 전류 및 고온을 인가하여 금속배선을 통한 전자(e-)의 이동이 발생되도록 한다.In the process of manufacturing a semiconductor device, as described above, after the metal wiring is formed, electron migration is evaluated to test the electrical reliability of the wiring. In order to evaluate electron mobility, high current and high temperature are applied to the metal wires so that the electrons (e-) move through the metal wires.

그런데 상기와 같이 금속배선을 형성하면 도 2와 같이 하부 금속배선(10)과 상부 금속배선(13)을 연결하는 비아(Via)의 플러그(12) 경계면에서 알루미늄(Al) 원자의 이동이 시작되기 때문에 예를 들어, 하부 금속배선(10)의 내부 쪽으로 보이드(Void; 14)가 형성되기 시작한다. 이러한 보이드(14)는 금속배선(10) 내부로 ~수십 ㎛ 크기로 증가되는데, 보이드(14)가 형성되어도 일정 시간(Tf)까지는 금속배선(10)을 통해 전류가 흐르게 되지만, 보이드(14)가 커지면 전류가 알루미늄(Al)보다 저항이 큰 반사방지막(11)을 통해 흐르게 되기 때문에 배선의 저항이 급격하게 증가된다. 이러한 현상을 분로층(Shunt layer) 효과라 하는데, 이와 같은 문제점으로 인해 소자의 전기적 특성 및 신뢰성이 저하될 수 있기 때문에 알루미늄(Al)의 구조와 방향성, 그레인 크기, 두께 등을 고려하는 것도 중요하지만 반사방지막의 재질과 구조도 중요하다.
However, when the metal wiring is formed as described above, the movement of aluminum atoms starts at the interface of the plug 12 of the via connecting the lower metal wiring 10 and the upper metal wiring 13 as shown in FIG. 2. Thus, for example, voids 14 begin to form toward the inside of the lower metallization 10. The voids 14 are increased to a size of several tens of micrometers inside the metal wires 10. Even though the voids 14 are formed, current flows through the metal wires 10 until a predetermined time Tf, but the voids 14 are formed. The larger the value, the more the current flows through the antireflection film 11 having a larger resistance than that of aluminum (Al), so that the resistance of the wiring increases rapidly. This phenomenon is called the shunt layer effect. It is also important to consider the structure, orientation, grain size, thickness, etc. of aluminum (Al) because the electrical characteristics and reliability of the device may be deteriorated due to such a problem. The material and structure of the antireflection film is also important.

따라서 본 발명은 금속층의 상부 및 하부에 합금층이 형성되도록 함으로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는 데 그 목적이 있다.
Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can solve the above disadvantages by allowing the alloy layer to be formed on the top and bottom of the metal layer.

상기한 목적을 달성하기 위한 본 발명은 절연막이 형성된 반도체 기판 상에 제 1 금속 및 제 2 금속을 순차적으로 증착하되, 상기 제 1 금속과 제 2 금속의 반응에 의해 상기 제 2 금속의 하부에 제1 합금층이 형성되도록 하는 단계와, 상기 제 2 금속 상에 제 3 금속 및 제 4 금속을 순차적으로 형성하되, 상기 제 3 금속과 제 4 금속의 반응에 의해 상기 제 2 금속의 상부에 제2 합금층이 형성되도록 하는 단계와, 상기 제2 합금층 상에 제 5 금속을 증착하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially deposits a first metal and a second metal on a semiconductor substrate on which an insulating film is formed, and is formed under the second metal by a reaction of the first metal and the second metal. Forming an alloy layer, and sequentially forming a third metal and a fourth metal on the second metal, wherein the second metal is formed on the second metal by reaction of the third metal and the fourth metal. And forming an alloy layer, and depositing a fifth metal on the second alloy layer.

상기 제 1 금속 및 제 3 금속은 티타늄(Ti)이며, 상기 제 2 금속 및 제 4 금속은 알루미늄(Al)이고, 상기 제 5 금속은 티타늄 나이트라이드(TiN)인 것을 특징으로 한다.The first metal and the third metal are titanium (Ti), the second metal and the fourth metal are aluminum (Al), and the fifth metal is titanium nitride (TiN).

상기 제2 합금층 및 제 5 금속이 반사방지막으로 이용되며, 상기 제1 및 제2 합금층은 TiAl3인 것을 특징으로 한다.The second alloy layer and the fifth metal are used as an antireflection film, and the first and second alloy layers are TiAl 3 .

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도이다.3A to 3D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

도 3a를 참조하면, 소정의 공정을 거친 반도체 기판(21) 상에 절연막(22)을 형성한 후 절연막(22) 상에 10 내지 100Å 두께의 티타늄(Ti; 23)을 증착한다. Referring to FIG. 3A, an insulating film 22 is formed on a semiconductor substrate 21 that has been subjected to a predetermined process, and then titanium (Ti) 23 having a thickness of 10 to 100 Å is deposited on the insulating film 22.

도 3b를 참조하면, 상기 티타늄(Ti; 23) 상에 알루미늄(Al; 24)을 증착한다. 이 때 알루미늄(Al; 24)이 고온에서 증착되기 때문에 하부의 티타늄(Ti; 23)과 알루미늄(Al; 24)의 반응에 의해 알루미늄 합금층(TiAl3; 23a)이 형성된다. Referring to FIG. 3B, aluminum (Al) 24 is deposited on the titanium 23. At this time, since aluminum (Al; 24) is deposited at a high temperature, an aluminum alloy layer (TiAl 3 ; 23a) is formed by the reaction of titanium (Ti; 23) and aluminum (Al; 24) in the lower portion.

도 3c를 참조하면, 상기 알루미늄(Al; 24) 상에 10 내지 100Å 두께의 티타늄(Ti; 25) 및 알루미늄(Al; 26)을 순차적으로 형성한다. Referring to FIG. 3C, titanium (Ti) 25 and aluminum (Al) 26 having a thickness of 10 to 100 μm are sequentially formed on the aluminum (Al) 24.

도 3d를 참조하면, 상기 알루미늄(Al; 26)을 증착하는 과정에서 고온에서의 티타늄(Ti; 25)과 알루미늄(Al; 26)의 반응에 의해 알루미늄 합금층(TiAl3; 25a)이 형성된다. 따라서 상기 알루미늄(Al; 26)은 상기 티타늄(Ti; 25)과의 반응에 의해 모두 소모될 정도의 두께, 예를 들어, 30 내지 300Å 정도로 형성되어야 한다.Referring to FIG. 3D, an aluminum alloy layer TiAl 3 ; 25a is formed by reaction of titanium (Ti) 25 and aluminum (Al; 26) at a high temperature in the process of depositing the aluminum (Al) 26. . Therefore, the aluminum (Al) 26 should be formed to a thickness such that all of them are consumed by the reaction with the titanium (Ti; 25), for example, about 30 to 300 kPa.

이 후 알루미늄 합금층(TiAl3; 25a) 상에 티타늄 나이트라이드(TiN; 27)를 증착하여 알루미늄 합금층(TiAl3; 15a)과 티타늄 나이트라이드(TiN; 17)로 이루어진 반사방지막의 형성을 완료하고, 사진 및 식각 공정으로 패터닝하여 금속배선을 형성한다.Thereafter, titanium nitride (TiN) 27 is deposited on the aluminum alloy layer (TiAl 3 ; 25a), thereby completing the formation of an anti-reflection film including the aluminum alloy layer (TiAl 3 ; 15a) and titanium nitride (TiN; 17). And metallization is formed by patterning by photo and etching processes.

본 발명에서 티타늄(Ti; 23), 알루미늄(Al; 24), 티타늄(Ti; 25), 알루미늄(Al; 26) 및 티타늄 나이트라이드(TiN; 27)는 연속적인 공정으로 증착하며, 고온에서의 알루미늄(Al) 증착 과정에서 티타늄(Ti)과 알루미늄(Al)의 반응에 의해 알루미늄 합금층(TiAl3)이 형성되기 때문에 합금층 형성을 위한 별도의 열처리는 실시하지 않아도 된다.In the present invention, titanium (Ti; 23), aluminum (Al; 24), titanium (Ti; 25), aluminum (Al; 26), and titanium nitride (TiN; 27) are deposited in a continuous process, and at high temperatures. Since the aluminum alloy layer TiAl 3 is formed by the reaction of titanium (Ti) and aluminum (Al) in the aluminum (Al) deposition process, a separate heat treatment for forming the alloy layer does not need to be performed.

상기와 같이 본 발명은 반사방지막(ARC)을 티타늄(Ti)/알루미늄(Al)/티타늄 나이트라이드(TiN)가 적층된 구조로 형성하되, 고온에서의 알루미늄(Al) 증착 과정에서 알루미늄(Al)과 티타늄(Ti)의 반응에 의해 상부 및 하부에 알루미늄 합금층(TiAl3)이 형성되도록 한다. 따라서 알루미늄 합금층(TiAl3)에 의해 금속배선과 상,하부층 간의 접착력이 향상되며, 알루미늄(Al) 원자의 이동이 억제되어 소자의 신뢰성이 향상된다. 만일 원자의 이동에 의해 금속배선에 보이드가 형성된다고 하더라도 알루미늄 합금층(TiAl3)의 저항(μΩ-㎝)이 하기와 같이 티타늄(Ti)이나 티타늄 나이트라이드(TiN)보다 작기 때문에 반사방지막 즉, 알루미늄 합금층(TiAl3)/티타늄 나이트라이드(TiN)를 통한 전류의 흐름에 의해 배선 저항의 급격한 증가가 방지된다. As described above, in the present invention, the anti-reflection film (ARC) is formed in a structure in which titanium (Ti) / aluminum (Al) / titanium nitride (TiN) is stacked, and aluminum (Al) is deposited during the deposition of aluminum (Al) at a high temperature. The aluminum alloy layer TiAl 3 is formed on and under the reaction of titanium with Ti. Therefore, the adhesion between the metal wiring and the upper and lower layers is improved by the aluminum alloy layer TiAl 3 , and the movement of aluminum (Al) atoms is suppressed, thereby improving the reliability of the device. Even if voids are formed in the metal wiring by the movement of atoms, the resistance (μΩ-cm) of the aluminum alloy layer (TiAl 3 ) is smaller than that of titanium (Ti) or titanium nitride (TiN) as follows. The rapid increase in wiring resistance is prevented by the flow of current through the aluminum alloy layer (TiAl 3 ) / titanium nitride (TiN).

Al: 2 ~ 4 > TiAl3: 4 ~ 8 >> Ti: 50 ~ 60 > TiN: 50 ~ 100
Al: 2 to 4> TiAl 3 : 4 to 8 >> Ti: 50 to 60> TiN: 50 to 100

상술한 바와 같이 본 발명은 티타늄(Ti), 알루미늄(Al), 티타늄(Ti), 알루미늄(Al) 및 티타늄 나이트라이드(TiN)를 연속적으로 증착하되, 고온에서의 알루미늄(Al) 증착 과정에서 티타늄(Ti)과 알루미늄(Al)의 반응에 의해 알루미늄 합금층(TiAl3)이 형성되도록 한다. 따라서 알루미늄(Al)으로 이루어진 금속층의 상부 및 하부에는 합금층(TiAl3)이 형성되며, 최상부에는 합금층(TiAl3)과 티타늄 나이트라이드(TiN)로 이루어진 반사방지막이 형성된다. As described above, the present invention continuously deposits titanium (Ti), aluminum (Al), titanium (Ti), aluminum (Al), and titanium nitride (TiN), while titanium is deposited at a high temperature in the process of aluminum (Al) deposition. The aluminum alloy layer TiAl 3 is formed by the reaction of Ti and aluminum. Therefore, an alloy layer TiAl 3 is formed on the upper and lower portions of the metal layer made of aluminum (Al), and an antireflection film formed of an alloy layer (TiAl 3 ) and titanium nitride (TiN) is formed on the top.

본 발명에 따르면 합금층(TiAl3)에 의해 금속배선과 상,하부층 간의 접착력이 향상되며, 알루미늄(Al) 원자의 이동이 억제되어 소자의 신뢰성이 향상된다. 또한, 원자의 이동에 의해 금속배선에 보이드가 형성된다고 하더라도 합금층(TiAl3)의 저항이 티타늄(Ti)이나 티타늄 나이트라이드(TiN)보다 작기 때문에 반사방지막을 통한 전류의 흐름이 이루어지더라도 배선 저항의 급격한 증가가 방지된다.
According to the present invention, the adhesion between the metal wiring and the upper and lower layers is improved by the alloy layer TiAl 3 , and the movement of aluminum (Al) atoms is suppressed, thereby improving the reliability of the device. In addition, even though voids are formed in the metal wiring by the movement of atoms, the resistance of the alloy layer TiAl 3 is smaller than that of titanium (Ti) or titanium nitride (TiN). A sharp increase in resistance is prevented.

Claims (5)

절연막이 형성된 반도체 기판 상에 제 1 금속 및 제 2 금속을 순차적으로 증착하되, 상기 제 1 금속과 제 2 금속의 반응에 의해 상기 제 2 금속의 하부에 제1 합금층이 형성되도록 하는 단계와,Sequentially depositing a first metal and a second metal on the semiconductor substrate on which the insulating film is formed, wherein a first alloy layer is formed below the second metal by a reaction of the first metal and the second metal; 상기 제 2 금속 상에 제 3 금속 및 제 4 금속을 순차적으로 형성하되, 상기 제 3 금속과 제 4 금속의 반응에 의해 상기 제 2 금속의 상부에 제2 합금층이 형성되도록 하는 단계와,Sequentially forming a third metal and a fourth metal on the second metal, wherein a second alloy layer is formed on the second metal by reaction of the third metal and the fourth metal; 상기 제2 합금층 상에 제 5 금속을 증착하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.And depositing a fifth metal on the second alloy layer. 제 1 항에 있어서, 상기 제2 합금층 및 제 5 금속이 반사방지막으로 이용되는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.2. The method of claim 1, wherein the second alloy layer and the fifth metal are used as antireflection films. 제 1 항에 있어서, 상기 제 1 금속 및 제 3 금속은 티타늄(Ti)이며, 상기 제 2 금속 및 제 4 금속은 알루미늄(Al)이고, 상기 제 5 금속은 티타늄 나이트라이드(TiN)인 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 1, wherein the first metal and the third metal are titanium (Ti), the second metal and the fourth metal are aluminum (Al), and the fifth metal is titanium nitride (TiN). A metal wiring forming method of a semiconductor device. 제 1 항에 있어서, 상기 제1 및 제2 합금층은 TiAl3인 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 1, wherein the first and second alloy layers are TiAl 3 . 제 1 항에 있어서, 상기 제 1 금속 및 제 3 금속은 10 내지 100Å의 두께로 형성하고, 상기 제 4 금속은 30 내지 300Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The method of claim 1, wherein the first metal and the third metal are formed to a thickness of 10 to 100 kPa, and the fourth metal is formed to a thickness of 30 to 300 kPa.
KR1020030047629A 2003-07-12 2003-07-12 Metal wiring formation method of semiconductor device Expired - Fee Related KR101005739B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010058941A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a metal line of a semiconductor device
KR20020003016A (en) * 2000-06-30 2002-01-10 박종섭 Method for manufacturing multi-thin film metal layer
KR20020068569A (en) * 2001-02-21 2002-08-28 동부전자 주식회사 Method for manufacturing multi-layered metal line of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010058941A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a metal line of a semiconductor device
KR20020003016A (en) * 2000-06-30 2002-01-10 박종섭 Method for manufacturing multi-thin film metal layer
KR20020068569A (en) * 2001-02-21 2002-08-28 동부전자 주식회사 Method for manufacturing multi-layered metal line of semiconductor device

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