KR20010008432A - Method for manufacturing capacitor having high dielectric ta2o5 thin film - Google Patents
Method for manufacturing capacitor having high dielectric ta2o5 thin film Download PDFInfo
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- KR20010008432A KR20010008432A KR1019980062525A KR19980062525A KR20010008432A KR 20010008432 A KR20010008432 A KR 20010008432A KR 1019980062525 A KR1019980062525 A KR 1019980062525A KR 19980062525 A KR19980062525 A KR 19980062525A KR 20010008432 A KR20010008432 A KR 20010008432A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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Abstract
본 발명은 고유전체 Ta2O5막을 갖는 반도체장치의 커패시터 형성방법에 관한 것으로서, 특히 이 방법은 반도체 소자를 구비한 반도체기판 상부에 소자간 절연을 위한 층간 절연막의 콘택홀을 통해 상기 반도체 소자와 연결되며 비정질 도프트 실리콘 내지 결정화된 도프트 폴리실리콘으로 이루어진 하부전극을 형성하는 단계와, 하부전극 상부면에 탄탈륨질화막을 형성하는 단계와, 탄탈륨질화막 상부면에 Ta2O5막을 형성하는 단계와, Ta2O5막 상부면에 도전층으로 이루어진 상부전극을 형성하는 단계를 이루어진다. 따라서, 본 발명은 하부전극을 형성한 후 그 표면에 내산화성과 열적 안정성이 우수한 탄탈륨질화막을 형성함으로써 고유전체막의 정전용량 및 누설전류 특성을 개선할 수 있다.The present invention relates to a method of forming a capacitor of a semiconductor device having a high-k dielectric Ta 2 O 5 film, and more particularly, to a method of forming a capacitor through a contact hole of an interlayer insulating film for inter-device insulation on a semiconductor substrate having a semiconductor device. Forming a bottom electrode connected to and formed of amorphous doped silicon or crystallized doped polysilicon, forming a tantalum nitride film on an upper surface of the lower electrode, and forming a Ta 2 O 5 film on an upper surface of the tantalum nitride film; And forming an upper electrode formed of a conductive layer on an upper surface of the Ta 2 O 5 film. Therefore, the present invention can improve the capacitance and leakage current characteristics of the high-k dielectric film by forming a tantalum nitride film having excellent oxidation resistance and thermal stability on its surface after forming the lower electrode.
Description
본 발명은 반도체장치의 커패시터 제조방법에 관한 것으로서, 특히 고집적 반도체장치의 커패시터의 전기적 특성을 향상시킬 수 있는 고유전체 Ta2O5막을 갖는 반도체장치의 커패시터 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device having a high dielectric constant Ta 2 O 5 film capable of improving electrical characteristics of a capacitor of a highly integrated semiconductor device.
현재 반도체 소자는 고집적화를 달성하기 위하여 셀 면적의 감소 및 동작 전압의 저전압화에 관한 연구/개발이 활발하게 진행되고 있다. 더구나 반도체 소자의 고집적화가 이루어질수록 커패시터의 면적은 급격하게 감소되고 있기 때문에 기억소자의 동작에 필요한 전하 즉, 단위 면적에 확보되는 커패시턴스를 더욱 증가시켜야만 한다.At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor is rapidly decreasing, and thus, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.
한편, 메모리 셀에 사용되는 커패시터의 기본 구조는 스토리지(storage)용 하부 전극, 유전체막 및 플레이트(plate)용 상부전극으로 구성된다. 이러한 구조를 가지는 커패시터는 작은 면적 내에서 보다 큰 고정전용량을 얻기 위해서 첫째 얇은 유전체막 두께를 확보하거나, 둘째 3차원적인 커패시터의 구조를 통해서 유효 면적을 증가하거나, 셋째 유전율이 높은 물질을 사용하여 유전체막을 형성하는 등의 몇 가지 조건이 만족되어야만 한다.Meanwhile, the basic structure of the capacitor used in the memory cell is composed of a lower electrode for storage, a dielectric film, and an upper electrode for a plate. Capacitors having such a structure have a first thin dielectric film thickness, a second three-dimensional capacitor structure to increase the effective area, or a third dielectric material in order to obtain a larger capacitance in a small area. Some conditions, such as forming a dielectric film, must be satisfied.
반도체장치의 커패시터는 통상적으로 주어진 유전체막의 두께에서 누설 전류가 적어지면 적어질수록, 파괴 전압이 커지면 커질수록 좋은 유전체막을 얻지만 유전체막의 두께가 100Å 이하로 박막화될 경우 파울러-노드하임(Fowler-Nordheim) 터널링에 의하여 누설 전류가 증가하여 신뢰성이 저하된다. 또한, 커패시터의 유효 면적을 증가시키기 위하여 3차원 구조를 이용해서 하부전극의 단면적을 증가시킬 경우에는 반도체장치의 고집적화에 따른 복잡한 구조로 인해 제조 공정이 어려워지고 있다. 이러한 이유에 의해서 메모리 셀에 이용되는 커패시터는 좁은 면적에서도 고정전용량의 확보가 충분히 이루어질 수 있는 높은 유전율을 가지는 물질을 커패시터의 유전체막으로 이용하는 방법을 주로 사용하고 있다.Capacitors in semiconductor devices generally obtain better dielectric films with less leakage current and larger breakdown voltages at a given dielectric film thickness, but Fowler-Nordheim when the dielectric film becomes thinner than 100 Å. ) The leakage current increases due to tunneling, which lowers the reliability. In addition, when the cross-sectional area of the lower electrode is increased by using a three-dimensional structure to increase the effective area of the capacitor, the manufacturing process becomes difficult due to the complicated structure resulting from the high integration of the semiconductor device. For this reason, the capacitor used in the memory cell mainly uses a method of using a material having a high dielectric constant, which can sufficiently secure a fixed capacitance even in a small area, as the dielectric film of the capacitor.
높은 유전율을 가지는 유전체로는 TiO2, Ta2O5등이 있으며, 이들 중에서 특히 Ta2O5는 화학기상증착법으로 증착하지만 Ta(OC2H5)5와 O2를 소스 가스로 사용하기 때문에 후속 공정 중에 탄소나 수분 등의 불순물이 섞여 있어 이것들이 누설 통로(leakage pass)의 역할을 한다. 또한, 증착한 Ta2O5는비정질 상태이기 때문에 막질이 불량하여 누설 전류가 크기 때문에 보통 Ta2O5증착 후에는 산소공급과 카본 제거를 위하여 O2또는 N2O 가스를 이용한 저온 또는 고온 열처리를 진행하고 있다. 하지만, 하부전극이 폴리실리콘으로 이루어졌을 때 전극들 사이에 내재되는 Ta2O5가 폴리실리콘과 반응하게 되어 산화되는 문제가 발생하게 된다. 하부전극의 자연 산화로 인해 유전체막의 누설 전류가 증가되어 커패시터의 유전체막으로서의 기능이 저하되는 문제점이 있었다.Dielectrics having high dielectric constants include TiO 2 and Ta 2 O 5. Among them, Ta 2 O 5 is deposited by chemical vapor deposition, but Ta (OC 2 H 5 ) 5 and O 2 are used as source gases. During the subsequent process, impurities such as carbon and moisture are mixed, which serves as a leakage pass. In addition, since the deposited Ta 2 O 5 is in an amorphous state, the film quality is poor and the leakage current is large. Therefore, after Ta 2 O 5 deposition, low temperature or high temperature heat treatment using O 2 or N 2 O gas for oxygen supply and carbon removal is performed. Going on. However, when the lower electrode is made of polysilicon, Ta 2 O 5 embedded between the electrodes reacts with the polysilicon, causing oxidation. Due to the natural oxidation of the lower electrode, the leakage current of the dielectric film is increased, thereby degrading the function of the capacitor as the dielectric film.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 고유전율을 가지는 유전체막의 경우 하부전극을 형성한 후 그 표면에 내산화성과 열적 안정성이 우수한 탄탈륨질화물질을 증착함으로써 고유전체막의 정전용량 및 누설전류 특성을 개선할 수 있는 고유전체 Ta2O5막을 갖는 반도체장치의 커패시터 형성방법을 제공하는데 있다.An object of the present invention is to solve the above problems of the prior art by forming a lower electrode in the dielectric film having a high dielectric constant and then depositing a tantalum nitride material excellent in oxidation resistance and thermal stability on the surface of the high dielectric film And a capacitor forming method for a semiconductor device having a high dielectric constant Ta 2 O 5 film capable of improving leakage current characteristics.
도 1 내지 도 5는 본 발명에 따른 고유전체 Ta2O5막을 갖는 반도체장치의 커패시터 형성방법을 설명하기 위한 공정 순서도.1 to 5 are process flowcharts illustrating a capacitor forming method of a semiconductor device having a high dielectric Ta 2 O 5 film according to the present invention.
*도면의 주요 부분에 대한 부호 설명** Description of symbols on the main parts of the drawings *
10: 실리콘 기판 20: 층간 절연막10 silicon substrate 20 interlayer insulating film
30: 하부전극 32: 탄탈륨질화막30: lower electrode 32: tantalum nitride film
34: 포토레지스트 패턴 36: 고유전체막34: photoresist pattern 36: high dielectric film
38: 상부 전극38: upper electrode
상기 목적을 달성하기 위하여 본 발명은 반도체기판의 활성영역과 접촉하는 하부 전극과 그 위의 고유전체 Ta2O5막 및 상부전극으로 이루어진 커패시터를 형성함에 있어서, 반도체 소자를 구비한 반도체기판 상부에 소자간 절연을 위한 층간 절연막의 콘택홀을 통해 상기 반도체 소자와 연결되며 비정질 도프트 실리콘 내지 결정화된 도프트 폴리실리콘으로 이루어진 하부전극을 형성하는 단계와, 상기 결과물에 탄탈륨질화막을 증착하고 메모리 셀사이의 탄탈륨질화막만을 선택적으로 제거하여 상기 하부전극 상부면에만 탄탈륨질화막을 남기는 단계와, 탄탈륨질화막 상부면에 Ta2O5막을 형성하는 단계와, Ta2O5막 상부면에 도전층으로 이루어진 상부전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a capacitor including a lower electrode in contact with an active region of a semiconductor substrate, a high dielectric Ta 2 O 5 film, and an upper electrode thereon, the upper portion of the semiconductor substrate having a semiconductor element. Forming a lower electrode connected to the semiconductor device through a contact hole of an interlayer insulating film for inter-device insulation and made of amorphous doped silicon or crystallized doped polysilicon, depositing a tantalum nitride film on the resultant, and Selectively removing only the tantalum nitride film, leaving a tantalum nitride film only on the upper surface of the lower electrode; forming a Ta 2 O 5 film on the upper surface of the tantalum nitride film; and an upper electrode comprising a conductive layer on the upper surface of the Ta 2 O 5 film. Characterized in that it comprises a step of forming.
본 발명에 따라 고유전체 Ta2O5막을 갖는 반도체장치의 커패시터 형성방법은, 탄탈륨질화막 형성 공정시 웨이퍼의 가열온도를 350℃∼450℃ 조건으로 하며 반응챔버의 압력을 0.1∼2Torr 조건으로 하고, 이때 탄탈륨질화막의 두께는 20∼200Å로 하는 것이 바람직하다.In the method of forming a capacitor of a semiconductor device having a high dielectric Ta 2 O 5 film according to the present invention, the heating temperature of the wafer is 350 ° C. to 450 ° C. during the tantalum nitride film forming step, and the pressure of the reaction chamber is 0.1 to 2 Torr. At this time, it is preferable that the thickness of a tantalum nitride film shall be 20-200 GPa.
또한, 탄탈륨질화막 형성 공정은 TaCl5및 NH3을 이용하며 TaCl5를 100℃ 이상으로 유지되는 기화기에서 기화시킨 후 공급하고 NH3을 1∼50slm 정도 주입하는 것을 특징으로 한다. 이때, 탄탈륨질화막의 반응 원료로서 Ta(OC2H5)5와 NH3을 이용할 수도 있다.In addition, the tantalum nitride film forming process is characterized in that by using TaCl 5 and NH 3 , and after supplying TaCl 5 in a vaporizer maintained at 100 ° C. or more, injecting NH 3 to about 1 to 50 slm. At this time, Ta (OC 2 H 5 ) 5 and NH 3 may be used as the reaction raw material of the tantalum nitride film.
본 발명에 따르면, 고유전율 Ta2O5막을 증착하기 전에 하부 전극위에 탄탈륨질화막을 추가 형성하기 때문에 상기 탄탈륨질화막이 하부전극의 자연 산화로 인해 유전체막의 누설 전류가 증가되는 것을 막아서 커패시터의 전기적 특성을 향상시킬 수 있고, 유전체막 형성전에 실시하는 전처리 공정을 스킵(skip)할 수 있어 제조 공정수를 줄일 수 있다.According to the present invention, since the tantalum nitride film is further formed on the lower electrode before the high dielectric constant Ta 2 O 5 film is deposited, the tantalum nitride film prevents the leakage current of the dielectric film from increasing due to the natural oxidation of the lower electrode, thereby improving the electrical characteristics of the capacitor. It is possible to improve and skip the pretreatment step performed before the dielectric film is formed, thereby reducing the number of manufacturing steps.
이하, 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 고유전체 Ta2O5막을 갖는 반도체장치의 커패시터 형성방법을 설명하기 위한 공정 순서도로서, 본 발명의 커패시터 제조 공정은 다음과 같다.1 to 5 are flowcharts illustrating a method of forming a capacitor in a semiconductor device having a high-k dielectric Ta 2 O 5 film according to the present invention. The capacitor manufacturing process of the present invention is as follows.
우선, 도 1에 도시된 바와 같이 반도체기판으로서 실리콘 기판(10)의 활성 영역 상부면에 게이트 전극, 소스/드레인을 갖는 반도체소자(도시하지 않음)를 형성하고, 그 기판(10) 전면에 USG(Undoped Silicate Glass), BPSG(Boro Phospho Silicate Glass) 및 SiON 중에서 선택한 물질을 증착하고 화학적기계적연마(Chemical Mechanical Polishing) 공정을 실시하여 층간 절연막(20)을 형성한다. 그 다음 기판(10)의 활성영역 즉, 드레인 영역과 접촉하는 커패시터의 단면적을 확보하기 위하여 사진 및 식각 공정으로 상기 층간 절연막(20)을 선택 식각하여 콘택홀(도시하지 않음)을 형성하고, 도프트 폴리실리콘(doped poly silicon)으로 상기 콘택홀을 매립하도록 증착하고 이를 패터닝하여 하부전극(30)을 형성한다. 이때, 상기 하부전극(30)의 면적을 증가하기 위하여 도프트 폴리실리콘(doped poly silicon) 대신에 비정질 실리콘(amorphous silicon)을 사용해서 선택적인 준안정폴리실리콘(metastable polysilicon)으로 성장시킨다. 이때는 막내에 P(phosphorus)가 부족하여 커패시턴스의 작아지기 때문에 충분한 P를 공급하기 위하여 PH3처리를 실시해준다.First, as shown in FIG. 1, a semiconductor device (not shown) having a gate electrode and a source / drain is formed on an upper surface of an active region of a silicon substrate 10 as a semiconductor substrate, and USG is formed on the entire surface of the substrate 10. (Undoped Silicate Glass), a material selected from Boro Phospho Silicate Glass (BPSG), and SiON is deposited and a chemical mechanical polishing process is performed to form an interlayer insulating film 20. Then, in order to secure the cross-sectional area of the capacitor in contact with the active region of the substrate 10, that is, the drain region, the interlayer insulating layer 20 is selectively etched by photolithography and etching to form a contact hole (not shown), and then The bottom electrode 30 is formed by depositing and patterning the contact hole with doped poly silicon. At this time, in order to increase the area of the lower electrode 30, instead of doped polysilicon, amorphous silicon is used to grow into selective metastable polysilicon. At this time, since P (phosphorus) is insufficient in the membrane and the capacitance is reduced, PH 3 treatment is performed to supply sufficient P.
이어서 도 2에 도시된 바와 같이 실리더형 구조의 하부전극(30) 위에 탄탈륨질화물(32)을 20∼200Å의 두께로 증착하는데, 반응 원료로는 TaCl5를 100℃이상으로 유지되는 기화기에서 기화시킨후 일정량을 반응챔버에 주입함과 동시에 NH3을 1∼50slm 정도 주입한다. 이때, 반응챔버의 조건은 웨이퍼 가열온도 350∼450℃로 유지하고, 압력은 0.1Torr∼2Torr로 한다. 한편, Ta 소스로 TaCl5대신에 Ta(OC2H5)5를 이용할 수 있는데, 이때 공정 조건은 웨이퍼 가열온도를 350∼450℃로 유지하고, 그 압력은 0.1Torr∼1Torr로 하는 것이 바람직하다. 하지만, Ta의 소스로는 Ta(OC2H5)5보다는 TaCl5가 우수한데, 그 이유는 Ta(OC2H5)5가 산소에 의한 Si의 산화가 발생할 수 있기 때문이다.Subsequently, tantalum nitride 32 is deposited to a thickness of 20 to 200 kPa on the lower electrode 30 of the cylinder-type structure, as shown in FIG. 2. As a reaction raw material, TaCl 5 is vaporized in a vaporizer maintained at 100 ° C. or higher. After the injection, a certain amount is injected into the reaction chamber and NH 3 is injected at about 1 to 50 slm. At this time, the conditions of the reaction chamber are maintained at a wafer heating temperature of 350 to 450 ° C., and the pressure is set to 0.1 Torr to 2 Torr. Meanwhile, Ta (OC 2 H 5 ) 5 may be used instead of TaCl 5 as the Ta source. In this case, it is preferable that the process conditions are maintained at a wafer heating temperature of 350 to 450 ° C., and the pressure is 0.1 Torr to 1 Torr. . However, TaCl 5 is superior to Ta (OC 2 H 5 ) 5 as a source of Ta because Ta (OC 2 H 5 ) 5 may cause oxidation of Si by oxygen.
그 다음 도 3 및 도 4에 도시된 바와 같이, 셀 마스크를 이용한 사진 공정을 이용하여 상기 탄탈륨질화막(32)이 형성된 기판 위에 포토레지스트 패턴(34)을 형성하고 식각 공정을 진행하여 커패시터 영역을 제외한 셀 사이에 증착된 탄탈륨질화막(32)을 선택적으로 제거한다. 그 이유는 탄탈륨질화막(32)이 도전성을 갖고 있어 셀 사이에 있는 탄탈륨질화막에 의해 셀과 셀 사이의 단락을 방지하기 위함이다. 그리고, 포토레지스트 페턴(34)을 제거한다.3 and 4, the photoresist pattern 34 is formed on the substrate on which the tantalum nitride film 32 is formed using a photo process using a cell mask, and the etching process is performed to remove the capacitor region. The tantalum nitride film 32 deposited between the cells is selectively removed. The reason is that the tantalum nitride film 32 is conductive and prevents a short circuit between the cells by the tantalum nitride film between the cells. Then, the photoresist pattern 34 is removed.
그 다음 도 5에 도시된 바와 같이 고유전물질인 Ta(OC2H5)5와 O2가스를 이용한 저온 화학기상증착법(low pressure chemical vapor deposition)으로 탄탈륨질화막(32)위에 Ta2O5막(36)을 형성한다. 여기서 Ta2O5막(36)을 형성하기 위한 웨이퍼의 가열 온도는 350∼450℃로 유지하며 반응챔버내 압력은 0.1Torr∼2Torr로 한다.Then, as shown in FIG. 5, the Ta 2 O 5 film on the tantalum nitride film 32 by low pressure chemical vapor deposition using high dielectric materials Ta (OC 2 H 5 ) 5 and O 2 gas. Form 36. Here, the heating temperature of the wafer for forming the Ta 2 O 5 film 36 is maintained at 350 to 450 ° C., and the pressure in the reaction chamber is set to 0.1 Torr to 2 Torr.
이후, 상기 결과물을 Ta2O5의 막질강화와 Ta2O5막내 산소 공간, 카본 계열의 불순물 제거를 위하여 후처리를 실시하는데, 후처리 공정은 저온 O2내지 N2O 플라즈마 처리, 고온의 O2내지 N2O 열처리, UV-O3을 이용한 후처리 등이 있으며 Ta2O5의 증착 조건에 따라 단일 내지 이중의 후처리 공정을 실시하도록 한다.Since, in the practice of the working-up, the resultant to the impurity removal of Ta 2 O 5 film quality enhancement and Ta 2 O 5 N Oxygen space, carbon series of post-processing step is a low temperature O 2 to N 2 O plasma treatment, a high-temperature O 2 to N 2 O heat treatment, post-treatment using UV-O 3 and the like, and to perform a single to dual post-treatment process according to the deposition conditions of Ta 2 O 5 .
그리고, 후처리된 Ta2O5막(36)위에 통상의 제조 공정에 따라 TiN 내지 WN을 도포한 후에 식각 공정으로 이를 패터닝하여 상부전극(38)을 형성한다.Then, TiN to WN are coated on the post-treated Ta 2 O 5 film 36 according to a conventional manufacturing process, and then patterned by the etching process to form the upper electrode 38.
상기와 같은 제조 공정에 따라 본 발명의 커패시터는 하부전극(30)과 Ta2O5막(36)사이에 탄탈륨질화막(32)을 추가 형성함으로써 열역학적으로 900℃이상까지 반응없이 안정한 상태를 유지, 즉 고유전체 Ta2O5막으로의 확산형 계면(diffused interface)을 형성하여 하부 전극의 산화를 방지한다.According to the above manufacturing process, the capacitor of the present invention maintains a stable state without a reaction up to 900 ° C. or more by forming a tantalum nitride film 32 between the lower electrode 30 and the Ta 2 O 5 film 36. That is, a diffusion interface to the high dielectric Ta 2 O 5 film is formed to prevent oxidation of the lower electrode.
따라서, 본 발명에 따른 커패시터 제조방법을 이용하게 되면, 고유전율을 가지는 Ta2O5로유전체막을 증착하기 전에 탄탈륨질화막을 추가 형성하기 때문에 후속 열처리 공정에 의해 발생하는 하부전극의 산화를 방지하여 유전체막의 정전용량 및 누설전류 특성 등을 향상시킬 수 있는 효과가 있다.Therefore, when the capacitor manufacturing method according to the present invention is used, a tantalum nitride film is additionally formed before depositing a Ta 2 O 5 dielectric film having a high dielectric constant, thereby preventing oxidation of a lower electrode generated by a subsequent heat treatment process. There is an effect that can improve the capacitance and leakage current characteristics of the film.
또한 본 발명은 유전체막 형성전에 실시하는 전처리 공정을 스킵(skip)할 수 있어 제조 공정수를 줄일 수 있다.In addition, the present invention can skip the pretreatment step performed before forming the dielectric film, thereby reducing the number of manufacturing steps.
Claims (5)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072261A (en) * | 1983-09-28 | 1985-04-24 | Fujitsu Ltd | Semiconductor memory |
| JPH0563157A (en) * | 1991-09-05 | 1993-03-12 | Mitsubishi Electric Corp | Semiconductor device |
| JPH09246494A (en) * | 1996-03-01 | 1997-09-19 | Texas Instr Japan Ltd | Dielectric capacitor, dielectric memory device, and manufacturing method thereof |
| JPH11233723A (en) * | 1998-02-13 | 1999-08-27 | Sony Corp | Electronic element and its manufacturing method, dielectric capacitor and its manufacturing method, optical element and its manufacturing method |
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1998
- 1998-12-30 KR KR1019980062525A patent/KR20010008432A/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072261A (en) * | 1983-09-28 | 1985-04-24 | Fujitsu Ltd | Semiconductor memory |
| JPH0563157A (en) * | 1991-09-05 | 1993-03-12 | Mitsubishi Electric Corp | Semiconductor device |
| JPH09246494A (en) * | 1996-03-01 | 1997-09-19 | Texas Instr Japan Ltd | Dielectric capacitor, dielectric memory device, and manufacturing method thereof |
| JPH11233723A (en) * | 1998-02-13 | 1999-08-27 | Sony Corp | Electronic element and its manufacturing method, dielectric capacitor and its manufacturing method, optical element and its manufacturing method |
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