KR100504434B1 - Method of forming capacitor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, the method forms a lower electrode formed of a conductive layer in contact with a semiconductor device through a contact hole of an interlayer insulating film for inter-device insulation on a semiconductor substrate. An amorphous Ta ₂ O ₅ film is formed on the surface, and a nitride film is formed on the surface of the Ta ₂ O ₅ film by performing a nitriding process using a plasma nitriding process or an electric furnace / rapid heat process in an in situ process. And a manufacturing process for forming an upper electrode made of a conductive layer. Accordingly, the present invention prevents the oxidation of the lower electrode generated during the high temperature annealing process for crystallization of the amorphous Ta ₂ O ₅ film and insufficient oxygen injection by plasma-nitriding or rapid thermal nitriding the Ta ₂ O ₅ film surface. Capacities and capacitors can be improved.

Description

Method of manufacturing capacitor of semiconductor device {Method of forming capacitor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, when the dielectric film of the capacitor is formed of Ta ₂ O ₅ , which is a high dielectric material, the interfacial stability with the upper electrode of the film can be achieved.

In order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor decreases drastically, but the charge required for the operation of the memory device, that is, the capacitance secured in the unit area must be increased.

In order to secure a sufficient dielectric capacity of the capacitor, structural studies such as thinning of the dielectric film and increasing the effective surface area, and the dielectric film used as a conventional silicon oxide film, such as NO (Nitride-Oxide) structure or ONO (Oxide-Nitride-Oxide) structure or Ta Material studies are attempting to replace ₂ O ₅ or BST (BaSrTiO ₃ ). Moreover, in recent years, Ta ₂ O ₅ high-k dielectric film that can secure higher capacitance (dielectric constant = 20-25) than low dielectric film of NO and ONO, which has difficulty in securing capacitance, can be applied to devices with more than 256MD in the future. I'm using more.

1 is a vertical cross-sectional view showing a capacitor of a stack type structure having a high capacitance Ta ₂ O ₅ film according to the prior art.

Referring to this, in the conventional capacitor manufacturing process, the interlayer insulating layer 20 is formed after performing an element (not shown) process having a gate electrode and a source drain junction layer on the semiconductor substrate 10. Next, a contact hole (not shown) for exposing a predetermined portion of the semiconductor substrate, that is, an impurity diffusion region, is formed by an etching process using a contact mask, and after the doped polysilicon is formed to a predetermined thickness, photographs and etching are performed. The lower electrode 30 is formed by patterning it using a process.

In order to suppress oxidation of the lower electrode due to the subsequent high temperature annealing treatment, a nitride treatment process is performed on the surface of the lower electrode 30 so as to form a silicon nitride thin film (Si ₃ N ₄ ) 32 on the surface of the lower electrode 30. To form. In this case, the nitriding treatment process uses a plasma nitriding treatment or an electric furnace and a rapid thermal process.

Next, an amorphous Ta ₂ O ₅ thin film 34 is deposited on the silicon nitride thin film 32 as a high dielectric film. At this time, the Ta ₂ O ₅ thin film 34 has a Plasma Enhanced Chemical Vapor Deposition (PECVD) method having excellent thin film quality, or a Low Pressure Chemical Vapor Deposition having relatively low step coverage but low step quality. ) Method.

After the TiN thin film 36 is deposited on the Ta ₂ O ₅ thin film 34 as a conductive barrier by LPCVD or sputtering, a doped polysilicon film 38 is laminated thereon to form an upper electrode ( Form T).

However, 5TiN + 2Ta ₂ O ₅ → 5TiO ₂ + 4TaN + at a temperature above 687K (414 ° C) in the capacitor manufacturing process as described above. Reaction with N ₂ may lead to generation of TiO ₂ and deterioration of Ta ₂ O ₅ may occur. That is, due to this reaction, a dielectric material called TiO ₂ is formed at the interface between the dielectric film and the upper electrode to form a series capacitor with Ta ₂ O ₅ , thereby reducing the total capacitance. Also, due to the high leakage characteristic of TiO ₂ itself This results in an increase in the leakage current of the entire dielectric.

In addition, since the TiN thin film 36 formed by the LPCVD method generally uses TiCl ₄ and NH ₃ sources, a high temperature of 600 ° C. or higher is required for the decomposition of TiCl ₄ , and the actual deposition process requires Cl (chlorine) in the thin film. This is done at higher temperatures to control the concentration. This high temperature process can cause mutual diffusion of atoms between the Ta ₂ O ₅ film and the lower electrode, and by using a highly reactive NH ₃ gas, the reaction is activated in the gas phase in the chamber to generate a large amount of particles, resulting in uniformity of the film. Becomes weak, which in turn degrades the reliability of the capacitor.

2 is a vertical cross-sectional view showing a capacitor of a cylinder type structure having a high capacitance Ta ₂ O ₅ film according to the prior art and a lower electrode of an HSG.

Such a cylinder-type capacitor is a method for increasing the cross-sectional area of the lower electrode, when the HSG (Hemi Spherical Grain) method is used to perform the HSG process on the doped polysilicon film 30 'and the surface of the hemispherical uneven film 31 ') To form a lower electrode (B). The process is the same as described above.

On the other hand, in order for the TiN thin film 36 to act as a barrier from the upper doped polysilicon 38, the thickness of the TiN thin film 36 should be 200 to 400 kPa. The coverage is poor. As a result, voids are generated between the grains and the grains in the capacitor having the three-dimensional complex capacitor structure or the lower electrode to which the HSG method is applied. As a result, the characteristics of the capacitor are deteriorated.

An object of the present invention is to solve the problems of the prior art as described above, when using Ta ₂ O ₅ dielectric material in the capacitor manufacturing process, the surface of the Ta ₂ O ₅ film by plasma nitridation or rapid thermal nitriding to amorphous Ta ₂ The present invention provides a method of manufacturing a capacitor of a semiconductor device capable of improving the reliability of a capacitor while ensuring high capacitance by preventing oxidation of a lower electrode generated during a high temperature annealing process for crystallization of an O ₅ film and insufficient oxygen injection.

In order to achieve the above object, the present invention provides a method of manufacturing a capacitor including a lower electrode, an upper electrode thereon, and a high dielectric Ta ₂ O ₅ film inherent in the electrodes. Forming a lower electrode made of a conductive layer in contact with the semiconductor element through a contact hole of the insulating film, forming an amorphous Ta ₂ O ₅ film on the upper surface of the lower electrode, and plasma nitriding or electric furnace / Forming a nitride film on the surface of the Ta ₂ O ₅ film by performing a nitriding treatment process using a rapid thermal process, and forming an upper electrode formed of a conductive layer on the nitride film.

Plasma nitridation process for the formation of the thin nitride film according to the present invention is carried out in the NH ₃ , N ₂ / O ₂ or N ₂ O atmosphere which is a gas atmosphere containing nitrogen and a temperature condition of 200 ~ 400 ℃, an electric furnace and In the case of using the rapid thermal nitriding process, the annealing is performed in an NH ₃ , N ₂ / O _2, or N ₂ O atmosphere, which is a gas atmosphere containing 750 to 950 ° C. and a nitrogen atmosphere.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are vertical cross-sectional views sequentially showing a capacitor manufacturing process of a stack type structure according to an embodiment of the present invention. Referring to this, the capacitor manufacturing method of the present invention is as follows.

First, as shown in FIG. 3A, a semiconductor device (not shown) having a gate electrode and a source / drain is formed on the upper surface of the active region of the silicon substrate 10 as a semiconductor substrate, and USG is formed on the entire surface of the substrate 10. (Undoped Silicate Glass), a material selected from Boro Phospho Silicate Glass (BPSG), and SiON is deposited and a chemical mechanical polishing process is performed to form an interlayer insulating film 20. Then, in order to secure the cross-sectional area of the capacitor in contact with the active region of the substrate 10, that is, the drain region, the interlayer insulating layer 20 is selectively etched by photolithography and etching to form a contact hole (not shown). The manufacturing process of the lower electrode of a stack structure is performed in a contact hole. In this case, an HSG process is used to increase the planar area of the lower electrode. First, an amorphous doped silicon is deposited in the contact hole of the interlayer insulating film 20, and then the silicon layer is patterned into a cylindrical structure using an etching process. In the state below the crystallization temperature, an amorphous seed is grown on the surface in a hemispherical irregular shape to form the lower electrode 40 of the HSG structure. In addition, PH ₃ treatment is performed to supply sufficient P (phosphorus) to the lower electrode 40.

Then, NH ₃ atmosphere (or N ₂ / H ₂₎ using plasma in the temperature range of 200-400 ° C. in an in-situ process to prevent oxidation of the lower electrode during Ta ₂ O ₅ film deposition and subsequent heat treatment. , N ₂ O) to form a thin silicon nitride film 32 by nitriding the surface of the lower electrode 40. In the above process, a rapid thermal nitriding process may be performed at 750 ° C. to 950 ° C. for 1 minute to 30 minutes.

Next, as shown in FIG. 3B, an amorphous Ta ₂ O ₅ film 44 is formed on the silicon nitride film 42 by LPCVD using TaCl ₅ to Ta (OC ₂ H ₅ ) ₅ and O ₂ gas. To form.

Then, as shown in FIG. 3C, a thin nitride film 46 is formed on the post-processed Ta ₂ O ₅ film 44 to a thickness of 10 to 20 kPa, because the oxidation and charge conductivity of the upper electrode to be formed thereafter. This is to prevent the problem.

In this case, the thin nitride film 46 is formed by a plasma nitridation process through an in-situ process or a nitriding process using an electric furnace and a rapid thermal process, and the plasma nitridation process is a gas containing nitrogen and a temperature condition of 200 to 400 ° C. In an atmosphere of NH ₃ , N ₂ / O ₂ or N ₂ O, the electric furnace and the rapid thermal nitriding process are carried out at a temperature of 750 to 950 ° C. and a nitrogen atmosphere of NH ₃ , N ₂ / O. Annealing in a ₂ or N ₂ O atmosphere.

On the other hand, during the nitriding process, the amorphous Ta ₂ O ₅ film 44 is crystallized or subjected to dry oxidation or light oxidation in an in situ and cluster type in an O ₂ or N ₂ O atmosphere. Crystallize.

Subsequently, as shown in FIG. 3D, polysilicon doped with impurities as a conductive layer is deposited on the upper surface of the nitride film 46 and patterned by an etching process to form an upper electrode 48. At this time, the thickness of the upper electrode 48 is set to 1000 to 1500 mW.

As described above, since the present invention uses a plasma and rapid thermal nitriding process without the problem of step coverage and Cl contamination, it is possible to prevent oxidation of polysilicon, which is the lower electrode, during the deposition of the upper electrode, and an effective oxide film of 30 kPa or less. The thickness can be obtained to increase the capacitance of the capacitor.

This is because in the prior art, after depositing the dielectric Ta ₂ O ₅ film, a high temperature annealing treatment is performed to crystallize the amorphous film. Will be improved.

Incidentally, the present invention is used when a rapid thermal nitridation process Ta ₂ O ₅ film as well as to form a uniform nitride film on the surface of Ta ₂ O ₅ film is crystallized by a high temperature annealing effect can be obtained at the same time.

In addition, when the present invention is applied to a capacitor having a simple stack structure, not only can a capacitance of 25 fF / cell or more required in a 256-DRAM class or more can be obtained, but also high temperature annealing treatment of Ta ₂ O ₅ film can be performed in situ and cluster type. As a result, the cleaning process required at the time of ex-situ can be omitted, thereby shortening the manufacturing process.

1 is a vertical cross-sectional view showing a capacitor of a stack type structure having a high capacitance Ta ₂ O ₅ film according to the prior art,

2 is a vertical cross-sectional view showing a capacitor of a cylinder type structure having a high capacitance Ta ₂ O ₅ film according to the prior art and a lower electrode of an HSG;

3A to 3D are vertical cross-sectional views sequentially illustrating a capacitor manufacturing process of a stack type structure according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: silicon substrate 20: interlayer insulating film

40: lower electrode 42: silicon nitride film

44: Ta ₂ O ₅ Membrane 46: Nitride Thin Film

48: upper electrode

Claims (4)

In the manufacturing process of a capacitor consisting of a lower electrode, an upper electrode thereon and a high dielectric Ta ₂ O ₅ film inherent to the electrodes, Forming a lower electrode formed of a conductive layer on and in contact with the semiconductor device through a contact hole of an interlayer insulating film for insulating between devices; Forming a Ta ₂ O ₅ film on an upper surface of the lower electrode; In an in situ process, in a nitrogen atmosphere of NH ₃ or N _{2 /} O ₂ or N ₂ O, plasma nitriding or in a nitrogen atmosphere of NH ₃ or N _{2 /} O ₂ or N ₂ O Forming a nitride film on the surface of the Ta ₂ O ₅ film by performing a nitriding treatment process using an electric furnace / quick thermal process; And And forming an upper electrode formed of a conductive layer on the thin nitride film. The method of claim 1, The plasma nitridation process for forming the thin nitride film is carried out at a temperature of 200 ~ 400 ℃ a capacitor manufacturing method of a semiconductor device. The method of claim 1, And a thickness of the thin nitride film is 10 to 20 kW. The method of claim 1, An electric furnace and a rapid thermal nitriding process for forming the thin nitride film are annealed at a temperature condition of 750 ~ 950 ℃.