KR20010004215A - Input buffer of semiconductor memory device - Google Patents

Abstract

The present invention is to implement the input buffer of the semiconductor memory device to improve the productivity and the operation speed by reducing the area, the present invention for the input buffer of the semiconductor memory device, in response to the input signal and the reference voltage signal A differential amplifier for outputting a first output signal inverting and amplifying the input signal to its first output terminal and outputting a second output signal amplifying the input signal to its second output terminal; A first inversion and feedback unit which inverts the first output signal to generate a first internal input signal and amplifies the generation of the first internal input signal by feeding back the first internal input signal; A second inversion and feedback unit for inverting the second output signal to generate a second internal input signal and for feedbacking the second internal input signal to amplify the generation of the second internal input signal; A control unit for enabling or disabling the differential amplifier and the first and second inverting and feedback units in response to a clock signal; And a precharge unit configured to precharge the first and second output terminals of the differential amplifier part in response to the clock signal.

Description

Input buffer of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an input buffer of a semiconductor memory device for increasing an operation speed by outputting external input signals in synchronization with a clock signal.

In general, the cell density of memory devices is rapidly increasing with generation, and the cell area is increasing. As the functions for controlling the cell blocks are also complicated, the size of the control block is rapidly increasing, resulting in large chip sizes. It is increasing in width. Because of this, the length of bus lines that carry external input signals to internal cell blocks has also increased dramatically, and delays in metal bus lines are no longer negligible. On the other hand, in a plurality of semiconductor devices (hereinafter, referred to as "synchronous semiconductor devices") which operate in synchronization with an externally supplied clock signal clk, the clock signal is input to a clock signal input buffer (hereinafter referred to as "clock buffer"). In response to this, the internal clock generator generates an internal clock synchronized with the external clock signal so that other components of the semiconductor device operate in synchronization with the internal clock. The semiconductor memory device temporarily stores and stores an input buffer adapted to adjust its potential level and timing and an input signal conformed to the input buffer in order to receive a signal transmitted from an external source and convert it into a signal suitable for internal logic thereof. An input latch is provided.

1 is a conceptual block diagram of a conventional input buffer and latch circuit.

As shown, an external input signal in_ext is applied to the input buffer 130 through the electrostatic discharge protection unit 110, and is converted into internal signals in_b and / in_b in the input buffer 130 and delayed. When applied to the unit 150, the delayed signals in_d and / in_d are applied to the latch unit 170 so that the setup / hold time can be adjusted. The internal input signals in_int and / in_int applied to the internal core block in response to the internal clock signal clk_d. Is generated.

Looking at the operation of the conventional input buffer and latch circuit having the above configuration, such as control signals and address signals such as chip select signal cs, low address strobe signal ras, column address strobe signal cas, and write enable signal we When the external input signal in_ext is input through the input pad, respectively, instantaneous high voltage such as static electricity is transferred to the internal core block to prevent the internal circuit from being destroyed, and then passes through the electrostatic protection unit 110 and then at the corresponding input buffer 130. Received and acclimatized. Here, the term "adaptation" refers to a signal that can be recognized by the internal logic of the semiconductor device by level shifting or amplifying the potential level of external input signals to an appropriate potential level. Means. Therefore, depending on the input signal, there may be a signal that already has a potential level suitable for internal logic, and the input buffer only performs a normal electrostatic discharge, a protection function, and the like for such an external signal. Further, since details of the adaptation of the input signal are well known in the art, a detailed description thereof will be omitted herein.

The input signal in received from the corresponding buffer 130 is transferred to the latch unit 170 after a delay process for adjusting the setup / hold time in the delay unit 150.

Since the signals in_d and / in_d transmitted to the latch unit 170 need to synchronize the reception timing of these signals with an external clock, the internal clock signal clk_d generated by the internal clock generator is assigned to each latch. All are supplied to achieve the required synchronization.

However, although the internal clock signal is being operated faster and faster to operate at a high frequency, if the input signals in_d and / in_d that arrive at the internal clock signal arrive late, the internal clock signal may malfunction.

That is, conventionally, after passing through the input buffer, delay unit, and latch unit, the generated signals in_d and / in_d are synchronized to the internal clock. Therefore, when the frequency of the clock clk is increased, each delay of the input buffer, delay unit, and latch unit is increased. Since time inevitably occurs, there is a risk of malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide an input buffer of a semiconductor memory device having an increased operation speed by using a buffer circuit that simultaneously performs a buffering operation and a delay and latch operation. have.

1 is a conceptual block diagram of a conventional input buffer and latch circuit.

2 is a conceptual block diagram of an input buffer according to an embodiment of the present invention.

3 is a detailed circuit diagram of an input buffer according to an embodiment of the present invention.

4 is an operation timing diagram of FIG. 2;

* Explanation of symbols for the main parts of the drawings

310a: pull-up signal driver 310b: pull-down signal driver

330a: first inversion and feedback section 330b: second inversion and feedback section

350: differential amplifier

In accordance with another aspect of the present invention, an input buffer of a semiconductor memory device outputs a first output signal obtained by inverting and amplifying the input signal to its first output terminal in response to an input signal and a reference voltage signal. A differential amplifier for outputting a second output signal amplified by the input signal to a second output terminal of the second amplifier; A first inversion and feedback unit which inverts the first output signal to generate a first internal input signal and amplifies the generation of the first internal input signal by feeding back the first internal input signal; A second inversion and feedback unit for inverting the second output signal to generate a second internal input signal and for feedbacking the second internal input signal to amplify the generation of the second internal input signal; A control unit for enabling or disabling the differential amplifier and the first and second inverting and feedback units in response to a clock signal; And a precharge unit configured to precharge the first and second output terminals of the differential amplifier part in response to the clock signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a conceptual block diagram of an input buffer according to an embodiment of the present invention, in which an external input signal in_ext is applied to an input buffer 250 through an electrostatic discharge protection unit 210, and an internal clock signal. The clock signal clk_d and the reference voltage vref which have been delayed by clk are applied together to the input buffer 250 to generate internal input signals in_int and / in_int.

3 is a detailed circuit diagram of an input buffer 250 according to an embodiment of the present invention. The first output node inverts and amplifies the input signal to the first output node N31 in response to the input signal in and the reference voltage signal vref. A differential amplifier 350 for outputting a signal and outputting a second output node signal obtained by amplifying the input signal to its second output node N33, and inverting the first output node signal to the first internal input signal in_int A first inverting and returning unit 330a for amplifying the first internal input signal in_int and amplifying the generation of the first internal input signal in_int, and inverting the second output node signal to generate a second internal input signal. a second inversion and feedback unit 330b for generating / in_int and feedbacking the second internal input signal / in_int to amplify the generation of the second internal input signal / in_int, and the differential amplifier in response to a clock signal clk_d. 350 and the first inversion and feedback unit 330a and the second inversion The controller 310b for enabling or disabling the feedback unit 330b, and the first output terminal N31 and the second output terminal N33 of the differential amplifier 310b when the disable is performed in response to the clock signal clk_d. It consists of a precharge part 310a which occupies.

The precharge unit 310a receives the clock signal clk_d at a gate terminal and precharges the nodes N31 and N33 to a power voltage through a source-drain path, and supplies the clock signal clk_d to a gate terminal. The PMOS transistor PM33 is configured to equalize the nodes N31 and N33 upon receipt, and the control unit 310b is configured as an NMOS transistor NM31 that supplies a pull-down signal through a source-drain path upon receiving the clock signal clk_d.

The differential amplifier 350 receives the first output node signal through a gate terminal and pulls up a second output node N33 connected to a drain. The differential amplifier 350 receives the second output node signal through a gate and receives a drain. A PMOS transistor PM34 pulling up the connected first output node N31, an NMOS transistor NM35 applying the first output node signal to a gate terminal and pulling down the second output node N33 connected to a drain, and the second output node at a gate terminal An NMOS transistor NM34 that receives a signal and pulls down the first output node N31 connected to the drain; an NMOS transistor NM32 that supplies a pull-down signal to the NMOS transistor NM34 through a source-drain path when the input signal in is applied to a gate terminal; The reference voltage signal vref is applied to a gate terminal to solve the NMOS transistor NM35 through a source-drain path. It consists of an NMOS transistor NM33 that supplies a drive signal.

The first inversion and feedback unit 330a inverts the first output node signal and outputs the first internal input signal in_int, and receives the output of the inverter INV31 as a gate through the NMOS transistor NM31. NMOS transistor NM36 which amplifies the supplied pull-down signal to the inverter INV31.

Similarly, the second inverting and feedback unit 330b receives an inverter INV32 that inverts the second output node signal and outputs the second internal input signal / in_int, and receives the output of the inverter INV32 as a gate. The NMOS transistor NM37 converts and amplifies the pull-down signal supplied through the NMOS transistor NM31 to the inverter INV32.

Referring to the timing diagram of FIG. 4, the operation of the present invention having the above configuration will be described.

The operation cycle of the input buffer 250 is determined by the clock signal clk_d delayed by the internal clock clk. When the clock signal clk_d is applied as a logic “low”, the precharge unit 310a is activated to output the output node N31. When a precharge operation of N33 occurs and a logic "high" is applied, the controller 310b is activated to amplify the input data in by the differential amplifier 350 to output the internal input signals in_int and / in_int. .

At the falling edge of the clock signal clk_d, the PMOS transistors PM31 and PM32 are turned on to precharge the output nodes N31 and N33 to a logic " high ", and the PMOS transistor PM33 is turned on to the node. Equalizes N31 and N33.

In the first input operation, the precharge unit 310a is disabled at the rising edge of the clock signal clk_d so that the output nodes N31 and N33 are floated to a logic " high " NMOS transistors NM34 and NM35 are turned on, and the NMOS transistor NM31 of the controller 310b is turned on to supply a pull-down signal to the differential amplifier 350 so as to amplify an input signal.

The input signal in is applied to logic "high" to turn on the NMOS transistor NM32, and the reference voltage signal vref is applied to the intermediate voltage between the power supply voltage and the ground voltage to weakly turn on the NMOS transistor NM33. The driving force of the NMOS transistor NM32 turned on by is greater so that the first output node N31 falls to a logic "low", which turns on the PMOS transistor PM35 to maintain the second output node N33 "high". .

The first output node N31 is inverted by the inverter IN31 of the first latch and feedback unit 330a to generate the first internal input signal in_int as "high", which turns on the NMOS transistor NM36 to accelerate the transfer of data. Let's do it.

The node N33 is inverted by the inverter INV32 of the second latch and feedback unit 330b to output the second internal input signal / in_int as "low".

After the first input operation is completed, the clock clk_d becomes a logic " low " to precharge the output nodes N31 and N33 to " high " and the clock clk_d is activated to a logic " high "

In the case of the second input operation, the second output node N33 is applied by the NMOS transistor NM33 that is applied to the input signal in as "low" and the NAND gate NM32 is turned off and weakly turned on by the reference voltage signal vref. It slowly falls to logic "low", whereby node N31 remains "high".

The first output node N31 is inverted by the first inversion and feedback unit 330a to output the first internal input signal in_int as "low," and the second output is output by the second inversion and feedback unit 330b. The node N33 is inverted to output the second internal input signal / in_int as "high", which turns on the feedback NMOS transistor NM37 to accelerate the rise of the second internal input signal / in_int.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention eliminates the input latches present in the plurality of input buffers of the semiconductor memory device, thereby improving productivity by reducing the area, and enabling the input signal to be quickly enabled to increase the operation speed of the semiconductor memory device. have.

Claims (6)

In the input buffer of the semiconductor memory device, In response to an input signal and a reference voltage signal, output a first output signal obtained by inverting and amplifying the input signal to its first output terminal, and outputting a second output signal amplified by the input signal to its second output terminal; A differential amplifier; A first inversion and feedback unit which inverts the first output signal to generate a first internal input signal and amplifies the generation of the first internal input signal by feeding back the first internal input signal; A second inversion and feedback unit for inverting the second output signal to generate a second internal input signal and for feedbacking the second internal input signal to amplify the generation of the second internal input signal; A control unit for enabling or disabling the differential amplifier and the first and second inverting and feedback units in response to a clock signal; And A precharge unit configured to precharge the first and second output terminals of the differential amplifier part in response to the clock signal; A semiconductor memory device comprising a. The method of claim 1, The differential amplifier, A first PMOS transistor configured to receive the first output signal to a gate terminal and pull up a second output terminal connected to a drain; A second PMOS transistor configured to receive the second output signal to a gate terminal and pull up a first output terminal connected to a drain; A first NMOS transistor configured to receive the first output signal to a gate terminal and pull down a second output terminal connected to a drain; A second NMOS transistor configured to receive the second output signal to a gate terminal and pull down the first output terminal connected to a drain; A third NMOS transistor receiving the input signal through a gate terminal and supplying a pull-down signal to the second NMOS transistor through a source-drain path; And A fourth NMOS transistor supplied with the reference voltage signal to a gate terminal to supply a pull-down signal to the first NMOS transistor through a source-drain path; A semiconductor memory device comprising a. The method of claim 2, The first inversion and feedback unit, An inverter configured to invert the first output signal to generate the first internal input signal; And An NMOS transistor receiving the first internal input signal through a gate terminal and supplying a pull-down signal to the first output terminal through a source-drain path; A semiconductor memory device comprising a. The method of claim 2, The second inversion and feedback unit, An inverter configured to invert the second output signal to generate the second internal input signal; And An NMOS transistor receiving the second internal input signal through a gate terminal and supplying a pull-down signal to the second output terminal through a source-drain path; A semiconductor memory device comprising a. The method of claim 1, The control unit, And an NMOS transistor configured to enable or disable by supplying ground power to the differential amplifier and the first and second inverting and feedback parts through a source-drain path by receiving the clock signal through a gate terminal. A semiconductor memory device. The method of claim 5, The precharge unit, A first PMOS transistor configured to receive the clock signal to a gate terminal and precharge the first output terminal through a source-drain path; A second PMOS transistor receiving the clock signal through a gate terminal and precharging the second output terminal through a source-drain path; And A third PMOS transistor receiving the clock signal through a gate terminal and connecting the first output terminal and the second output terminal through a source-drain path; A semiconductor memory device comprising a.