KR20000059514A - A manufacturing method of wires for a semicontuctor device - Google Patents

Abstract

An interlayer insulating film is deposited to a thickness of 10,000 to 20,000 Å by a CVD method on a poly-intermetal insulating film on which a contact is formed of a material such as tungsten, and then the interlayer insulating film is etched to form a contact hole in a portion where wiring is to be formed. The titanium / titanium nitride film is deposited by sputtering to form a barrier layer, and a metal film such as tungsten, molybdenum, nickel, magnesium, gold, and silver is deposited by CVD, or tungsten, aluminum, molybdenum, nickel, gold, silver, or the like. After spin coating the liquid metal, it is cured to form a metal film. At the time of spin coating, micro-vibration of 100 to 1,000 KHz is applied to the rotating shaft or megasonic spray is applied. Thereafter, chemical and mechanical polishing are performed to form a wiring such that a thickness of about 10 to 50% of the thickness of the interlayer insulating film before polishing and a thickness of about 3,000 to 6,000 kPa are reduced.

Description

A wiring method of a semiconductor device {A MANUFACTURING METHOD OF WIRES FOR A SEMICONTUCTOR DEVICE}

The present invention relates to a method for forming wiring of a semiconductor element.

Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. In the multilayer wiring method, an interlayer insulating film is formed between the wirings and the wirings, and the two wirings are contacted through the contacts drilled through the interlayer insulating film. Therefore, the size of the semiconductor chip can be reduced because the planar space through which the wiring passes between the semiconductor elements is reduced.

Next, a method of forming a contact and a wiring of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a conventional method for forming a contact and wiring of a semiconductor device according to a process sequence.

As shown in FIG. 1A, a silicide film 20 such as silicon titanium (TiSi) is formed on a silicon substrate 10 on which semiconductor devices (not shown), trenches (not shown), and the like are formed. And a poly-metal interlayer insulating film 30 composed of a single film or a double film such as a tetraethyle orthosilicate (TEOS) film, a non-doped silicate glass (NSG) film, a borophosphosilicate glass (BPSG), and the like. As in, the poly-metal interlayer insulating film 30 is etched to form a contact hole (c).

As shown in FIG. 1C, titanium (Ti) or titanium nitride (TiN) is deposited thereon and then annealed to form an ohmic contact metal layer 40 to improve electrical contact properties.

Next, as illustrated in FIG. 1D, tungsten or the like is deposited by chemical vapor deposition (CVD) to form a metal film 50 for plug formation, and the metal film 50 is chemically and mechanically formed. Polishing or back etching is performed to form the contact pattern 51 as shown in FIG. 1E.

Next, as shown in FIG. 1F, an aluminum (Al) metal film for wiring is deposited and etched, and then the wiring 61 is formed through a cleaning process. The wiring 61 is electrically connected to the lower semiconductor element or the like through the contact 51.

In the method of forming a wiring of a semiconductor device according to the related art, a wiring etch defect such as a bridge or a short circuit is likely to occur, and a polymer may be generated during etching. In addition, since the aluminum wiring is exposed to the external environment such as the atmosphere or the chemical liquid during or after cleaning, corrosion or wiring loss may occur.

SUMMARY OF THE INVENTION An object of the present invention for solving the problems of the prior art is to provide a method for forming a wiring of a semiconductor device which prevents defects such as bridges and short circuits between wirings during wiring etching.

Another object of the present invention is to prevent the formation of a polymer when forming the wiring.

Another object of the present invention is to prevent corrosion or loss of wiring by an external environment.

1A to 1F are cross-sectional views illustrating a method of forming a wiring of a semiconductor device according to the prior art, according to a process sequence;

2A through 2D are cross-sectional views illustrating a method of forming a wiring of a semiconductor device in accordance with an embodiment of the present invention, in the order of a process.

In order to solve this problem, in the present invention, an interlayer insulating film having a contact hole exposing a contact metal part and a metal film formed on the interlayer insulating film are simultaneously chemically and mechanically polished and ground to form a wiring connected to the contact metal part.

In the method for forming a wiring of a semiconductor device according to an embodiment of the present invention, an interlayer insulating film having a first thickness is formed on the poly-intermetal insulating film, and the contact metal part is exposed to expose the contact hole for forming the wiring by etching the interlayer insulating film. Next, a metal film is formed on the interlayer insulating layer to be connected to the contact metal part through the contact hole. Thereafter, the metal film and the interlayer insulating film are ground by chemical and mechanical polishing to form wiring.

Here, the metal film can be deposited by chemical vapor deposition, in which case it is preferable to use a material such as tungsten, molybdenum, nickel, magnesium, gold or silver.

In addition, the metal film may be formed by spin coating and curing the liquid metal, and during spin coating, it is preferable to apply fine vibration with a frequency of 100 to 1,000 KHz to make the spin coating well. In this method, it is preferable to use aluminum, tungsten, molybdenum, nickel, silver or gold as the material of the metal film.

Chemical and mechanical polishing preferably removes about 10 to 50% of the first thickness of the interlayer insulating film, that is, 3,000 to 6,000 Pa.

In addition, the interlayer insulating film can be formed by a chemical vapor deposition method.

As described above, since the wiring of the semiconductor element is formed by chemical and mechanical polishing, defects such as bridges and short circuits between the wirings can be prevented, and corrosion and loss of the wiring by air or chemicals can be minimized.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

2A to 2D are cross-sectional views illustrating a method of forming wirings of a semiconductor device in accordance with an embodiment of the present invention, according to a process sequence.

First, the silicide film 20 and the poly-intermetallic insulating film on the silicon substrate 10 on which semiconductor elements (not shown), trenches (not shown), etc. are formed in the same manner as shown in FIGS. 1A to 1E. (32), barrier layer 41 and contact pattern 51 are formed.

Next, as shown in FIG. 2A, an interlayer insulating material is deposited on the contact pattern 51 and the poly-metal interlayer insulating film 32 to a thickness of 10,000 to 20,000 Å by CVD to form an interlayer insulating film 70.

As shown in FIG. 2B, the interlayer insulating layer 70 is etched to form contact holes for forming wiring. At this time, the contact pattern 51 is also exposed through the contact hole. The interlayer insulating film 71 through which such contact holes are drilled provides a wiring frame in a subsequent wiring forming process.

Next, a metal film for forming wirings and contacts is deposited on the interlayer insulating film 71 and into the contact holes by CVD. In this case, the metal film is formed of tungsten (W), molybdenum (Mo), nickel (Ni), magnesium (Mg), gold (Au), silver (Ag), or the like.

Meanwhile, the metal film may be formed by spin coating using liquid metals such as tungsten, aluminum, molybdenum, nickel, gold, and silver, and most metals used in the CVD method may be used as the material. . During spin coating, in order to easily coat the liquid metal liquid, 100 to 1,000 KHz of micro vibration is applied to the rotating shaft or a megasonic spray is performed. Thereafter, the coated metal film is cured through heat treatment.

Subsequently, chemical-mechanical polishing (CMP) is performed to form the wiring 62 surrounded by the interlayer insulating film 72 as shown in FIG. 2C. At this time, the chemical and mechanical polishing is sufficiently polished so that the thickness of the interlayer insulating film (reference numeral 71 of FIG. 2B) before polishing is reduced by about 10 to 50% of the thickness of 5,000 to 15,000 kPa and about 3,000 to 6,000 kPa. 2b, the upper metal layer and the barrier layer are removed, leaving only the metal layer and the barrier layer inside the contact. In this process, bridges and short circuits occurring between the wirings 62 are eliminated.

Next, as shown in FIG. 2D, an interlayer insulating film 80 of 10,000 to 20,000 Å thickness is further formed so that the wiring 62 formed in the previous step is separated from the upper wiring to be formed in a subsequent process.

As described above, in the method for forming a wiring of a semiconductor device according to the present invention, an interlayer insulating film having a contact hole for forming a wiring is further formed on the poly-metal insulating film, and the method is sufficiently ground by chemical and mechanical polishing methods. Since the wiring is formed, defects such as bridges and short circuits between the wirings can be prevented, and the area of the wiring exposed to the outside becomes narrow, thereby minimizing corrosion or loss of the wiring due to air or chemicals. In addition, when forming a metal film by spin coating a liquid metal, defects such as voids and the like in the contact portion can be removed.

Claims (9)

In a semiconductor device comprising a poly-intermetal insulating film covering a silicon substrate and a contact hole for exposing a portion of the silicon substrate, and a contact metal portion formed in the contact hole, Forming an interlayer insulating film having a first thickness on the poly-intermetal insulating film, Forming a contact hole for etching the interlayer insulating layer to expose the contact metal part; Forming a metal film on the interlayer insulating film to be connected to the contact metal part through the contact hole; and Forming a wire by grinding the metal film and the interlayer insulating film by chemical and mechanical polishing methods Wire forming method of a semiconductor device comprising a. In claim 1, And forming the metal film by chemical vapor deposition. In claim 2, And the metal film is formed of tungsten, molybdenum, nickel, magnesium, gold, or silver. In claim 1, Forming the metal film, A method of forming a wiring in a semiconductor device, comprising the step of spin coating and hardening a liquid metal. In claim 4, A method for forming a wiring of a semiconductor device to which fine vibrations with a frequency of 100 to 1,000 KHz are applied during the spin coating. In claim 4, A method for forming a wiring of a semiconductor device using aluminum, tungsten, molybdenum, nickel, silver or gold as the material of the metal film. In claim 1, Wherein said chemical and mechanical polishing is performed until 10 to 50% of said first thickness of said interlayer insulating film is removed. In claim 1, A method for forming a wiring of a semiconductor device in which said first thickness of said interlayer insulating film is removed in the chemical and mechanical polishing process. In claim 1, And the interlayer insulating film is formed by a chemical vapor deposition method.