KR20000045464A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20000045464A KR20000045464A KR1019980062022A KR19980062022A KR20000045464A KR 20000045464 A KR20000045464 A KR 20000045464A KR 1019980062022 A KR1019980062022 A KR 1019980062022A KR 19980062022 A KR19980062022 A KR 19980062022A KR 20000045464 A KR20000045464 A KR 20000045464A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 트렌치를 이용한 소자분리공정에서 반도체기판 상부에 패드산화막과 질화막 및 유기무반사막의 적층구조를 형성하고, 상기 유기무반사막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴을 형성한 다음, 상기 감광막 패턴을 식각마스크로 상기 유기무반사막을 상기 감광막 패턴의 하부에 언더컷이 형성되도록 식각하고, 상기 감광막 패턴 및 유기무반사막을 식각마스크로 사용하여 상기 질화막과 패드산화막을 식각하면서 그 식각면에 폴리머를 증착시킨 다음, 상기 감광막 패턴 및 폴리머를 식각마스크로 사용하여 상기 반도체기판을 식각하여 트렌치를 형성하여 상기 트렌치 상부의 라운딩을 크게 형성하여 소자의 전기적 특성을 양호하게 하고 그에 따른 소자의 수율을 증가시키는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, in which a stacked structure of a pad oxide film, a nitride film, and an organic anti-reflective film is formed on an upper surface of a semiconductor substrate in a device isolation process using a trench, and the device isolation region is formed on the organic antireflective film. After forming a photoresist pattern that exposes a portion, the photoresist pattern is etched using an etch mask and the organic antireflection film is etched to form an undercut under the photoresist pattern, and the photoresist pattern and the organic antireflection film are used as an etching mask. After etching the pad oxide film, a polymer is deposited on the etched surface, and the semiconductor substrate is etched using the photoresist pattern and the polymer as an etch mask to form a trench to form a rounded upper portion of the trench to increase electrical characteristics of the device. To increase the yield of the device It is technology.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 트렌치를 이용한 소자분리공정에서 상기 트렌치의 상부를 크게 라운딩시켜 소자의 전기적 특성을 향상시켜 공정수율을 증가시키는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, in which the upper part of the trench is largely rounded to improve the electrical characteristics of the device in order to increase the process yield.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
또한, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process is difficult to bury the trench region as the design rule is reduced as well as the complexity of the process, it will be difficult to apply the trench isolation process when the design rule approaches 0.1 ㎛.
이하, 첨부된 도면을 참고로 종래기술에 대하여 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described with respect to the prior art.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 패드산화막(12)과 질화막(13)의 적층구조를 형성하고, 상기 질화막(13) 상부에 소자분리 영역으로 예정된 부분을 노출시키는 감광막 패턴(14)을 형성한다. (도 1a참조)First, a stack structure of the pad oxide film 12 and the nitride film 13 is formed on the semiconductor substrate 11, and a photosensitive film pattern 14 is formed on the nitride film 13 to expose a predetermined portion as an isolation region. . (See FIG. 1A)
다음, 상기 감광막 패턴(14)을 식각마스크로 사용하여 상기 적층구조 및 소정 두께의 반도체기판(11)을 식각하여 트렌치(16)를 형성한다. 상기 식각공정시 상기 감광막 패턴의 상부에 폴리머(15)를 적층시켜 트렌치(16)의 상부가 라운드하게 형성되도록 한다.Next, using the photoresist pattern 14 as an etching mask, the stacked structure and the semiconductor substrate 11 having a predetermined thickness are etched to form the trench 16. During the etching process, the polymer 15 is stacked on the photoresist pattern so that the upper portion of the trench 16 is rounded.
그 다음, 상기 폴리머(15) 및 감광막 패턴(14)을 제거한다.Next, the polymer 15 and the photoresist pattern 14 are removed.
다음, 상기 트렌치(16)의 표면을 열산화시켜 희생산화막을 성장시킨 후 습식식각을 실시하여 제거함으로써 상기 트렌치 형성공정시 발생된 상기 트렌치 표면의 결함을 제거한다.Next, the surface of the trench 16 is thermally oxidized to grow a sacrificial oxide film, followed by wet etching to remove defects on the trench surface generated during the trench formation process.
그 후, 다시 열산화공정을 실시하여 상기 트렌치의 표면에 산화막을 형성한다.Thereafter, a thermal oxidation process is performed again to form an oxide film on the surface of the trench.
다음, 전체표면 상부에 상기 트렌치를 매립하는 산화막을 형성한다.Next, an oxide film filling the trench is formed on the entire surface.
그 다음, 상기 산화막을 상기 질화막을 식각방지막으로 사용하여 화학적기계적연마(chemical mechanical polishing, 이하 CMP 라함)공정을 실시하여 제거하여 소자분리절연막을 형성한다.Then, the oxide film is removed by performing a chemical mechanical polishing (CMP) process using the nitride film as an etch stop layer to form a device isolation insulating film.
다음, 소자분리영역과 반도체기판과의 단차를 줄이기 위하여 상기 소자분리절연막을 습식식각방법으로 제거한다.Next, in order to reduce the step difference between the device isolation region and the semiconductor substrate, the device isolation insulating film is removed by a wet etching method.
그 후, 상기 질화막을 제거한다.Thereafter, the nitride film is removed.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 트렌치의 상부를 라운딩하게 형성시키기 위하여 질화막 상부에 소자분리영역을 노출시키는 감광막 패턴을 형성한 다음, 상기 질화막을 식각하고 인시튜(in-situ)로 반도체기판을 식각하여 트렌치를 형성하는데, 이때, 상기 질화막의 측벽에 폴리머가 발생되어 감광막 패턴과 질화막의 측벽에 증착된다. 따라서, 트렌치를 형성하기 위한 식각공정시 폴리머가 증착되어 있는 부분은 식각장벽이 되어 트렌치의 상부가 라운딩된다. 그러나 트렌치의 측벽에 증착되는 폴리머의 양이 적기 때문에 라운딩을 크게 형성할 수 없는 단점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, in order to form a rounded upper portion of a trench, a photoresist pattern is formed on the nitride layer to expose an isolation region, and then the nitride layer is etched and in-situ. The semiconductor substrate is etched to form a trench, in which a polymer is generated on the sidewall of the nitride film and deposited on the photoresist pattern and the sidewall of the nitride film. Therefore, in the etching process for forming the trench, the portion where the polymer is deposited becomes an etch barrier and the upper portion of the trench is rounded. However, since the amount of polymer deposited on the sidewalls of the trench is small, the rounding cannot be largely formed.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치를 이용한 소자분리공정에서 반도체기판 상부에 패드산화막과 질화막의 적층구조를 형성하고, 상기 질화막 상부에 유기무반사막을 형성한 다음, 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴을 식각마스크로 상기 유기무반사막을 식각하여 상기 감광막 패턴의 하부에 언더컷을 형성하고, 상기 질화막을 식각하되, 그 식각면에 폴리머를 증착시킨 후, 상기 감광막 패턴과 폴리머를 식각마스크로 상기 반도체기판을 식각하여 트렌치를 형성함으로써 상기 트렌치의 상부를 크게 라운딩시켜 소자의 전기적 특성 및 공정수율을 향상시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, in the device isolation process using a trench, a stacked structure of a pad oxide film and a nitride film is formed on the semiconductor substrate, an organic antireflection film is formed on the nitride film, and then a device isolation region. The organic anti-reflective film is etched with an etch mask to expose a predetermined portion to form an undercut under the photoresist pattern, the nitride film is etched, and a polymer is deposited on the etch surface, and then the photoresist pattern and It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a semiconductor is etched using a polymer etching mask to form a trench, thereby greatly rounding the upper portion of the trench to improve electrical characteristics and process yield of the device.
도 1a 내지 도 1d 는 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
◈ 도면의 주요부분에 대한 부호의 설명◈ Explanation of symbols for the main parts of the drawings
11, 21 : 반도체기판 12, 22 : 패드산화막11, 21: semiconductor substrate 12, 22: pad oxide film
13, 23 : 질화막 14 : 감광막 패턴13 and 23: nitride film 14: photosensitive film pattern
15, 26 : 폴리머 16, 27 : 트렌치15, 26: polymer 16, 27: trench
24 : 유기무반사막24: organic antireflection film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 패드산화막, 질화막 및 유기무반사막의 적층구조를 형성하는 공정과,Forming a stacked structure of a pad oxide film, a nitride film and an organic anti-reflective film on the semiconductor substrate;
상기 유기무반사막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the organic anti-reflective film to expose a portion of the organic light-reflective film as a device isolation region;
상기 감광막 패턴을 식각마스크로 사용하여 상기 유기무반사막을 식각하되, 소정 두께 언더컷되도록 식각하는 공정과,Using the photoresist pattern as an etch mask to etch the organic antireflective film, but to etch it to undercut a predetermined thickness;
상기 감광막 패턴 및 유기반사막을 식각마스크로 상기 질화막 및 패드산화막을 식각하되, 상기 적층구조의 측벽에 폴리머를 형성시키는 공정과,Etching the nitride layer and the pad oxide layer using the photoresist pattern and the organic reflection layer as an etch mask, and forming a polymer on sidewalls of the laminated structure;
상기 감광막 패턴 및 폴리머를 식각마스크로 사용하여 상기 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the semiconductor substrate using the photoresist pattern and the polymer as an etching mask;
상기 감광막 패턴, 폴리머 및 유기무반사막을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the photosensitive film pattern, the polymer, and the organic anti-reflective film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
먼저, 반도체기판(21) 상부에 패드산화막(22)과 질화막(23) 및 유기무반사막(organic anti reflective coating layer, 24)을 순차적으로 형성한다. 이때, 상기 유기무반사막(24)은 300 ∼ 1500Å 두께로 형성한다.First, a pad oxide film 22, a nitride film 23, and an organic anti reflective coating layer 24 are sequentially formed on the semiconductor substrate 21. At this time, the organic antireflection film 24 is formed to a thickness of 300 ~ 1500 ∼.
다음, 상기 유기무반사막(24) 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴(25)을 형성한다.Next, a photoresist pattern 25 is formed on the organic antireflective film 24 to expose a portion of the device isolation region.
다음, 상기 감광막 패턴(25)을 식각마스크로 사용하여 상기 유기무반사막(24)을 식각한다. 이때, 상기 유기무반사막(24)은 Cl2: O2가 1 : 1 ∼ 1 : 5 로 혼합된 Cl2/O2혼합가스를 식각가스로 사용하고, 20 ∼ 150%의 과도식각을 실시하여 상기 감광막 패턴(25) 하부에 언더컷을 형성하여 임계치수(critical dimension, CD) 이득이 10 ∼ 30㎚가 되도록 한다.Next, the organic antireflective film 24 is etched using the photoresist pattern 25 as an etching mask. In this case, the organic anti-reflective film 24 uses a Cl 2 / O 2 mixed gas mixed with Cl 2 : O 2 from 1: 1 to 1: 5 as an etching gas, and performs 20 to 150% transient etching. An undercut is formed under the photosensitive film pattern 25 so that a critical dimension (CD) gain is 10 to 30 nm.
그 다음, 상기 감광막 패턴(25) 및 유기무반사막(24)을 식각마스크로 사용하여 상기 질화막(23)을 식각한다. 이때, 과도식각공정을 실시하여 상기 반도체기판(21)이 20 ∼ 200Å 정도 손실되고, 상기 감광막 패턴(25), 유기무반사막(24), 질화막(23) 및 패드산화막(22)의 측벽에 폴리머(26)를 증착시킨다. 상기 질화막(23)은 CHF3/Ar 혼합가스를 식각가스로 사용하여 식각한다.Next, the nitride film 23 is etched using the photoresist pattern 25 and the organic antireflective film 24 as an etching mask. At this time, the semiconductor substrate 21 is lost by 20 to 200 kV by performing an over-etching process, and a polymer is formed on the sidewalls of the photoresist pattern 25, the organic antireflection film 24, the nitride film 23, and the pad oxide film 22. (26) is deposited. The nitride film 23 is etched using CHF 3 / Ar mixed gas as an etching gas.
다음, 상기 감광막 패턴(25) 및 폴리머(26)를 식각마스크로 사용하여 상기 반도체기판(21)을 식각하여 트렌치(27)를 형성하되, 상기 트렌치(27)는 Cl2/Ar혼합가스를 식각가스로 사용하여 상기 반도체기판(21)을 2000 ∼ 4000Å 식각하여 형성한다.Next, the semiconductor substrate 21 is etched using the photoresist pattern 25 and the polymer 26 as an etch mask to form a trench 27, wherein the trench 27 etches the Cl 2 / Ar mixed gas. The semiconductor substrate 21 is etched by 2000 to 4000 microns using gas.
그 다음, 상기 감광막 패턴(25), 폴리머(26) 및 유기무반사막(24)을 O2플라즈마를 사용하여 제거한 후, BOE(buffered oxide etchant)용액을 사용하여 세정공정을 실시한다.Next, the photoresist pattern 25, the polymer 26, and the organic antireflection film 24 are removed using an O 2 plasma, and then a cleaning process is performed using a buffered oxide etchant (BOE) solution.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 트렌치를 이용한 소자분리공정에서 반도체기판 상부에 패드산화막과 질화막 및 유기무반사막의 적층구조를 형성하고, 상기 유기무반사막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막 패턴을 형성한 다음, 상기 감광막 패턴을 식각마스크로 상기 유기무반사막을 상기 감광막 패턴의 하부에 언더컷이 형성되도록 식각하고, 상기 감광막 패턴 및 유기무반사막을 식각마스크로 사용하여 상기 질화막과 패드산화막을 식각하면서 그 식각면에 폴리머를 증착시킨 다음, 상기 감광막 패턴 및 폴리머를 식각마스크로 사용하여 상기 반도체기판을 식각하여 트렌치를 형성하여 상기 트렌치 상부의 라운딩을 크게 형성하여 소자의 전기적 특성을 양호하게 하고 그에 따른 소자의 수율을 증가시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, in a device isolation process using a trench, a stacked structure of a pad oxide film, a nitride film, and an organic antireflection film is formed on the semiconductor substrate, and the device is separated on the organic antireflection film. After forming a photoresist pattern that exposes a predetermined portion to an area, the photoresist pattern is etched using an etch mask, and the organic antireflection film is etched to form an undercut under the photoresist pattern, and the photoresist pattern and the organic antireflection film are used as an etch mask. By depositing a polymer on the etching surface while etching the nitride film and the pad oxide film, using the photoresist pattern and the polymer as an etching mask, the semiconductor substrate is etched to form a trench to form a rounding of the upper portion of the trench. Improve the electrical properties of It has the advantage of increasing the yield.
Claims (8)
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| KR1019980062022A KR20000045464A (en) | 1998-12-30 | 1998-12-30 | Method for fabricating semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100687401B1 (en) * | 2004-06-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Device Separator Formation Method of Semiconductor Device |
| CN114284203A (en) * | 2021-12-13 | 2022-04-05 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing isolation structure with top rounded corner groove |
-
1998
- 1998-12-30 KR KR1019980062022A patent/KR20000045464A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100687401B1 (en) * | 2004-06-30 | 2007-02-27 | 주식회사 하이닉스반도체 | Device Separator Formation Method of Semiconductor Device |
| CN114284203A (en) * | 2021-12-13 | 2022-04-05 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing isolation structure with top rounded corner groove |
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