KR20000041751A - Circuit for delivering negative charge pumping voltage of semiconductor device - Google Patents

Abstract

PURPOSE: A circuit for delivering a negative charge pumping voltage in a semiconductor device is provided to maximize the efficiency of a charge pump by inserting resistance to the drain terminals of each pass transistor. CONSTITUTION: First and second resistance(R1,P2) are connected to the drain terminals of first and second transistors(P21,P22) for reducing the potentials of first and second nodes(K21,K22) lower than a junction breakdown voltage. Moreover, a third resistance(R3) is connected to the drain terminal of a fifth transistor(P25). Thus, the voltage falls sequentially by inserting the resistance to the drain terminals of each pass transistor. Moreover, the charge pump efficiency is maximized by obtaining a lower output voltage than a breakdown voltage of each pass transistor.

Description

Negative Charge Pumping Voltage Transfer Circuit of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a negative charge pumping voltage transfer circuit of a semiconductor device. In particular, a minimum voltage may be reduced by inserting a resistor between a junction and a node to obtain a voltage lower than a junction breakdown voltage. The present invention relates to a negative charge pumping voltage transfer circuit of a semiconductor device capable of maximizing efficiency of a charge pump.

1 is a circuit diagram illustrating a negative charge pumping voltage transfer circuit of a conventional semiconductor device, and FIGS. 4 (a) and 4 (b) illustrate input signals and potentials of main nodes when transferring a negative charge pumping voltage. This is a waveform diagram shown.

The pumped voltage V _NQP is input from the negative charge pump circuit 10, and the first to third clock signals CLK1 to CLK3 are supplied in a waveform as shown in FIG. 4A.

The first PMOS transistor P11 is driven according to the first clock signal CLK1 supplied through the first pumping capacitor C11 and receives the pumping voltage V _NQP supplied from the negative charge pump circuit 10. The second PMOS transistor P12 is driven according to the second clock signal CLK2 supplied through the second pumping capacitor C12 to the pumping voltage V _NQP supplied from the negative charge pump circuit 10 as an input. do. The first pass transistor P13 is connected between the drain terminal and the ground terminal Vss of the first PMOS transistor P11, and the second pass transistor is connected between the drain terminal and the ground terminal Vss of the second PMOS transistor P12. P14 is connected. Here, the first and second pass transistors P13 and P14 are configured using, for example, PMOS transistors whose gates are connected to the ground terminal Vss. On the other hand, the gate terminal of the first PMOS transistor P11 and the first node K11 which is the drain terminal of the second PMOS transistor P12 are connected to each other, and the gate terminal and the first PMOS of the second PMOS transistor P12 are connected to each other. The second node K12, which is the drain terminal of the transistor P11, is connected to each other.

The third PMOS transistor P15 is driven according to the potential of the second node K12 and receives the pumping voltage V _NQP supplied from the negative charge pump circuit 10 as an input. The third pass transistor P16 is connected between the drain terminal of the third PMOS transistor P15 and the ground terminal Vss. The third pass transistor P16 has, for example, a gate connected to the ground terminal Vss. It is configured using a PMOS transistor. In addition, a third pumping capacitor C13 for pumping a voltage induced in the drain terminal of the third PMOS transistor P15 is connected to the drain terminal of the third PMOS transistor P15 according to the third clock signal CLK3. have. A load capacitor C _load for outputting the pumped voltage is connected between the third node K13, which is an output terminal of the third pumping capacitor C13, and the ground terminal Vss.

The potentials of the first and second nodes K11 and K12 are determined by the coupling ratios of the gate capacitors and the junction capacitors and the pumping capacitors C ₁₁ and C ₁₂ by the first and second PMOS transistors P11 and P12. Lose.

Since the gate capacitor and the junction capacitor by the first and second PMOS transistors P11 and P12 are relatively small, the potentials of the first and second nodes K11 and K12 are first and second pass transistors P13 and P14. ) drain junction breakdown voltage (= V _BD -15) is lowered to (K11 and K12 of the V _BD of Fig. 4).

The third PMOS transistor P15 transfers the pumping voltage V _NQP supplied from the negative charge pump circuit to the maximum value of the third node K13, and the threshold voltage value of the second pass transistor P14 and the second node. The level is determined in accordance with the potential of K12. When the junction breakdown voltage of the second pass transistor P14 is -V _BD , the potential of the third node K13 may not be transferred below -V _BD + Vt. The potential of the third node K13 is determined by the coupling ratio of the third pumping capacitor C13 and the load capacitor Cload by the third clock signal CLK3 from the maximum value transmitted. At this time, the coupling ratio K = C13 / (C13 + C _load ), and the potential of the third node K13 determined by this has a minimum value of ΔV (= Vcc × K). In this case, the minimum value of the third node K13 may not decrease below the junction breakdown voltage of the third pass transistor P16.

3 is a circuit diagram illustrating the transfer of a negative charge pumping voltage.

The output voltage V _NQP of the negative charge pump circuit is transferred to the program gate PGATE of the memory cell array. For this purpose, switching means P31 to P3n are required according to the size of the memory cell array. Each switching means P31 to P3n is controlled by the output voltages OUT to OUTn of the negative charge pumping voltage transfer circuit. The potential of the program gate PGATE may have a voltage increased by the threshold voltage Vtp of each switching means from the output voltage OUT of each negative charge pumping voltage transfer circuit. Therefore, in order for the potential of the program gate PGATE to be lowered, the output voltages OUT to OUTn of each negative charge pumping voltage transfer circuit must be sufficiently low. In order for the output voltage OUT of the negative charge pumping voltage transfer circuit to be sufficiently low, the junction breakdown voltage of the third pass transistor P16 must be lowered, and the potential of the second node K12 must be lowered. The junction breakdown voltage of the third pass transistor P16 and the potential of the second node K12 depend on the junction breakdown voltages of the first and second pass transistors P13 and P14. Therefore, it is essential to lower the junction breakdown voltage to deliver the minimum potential to the program gate (PGATE). As shown in FIG. 4, it can be seen that the minimum values of the first to third nodes K11 to K13 depend on the junction breakdown voltage. However, it is not easy to match the junction breakdown voltage in the process, and thus there is a problem in that the operating characteristics of the device are degraded.

Therefore, the present invention instantaneously causes a voltage drop by inserting a resistor into the drain terminal of each pass transistor that induces a negative charge pumped voltage, thereby obtaining an output voltage lower than the junction breakdown voltage of each pass transistor, thereby maximizing charge pump efficiency. It is an object of the present invention to provide a negative charge pumping voltage transfer circuit of a semiconductor device.

The negative charge pumping voltage transfer circuit of the semiconductor device according to the present invention for achieving the above object is a first transistor connected between the output terminal and the first node of the negative charge pump circuit and the gate electrode is connected to the second node, the negative charge Supplying first and second clock signals to a second transistor connected between an output terminal of the pump circuit and a second node, the gate electrode of which is connected to the first node, and to each gate electrode of the first and second transistors, respectively. First and second capacitors, a first element for increasing the voltage induced at the first node, a second element for increasing the voltage induced at the second node, and the first element and the ground terminal. A third transistor connected between the second transistor and the ground electrode and a second transistor connected between the second element and the ground terminal and grounded with the gate electrode; A fourth transistor connected between the four transistors, an output terminal and an output terminal of the negative charge pump circuit, a gate electrode connected to the first node, a third element for increasing a voltage induced at the output terminal, And a sixth transistor connected between the third element and the ground terminal and connected to the first node having the gate electrode grounded, and a third capacitor for supplying a third clock signal to the output terminal.

1 is a circuit diagram illustrating a negative charge pumping voltage transfer circuit of a conventional semiconductor device.

2 is a circuit diagram illustrating a negative charge pumping voltage transfer circuit of a semiconductor device according to the present invention.

3 is a circuit diagram illustrating the transfer of negative charge pumping voltage.

4 (a) and 4 (b) are waveform diagrams for explaining the potentials of the main node and the input signal when the negative charge pumping voltage is transmitted.

<Description of the symbols for the main parts of the drawings>

20: negative charge pump circuit

C21 to C23: first to third capacitor

P21, P22, P23, P24, P25, P26: first to sixth transistors

R1 to R3: first to third elements

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 2 is a circuit diagram illustrating a negative charge pumping voltage transfer circuit of a semiconductor device according to an exemplary embodiment of the present invention, and FIGS. 4A and 4B illustrate input signals and potentials of main nodes when transferring a negative charge pumping voltage. It is a waveform diagram shown to illustrate.

The pumped voltage V _NQP is input from the negative charge pump circuit 20, and the first to third clock signals CLK1 to CLK3 are supplied in a waveform as shown in FIG. 4A.

The first transistor P21 is driven according to the first clock signal CLK1 supplied through the first capacitor C21 and receives the pumping voltage V _NQP supplied from the negative charge pump circuit 20 as an input. The second transistor P22 is driven according to the second clock signal CLK2 supplied through the second capacitor C22 and receives the pumping voltage V _NQP supplied from the negative charge pump circuit 20. The first element R1 is connected to the drain terminal of the first transistor P21 to increase the voltage induced in the drain terminal of the first transistor P21 by the second clock signal CLK2. The second element R2 is connected to the drain terminal of the second transistor P22 to increase the voltage induced by the first clock signal CLK1 to the drain terminal of the second transistor P22. A third transistor P23 whose gate is grounded is connected between the first element R1 and the ground terminal Vss, and a fourth transistor P24 whose gate is grounded between the second element R2 and the ground terminal Vss. ) Is connected. Here, the first to fourth transistors P21 to P24 are configured using, for example, PMOS transistors, and the first and second elements R1 and R2 are configured using resistance elements. On the other hand, the gate terminal of the first transistor P21 and the first node K21 which is the drain terminal of the second transistor P22 are connected to each other, and the gate terminal of the second transistor P22 and the first transistor P21 are connected to each other. The second node K22, which is a drain terminal of, is connected to each other.

The fifth transistor P25 is driven according to the potential of the second node K22 and receives the pumping voltage V _NQP supplied from the negative charge pump circuit 20 as an input. A third element R3 is connected to the drain terminal of the fifth transistor P25, and a sixth transistor P26 having a gate grounded is connected between the third element R3 and the ground terminal Vss. The fifth and sixth transistors P25 and P26 are configured using, for example, PMOS transistors, and the third element R3 is configured using a resistor. In addition, a third capacitor C23 for pumping a voltage induced in the drain terminal of the fifth transistor P25 is connected to the drain terminal of the fifth transistor P25 in accordance with the third clock signal CLK3. A load capacitor C _load for outputting the pumped voltage is connected between the third node K23, which is an output terminal of the third capacitor C23, and the ground terminal Vss.

In the present invention, as shown in FIG. 2, the potentials of the first and second nodes K21 and K22 are lower than the junction breakdown voltage V _BD = -15. Resistance elements R1 and R2 are inserted between the drain terminal and the third and fourth transistors P23 and P24. Accordingly, even if breakdown occurs in the drain terminals of the third and fourth transistors P23 and P24, the first and the second are instantaneously by ΔV ₁ (i ₁ × R ₁ ) and ΔV ₂ (i ₂ × R ₂ ). The voltage was induced at the two nodes K21 and K22 so as to ensure a voltage by ΔV instantaneously.

The minimum value of the third node K23 is induced by the third clock signal CLK3, and the coupling ratio K = C3 / (C3 + Cload) between the third capacitor C23 and the load capacitor C _load and the power supply. According to the voltage Vcc value, it drops by (DELTA) V = Vcc * K. Since the breakdown voltage below the junction of the third node K23 cannot be maintained, a resistance element R3 is inserted between the drain terminal of the fifth transistor P25 and the sixth transistor P26 to prevent the sixth transistor P26. Even when breakdown occurs in the drain terminal, the voltage is momentarily induced to the third node K23 by ΔV (i ₃ × R ₃ ) so that the third node K23 has the minimum value V _BD ′ (FIG. 4, see K23 waveform). Accordingly, the negative pumping voltage V transmitted to the program gate PGATE by ensuring that the negative voltage of the gate voltage of each switching means P31 to P3n of FIG. 3 is instantaneously secured by ΔV (i ₃ × R ₃ ). _NQP ) voltage is also secured by ΔV.

As shown in FIG. 4 (b), the minimum voltage A 'of the third node K23, which is an output terminal of the negative charge pumping voltage transfer circuit according to the present invention, has a lower potential than that of the conventional A. As shown in FIG. . In addition, in the case of the voltage B 'applied to the program gate, the voltage B applied to the conventional program gate PGATE is negative in accordance with the present invention, compared with the voltage B higher than the negative charge pumping voltage V _NQP . When using the charge pumping voltage transfer circuit, it can be seen that a negative voltage corresponding to the negative charge pumping voltage V _NQP is applied to the program gate PGATE.

As described above, according to the present invention, an instantaneous voltage drop occurs by inserting a resistor into the drain terminal of each pass transistor for inducing a negative charge-pumped voltage to obtain an output voltage lower than the junction breakdown voltage of each pass transistor. The pump efficiency can be maximized, sufficient margin can be secured for the process variable change, and the yield of the device can be increased by improving characteristics of the erase operation of the semiconductor device.

Claims (3)

A first transistor connected between the output terminal of the negative charge pump circuit and the first node and having a gate electrode connected to the second node; A second transistor connected between an output terminal of a negative charge pump circuit and a second node, and a gate electrode connected to the first node; First and second capacitors for supplying first and second clock signals to respective gate electrodes of the first and second transistors, respectively; A first element for increasing a voltage induced at the first node; A second element for increasing a voltage induced at the second node; A third transistor connected between the first element and the ground terminal and having a gate electrode grounded; A fourth transistor connected between the second element and the ground terminal and having a gate electrode grounded; A fifth transistor connected between an output terminal and an output terminal of the negative charge pump circuit, and a gate electrode connected to the first node; A third element for increasing a voltage induced at the output terminal; A sixth transistor connected between the third element and the ground terminal and connected to a first node having a gate electrode grounded; And a third capacitor for supplying a third clock signal to the output terminal. The method of claim 1, And each of the first to third elements is formed of a resistance element. The method of claim 1, Each of the first to sixth transistors is a PMOS transistor, characterized in that the negative charge pumping voltage transfer circuit of the semiconductor device.